Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix some missing hard-coded paths #647

Browse Source
This commit is contained in:
James Stine 2024-09-18 12:47:08 -05:00
parent 13dc93c579
commit 9e88807ad5
3 changed files with 4 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bin/fparchtest.sh
View File

@ -13,8 +13,6 @@
# pip3 install git+https://github.com/riscv/riscv-isac.git # pip3 install git+https://github.com/riscv/riscv-isac.git
# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg # Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg
RISCVCTG=/home/harris/repos/riscv-ctg
#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32 #riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32
#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32 #riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32
riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug

7
linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~
View File

@ -1,7 +0,0 @@
FPGA_AXI_SDC_MODULE_VERSION = 1.0
FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc
FPGA_AXI_SDC_SITE_METHOD = local
FPGA_AXI_SDC_LICENSE = GPLv2
$(eval $(kernel-module))
$(eval $(generic-package))

4
site-setup.sh
View File

@ -30,6 +30,10 @@ export SYN_MW=/home/jstine/MW
export SYN_memory=/home/jstine/WallyMem/rv64gc/ export SYN_memory=/home/jstine/WallyMem/rv64gc/
#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/ #export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
# Environmental variables for FPGA
export RISCVCTG=/home/harris/repos/riscv-ctg
# GCC # GCC
if [ -z "$LD_LIBRARY_PATH" ]; then if [ -z "$LD_LIBRARY_PATH" ]; then
export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib