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csr comments
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@ -32,17 +32,31 @@
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module csr #(parameter
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module csr #(parameter
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MIP = 12'h344,
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MIP = 12'h344,
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SIP = 12'h144
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SIP = 12'h144) (
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic FlushM, FlushW,
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input logic FlushM, FlushW,
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input logic StallE, StallM, StallW,
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input logic StallE, StallM, StallW,
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input logic [31:0] InstrM,
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input logic [31:0] InstrM, // current instruction
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input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F,
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input logic [`XLEN-1:0] PCM, PCNext2F, // program counter, next PC going to trap/return logic
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input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, IntPendingM, InterruptM,
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input logic [`XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic CSRReadM, CSRWriteM, // read or write CSR
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input logic [63:0] MTIME_CLINT,
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input logic TrapM, // trap is occurring
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input logic InstrValidM, FRegWriteM, LoadStallD,
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input logic mretM, sretM, wfiM, // return or WFI instruction
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input logic IntPendingM, // at least one interrupt is pending and could occur if enabled
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input logic InterruptM, // interrupt is occurring
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input logic MTimerInt, // timer interrupt
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input logic MExtInt, SExtInt, // external interrupt (from PLIC)
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input logic MSwInt, // software interrupt
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input logic [63:0] MTIME_CLINT, // TIME value from CLINT
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input logic InstrValidM, // current instruction is valid
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input logic FRegWriteM, // writes to floating point registers change STATUS.FS
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input logic [4:0] SetFflagsM, // Set floating point flag bits in FCSR
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input logic [1:0] NextPrivilegeModeM, // STATUS bits updated based on next privilege mode
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input logic [1:0] PrivilegeModeW, // current privilege mode
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input logic [`LOG_XLEN-1:0] CauseM, // Trap cause
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input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode
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// inputs for performance counters
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input logic LoadStallD,
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input logic DirPredictionWrongM,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic RASPredPCWrongM,
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@ -52,66 +66,61 @@ module csr #(parameter
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input logic DCacheAccess,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic ICacheAccess,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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// outputs from CSRs
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input logic [`LOG_XLEN-1:0] CauseM,
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input logic SelHPTW,
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output logic [1:0] STATUS_MPP,
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output logic [1:0] STATUS_MPP,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
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output logic [`XLEN-1:0] MEDELEG_REGW,
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output logic [`XLEN-1:0] MEDELEG_REGW,
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output logic [`XLEN-1:0] SATP_REGW,
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output logic [`XLEN-1:0] SATP_REGW,
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output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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output logic STATUS_MIE, STATUS_SIE,
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output logic STATUS_MIE, STATUS_SIE,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
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output logic [1:0] STATUS_FS,
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output logic [1:0] STATUS_FS,
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input logic [4:0] SetFflagsM,
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output logic [2:0] FRM_REGW,
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output logic [2:0] FRM_REGW,
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output logic [`XLEN-1:0] CSRReadValW, UnalignedPCNextF,
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//
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output logic IllegalCSRAccessM, BigEndianM
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output logic [`XLEN-1:0] CSRReadValW, // value read from CSR
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output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
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output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
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output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields
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);
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);
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localparam NOP = 32'h13;
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logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
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logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] CSRReadValM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] CSRReadValM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] CSRSrcM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] CSRSrcM;
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logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;
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logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
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logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW;
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logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW;
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logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW;
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logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW;
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logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
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logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
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logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
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logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
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logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
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logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
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logic WriteFRMM, WriteFFLAGSM;
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logic WriteFRMM, WriteFFLAGSM;
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logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
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logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
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logic [11:0] CSRAdrM;
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logic [11:0] CSRAdrM;
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logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
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logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM;
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logic InsufficientCSRPrivilegeM;
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logic IllegalCSRMWriteReadonlyM;
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logic IllegalCSRMWriteReadonlyM;
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logic [`XLEN-1:0] CSRReadVal2M;
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logic [`XLEN-1:0] CSRReadVal2M;
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logic [11:0] MIP_REGW_writeable;
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logic [11:0] MIP_REGW_writeable;
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logic [`XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
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logic [`XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
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logic MTrapM, STrapM;
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logic MTrapM, STrapM;
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logic [`XLEN-1:0] EPC;
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logic [`XLEN-1:0] EPC;
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logic RetM;
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logic RetM;
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logic SelMtvecM;
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logic SelMtvecM;
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logic [`XLEN-1:0] TVecAlignedM;
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logic [`XLEN-1:0] TVecAlignedM;
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logic InstrValidNotFlushedM;
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logic InstrValidNotFlushedM;
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// only valid unflushed instructions can access CSRs
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// MTVAL
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// MTVAL: gets value from PC, Instruction, or load/store address
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///////////////////////////////////////////
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///////////////////////////////////////////
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always_comb
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always_comb
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if (InterruptM) NextFaultMtvalM = 0;
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if (InterruptM) NextFaultMtvalM = 0;
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else case (CauseM)
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else case (CauseM)
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12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
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12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
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2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
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2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
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@ -39,27 +39,27 @@ module csrc #(parameter
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TIME = 12'hC01,
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TIME = 12'hC01,
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TIMEH = 12'hC81
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TIMEH = 12'hC81
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) (
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic StallE, StallM,
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input logic StallE, StallM,
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input logic FlushM,
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input logic FlushM,
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input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
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input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
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input logic DirPredictionWrongM,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic PredictionInstrClassWrongM,
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input logic PredictionInstrClassWrongM,
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input logic [4:0] InstrClassM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic ICacheAccess,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [63:0] MTIME_CLINT,
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input logic [63:0] MTIME_CLINT,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM
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output logic IllegalCSRCAccessM
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);
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);
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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logic [4:0] CounterNumM;
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logic [4:0] CounterNumM;
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@ -30,20 +30,20 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module csri #(parameter
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module csri #(parameter
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MIE = 12'h304,
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MIE = 12'h304,
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MIP = 12'h344,
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MIP = 12'h344,
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SIE = 12'h104,
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SIE = 12'h104,
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SIP = 12'h144
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SIP = 12'h144
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) (
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic InstrValidNotFlushedM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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(* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt,
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(* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt,
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output logic [11:0] MIP_REGW, MIE_REGW,
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output logic [11:0] MIP_REGW, MIE_REGW,
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(* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
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(* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
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);
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);
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logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
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logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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@ -34,63 +34,63 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module csrm #(parameter
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module csrm #(parameter
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// Machine CSRs
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// Machine CSRs
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MVENDORID = 12'hF11,
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MVENDORID = 12'hF11,
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MARCHID = 12'hF12,
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MARCHID = 12'hF12,
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MIMPID = 12'hF13,
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MIMPID = 12'hF13,
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MHARTID = 12'hF14,
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MHARTID = 12'hF14,
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MCONFIGPTR = 12'hF15,
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MCONFIGPTR = 12'hF15,
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MSTATUS = 12'h300,
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MSTATUS = 12'h300,
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MISA_ADR = 12'h301,
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MISA_ADR = 12'h301,
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MEDELEG = 12'h302,
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MEDELEG = 12'h302,
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MIDELEG = 12'h303,
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MIDELEG = 12'h303,
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MIE = 12'h304,
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MIE = 12'h304,
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MTVEC = 12'h305,
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MTVEC = 12'h305,
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MCOUNTEREN = 12'h306,
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MCOUNTEREN = 12'h306,
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MSTATUSH = 12'h310,
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MSTATUSH = 12'h310,
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MCOUNTINHIBIT = 12'h320,
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MCOUNTINHIBIT = 12'h320,
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MSCRATCH = 12'h340,
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MSCRATCH = 12'h340,
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MEPC = 12'h341,
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MEPC = 12'h341,
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MCAUSE = 12'h342,
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MCAUSE = 12'h342,
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MTVAL = 12'h343,
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MTVAL = 12'h343,
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MIP = 12'h344,
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MIP = 12'h344,
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MTINST = 12'h34A,
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MTINST = 12'h34A,
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PMPCFG0 = 12'h3A0,
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PMPCFG0 = 12'h3A0,
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// .. up to 15 more at consecutive addresses
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// .. up to 15 more at consecutive addresses
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PMPADDR0 = 12'h3B0,
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PMPADDR0 = 12'h3B0,
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// ... up to 63 more at consecutive addresses
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// ... up to 63 more at consecutive addresses
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TSELECT = 12'h7A0,
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TSELECT = 12'h7A0,
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TDATA1 = 12'h7A1,
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TDATA1 = 12'h7A1,
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TDATA2 = 12'h7A2,
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TDATA2 = 12'h7A2,
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TDATA3 = 12'h7A3,
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TDATA3 = 12'h7A3,
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DCSR = 12'h7B0,
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DCSR = 12'h7B0,
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DPC = 12'h7B1,
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DPC = 12'h7B1,
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DSCRATCH0 = 12'h7B2,
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DSCRATCH0 = 12'h7B2,
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DSCRATCH1 = 12'h7B3,
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DSCRATCH1 = 12'h7B3,
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// Constants
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// Constants
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ZERO = {(`XLEN){1'b0}},
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ZERO = {(`XLEN){1'b0}},
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MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11),
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MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11),
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MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
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MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
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) (
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic InstrValidNotFlushedM,
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input logic CSRMWriteM, MTrapM,
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input logic CSRMWriteM, MTrapM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [`XLEN-1:0] CSRWriteValM,
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output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
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output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW,
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output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
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output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] MEDELEG_REGW,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] MEDELEG_REGW,
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(* mark_debug = "true" *) output logic [11:0] MIDELEG_REGW,
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(* mark_debug = "true" *) output logic [11:0] MIDELEG_REGW,
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// 64-bit registers in RV64, or two 32-bit registers in RV32
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// 64-bit registers in RV64, or two 32-bit registers in RV32
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//output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
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//output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW,
|
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW,
|
||||||
output logic WriteMSTATUSM, WriteMSTATUSHM,
|
output logic WriteMSTATUSM, WriteMSTATUSHM,
|
||||||
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
|
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW;
|
||||||
|
@ -45,7 +45,6 @@ module csrs #(parameter
|
|||||||
// Constants
|
// Constants
|
||||||
ZERO = {(`XLEN){1'b0}},
|
ZERO = {(`XLEN){1'b0}},
|
||||||
SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9)
|
SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9)
|
||||||
|
|
||||||
) (
|
) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic InstrValidNotFlushedM,
|
input logic InstrValidNotFlushedM,
|
||||||
@ -62,7 +61,7 @@ module csrs #(parameter
|
|||||||
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
|
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
|
||||||
output logic WriteSSTATUSM,
|
output logic WriteSSTATUSM,
|
||||||
output logic IllegalCSRSAccessM
|
output logic IllegalCSRSAccessM
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
// Supervisor mode CSRs sometimes supported
|
// Supervisor mode CSRs sometimes supported
|
||||||
@ -70,7 +69,7 @@ module csrs #(parameter
|
|||||||
logic WriteSTVECM;
|
logic WriteSTVECM;
|
||||||
logic WriteSSCRATCHM, WriteSEPCM;
|
logic WriteSSCRATCHM, WriteSEPCM;
|
||||||
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
|
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
|
||||||
|
|
||||||
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
|
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
|
||||||
|
@ -43,7 +43,7 @@ module csru #(parameter
|
|||||||
output logic [2:0] FRM_REGW,
|
output logic [2:0] FRM_REGW,
|
||||||
output logic WriteFRMM, WriteFFLAGSM,
|
output logic WriteFRMM, WriteFFLAGSM,
|
||||||
output logic IllegalCSRUAccessM
|
output logic IllegalCSRUAccessM
|
||||||
);
|
);
|
||||||
|
|
||||||
// Floating Point CSRs in User Mode only needed if Floating Point is supported
|
// Floating Point CSRs in User Mode only needed if Floating Point is supported
|
||||||
if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
|
if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
|
||||||
|
@ -32,13 +32,18 @@
|
|||||||
module privdec (
|
module privdec (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic StallM,
|
input logic StallM,
|
||||||
input logic [31:20] InstrM,
|
input logic [31:20] InstrM, // privileged instruction function field
|
||||||
input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM,
|
input logic PrivilegedM, // is this a privileged instruction (from IEU controller)
|
||||||
input logic [1:0] PrivilegeModeW,
|
input logic IllegalIEUInstrFaultM, // Not a legal IEU instruction
|
||||||
input logic STATUS_TSR, STATUS_TVM, STATUS_TW,
|
input logic IllegalFPUInstrM, // Not a legal FPU instruction
|
||||||
output logic IllegalInstrFaultM,
|
input logic IllegalCSRAccessM, // Not a legal CSR access
|
||||||
output logic EcallFaultM, BreakpointFaultM,
|
input logic [1:0] PrivilegeModeW, // current privilege level
|
||||||
output logic sretM, mretM, wfiM, sfencevmaM);
|
input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits
|
||||||
|
output logic IllegalInstrFaultM, // Illegal instruction
|
||||||
|
output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
|
||||||
|
output logic sretM, mretM,
|
||||||
|
output logic wfiM, sfencevmaM
|
||||||
|
);
|
||||||
|
|
||||||
logic IllegalPrivilegedInstrM;
|
logic IllegalPrivilegedInstrM;
|
||||||
logic WFITimeoutM;
|
logic WFITimeoutM;
|
||||||
|
Loading…
Reference in New Issue
Block a user