diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 37a41246a..374162a4d 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -32,17 +32,31 @@ module csr #(parameter MIP = 12'h344, - SIP = 12'h144 - ) ( + SIP = 12'h144) ( input logic clk, reset, input logic FlushM, FlushW, input logic StallE, StallM, StallW, - input logic [31:0] InstrM, - input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F, - input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, IntPendingM, InterruptM, - input logic MTimerInt, MExtInt, SExtInt, MSwInt, - input logic [63:0] MTIME_CLINT, - input logic InstrValidM, FRegWriteM, LoadStallD, + input logic [31:0] InstrM, // current instruction + input logic [`XLEN-1:0] PCM, PCNext2F, // program counter, next PC going to trap/return logic + input logic [`XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU + input logic CSRReadM, CSRWriteM, // read or write CSR + input logic TrapM, // trap is occurring + input logic mretM, sretM, wfiM, // return or WFI instruction + input logic IntPendingM, // at least one interrupt is pending and could occur if enabled + input logic InterruptM, // interrupt is occurring + input logic MTimerInt, // timer interrupt + input logic MExtInt, SExtInt, // external interrupt (from PLIC) + input logic MSwInt, // software interrupt + input logic [63:0] MTIME_CLINT, // TIME value from CLINT + input logic InstrValidM, // current instruction is valid + input logic FRegWriteM, // writes to floating point registers change STATUS.FS + input logic [4:0] SetFflagsM, // Set floating point flag bits in FCSR + input logic [1:0] NextPrivilegeModeM, // STATUS bits updated based on next privilege mode + input logic [1:0] PrivilegeModeW, // current privilege mode + input logic [`LOG_XLEN-1:0] CauseM, // Trap cause + input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode + // inputs for performance counters + input logic LoadStallD, input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, @@ -52,66 +66,61 @@ module csr #(parameter input logic DCacheAccess, input logic ICacheMiss, input logic ICacheAccess, - input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic [`LOG_XLEN-1:0] CauseM, - input logic SelHPTW, + // outputs from CSRs output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, - output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic STATUS_MIE, STATUS_SIE, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output logic [1:0] STATUS_FS, - output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], + output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], - - input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - output logic [`XLEN-1:0] CSRReadValW, UnalignedPCNextF, - output logic IllegalCSRAccessM, BigEndianM + // + output logic [`XLEN-1:0] CSRReadValW, // value read from CSR + output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns + output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level + output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields ); - localparam NOP = 32'h13; logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM; (* mark_debug = "true" *) logic [`XLEN-1:0] CSRReadValM; (* mark_debug = "true" *) logic [`XLEN-1:0] CSRSrcM; logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM; (* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM; - (* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW; logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW; - - logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; - logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; - logic CSRMWriteM, CSRSWriteM, CSRUWriteM; - logic WriteFRMM, WriteFFLAGSM; - + logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; + logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; + logic CSRMWriteM, CSRSWriteM, CSRUWriteM; + logic WriteFRMM, WriteFFLAGSM; logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; - - logic [11:0] CSRAdrM; - logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM; - logic IllegalCSRMWriteReadonlyM; + logic [11:0] CSRAdrM; + logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM; + logic InsufficientCSRPrivilegeM; + logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; - logic [11:0] MIP_REGW_writeable; + logic [11:0] MIP_REGW_writeable; logic [`XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM; - logic MTrapM, STrapM; - + logic MTrapM, STrapM; logic [`XLEN-1:0] EPC; - logic RetM; - logic SelMtvecM; + logic RetM; + logic SelMtvecM; logic [`XLEN-1:0] TVecAlignedM; - - logic InstrValidNotFlushedM; + logic InstrValidNotFlushedM; + + // only valid unflushed instructions can access CSRs assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW; /////////////////////////////////////////// - // MTVAL + // MTVAL: gets value from PC, Instruction, or load/store address /////////////////////////////////////////// always_comb - if (InterruptM) NextFaultMtvalM = 0; + if (InterruptM) NextFaultMtvalM = 0; else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 4e7870100..0982d990f 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -39,27 +39,27 @@ module csrc #(parameter TIME = 12'hC01, TIMEH = 12'hC81 ) ( - input logic clk, reset, - input logic StallE, StallM, - input logic FlushM, - input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM, - input logic DirPredictionWrongM, - input logic BTBPredPCWrongM, - input logic RASPredPCWrongM, - input logic PredictionInstrClassWrongM, - input logic [4:0] InstrClassM, - input logic DCacheMiss, - input logic DCacheAccess, - input logic ICacheMiss, - input logic ICacheAccess, - input logic [11:0] CSRAdrM, - input logic [1:0] PrivilegeModeW, - input logic [`XLEN-1:0] CSRWriteValM, - input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, - input logic [63:0] MTIME_CLINT, - output logic [`XLEN-1:0] CSRCReadValM, - output logic IllegalCSRCAccessM - ); + input logic clk, reset, + input logic StallE, StallM, + input logic FlushM, + input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM, + input logic DirPredictionWrongM, + input logic BTBPredPCWrongM, + input logic RASPredPCWrongM, + input logic PredictionInstrClassWrongM, + input logic [4:0] InstrClassM, + input logic DCacheMiss, + input logic DCacheAccess, + input logic ICacheMiss, + input logic ICacheAccess, + input logic [11:0] CSRAdrM, + input logic [1:0] PrivilegeModeW, + input logic [`XLEN-1:0] CSRWriteValM, + input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, + input logic [63:0] MTIME_CLINT, + output logic [`XLEN-1:0] CSRCReadValM, + output logic IllegalCSRCAccessM +); if (`ZICOUNTERS_SUPPORTED) begin:counters logic [4:0] CounterNumM; diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 6917da17d..751362f69 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -30,20 +30,20 @@ `include "wally-config.vh" module csri #(parameter - MIE = 12'h304, - MIP = 12'h344, - SIE = 12'h104, - SIP = 12'h144 - ) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRMWriteM, CSRSWriteM, - input logic [`XLEN-1:0] CSRWriteValM, - input logic [11:0] CSRAdrM, - (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, - output logic [11:0] MIP_REGW, MIE_REGW, - (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 - ); + MIE = 12'h304, + MIP = 12'h344, + SIE = 12'h104, + SIP = 12'h144 +) ( + input logic clk, reset, + input logic InstrValidNotFlushedM, + input logic CSRMWriteM, CSRSWriteM, + input logic [`XLEN-1:0] CSRWriteValM, + input logic [11:0] CSRAdrM, + (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, + output logic [11:0] MIP_REGW, MIE_REGW, + (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 +); logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index df2f48da3..4d14ef3fa 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -34,63 +34,63 @@ `include "wally-config.vh" module csrm #(parameter - // Machine CSRs - MVENDORID = 12'hF11, - MARCHID = 12'hF12, - MIMPID = 12'hF13, - MHARTID = 12'hF14, - MCONFIGPTR = 12'hF15, - MSTATUS = 12'h300, - MISA_ADR = 12'h301, - MEDELEG = 12'h302, - MIDELEG = 12'h303, - MIE = 12'h304, - MTVEC = 12'h305, - MCOUNTEREN = 12'h306, - MSTATUSH = 12'h310, - MCOUNTINHIBIT = 12'h320, - MSCRATCH = 12'h340, - MEPC = 12'h341, - MCAUSE = 12'h342, - MTVAL = 12'h343, - MIP = 12'h344, - MTINST = 12'h34A, - PMPCFG0 = 12'h3A0, - // .. up to 15 more at consecutive addresses - PMPADDR0 = 12'h3B0, - // ... up to 63 more at consecutive addresses - TSELECT = 12'h7A0, - TDATA1 = 12'h7A1, - TDATA2 = 12'h7A2, - TDATA3 = 12'h7A3, - DCSR = 12'h7B0, - DPC = 12'h7B1, - DSCRATCH0 = 12'h7B2, - DSCRATCH1 = 12'h7B3, - // Constants - ZERO = {(`XLEN){1'b0}}, - MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11), - MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable - ) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRMWriteM, MTrapM, - input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, - input logic [`XLEN-1:0] CSRWriteValM, - output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW, - (* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW, - output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, + // Machine CSRs + MVENDORID = 12'hF11, + MARCHID = 12'hF12, + MIMPID = 12'hF13, + MHARTID = 12'hF14, + MCONFIGPTR = 12'hF15, + MSTATUS = 12'h300, + MISA_ADR = 12'h301, + MEDELEG = 12'h302, + MIDELEG = 12'h303, + MIE = 12'h304, + MTVEC = 12'h305, + MCOUNTEREN = 12'h306, + MSTATUSH = 12'h310, + MCOUNTINHIBIT = 12'h320, + MSCRATCH = 12'h340, + MEPC = 12'h341, + MCAUSE = 12'h342, + MTVAL = 12'h343, + MIP = 12'h344, + MTINST = 12'h34A, + PMPCFG0 = 12'h3A0, + // .. up to 15 more at consecutive addresses + PMPADDR0 = 12'h3B0, + // ... up to 63 more at consecutive addresses + TSELECT = 12'h7A0, + TDATA1 = 12'h7A1, + TDATA2 = 12'h7A2, + TDATA3 = 12'h7A3, + DCSR = 12'h7B0, + DPC = 12'h7B1, + DSCRATCH0 = 12'h7B2, + DSCRATCH1 = 12'h7B3, + // Constants + ZERO = {(`XLEN){1'b0}}, + MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11), + MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable +) ( + input logic clk, reset, + input logic InstrValidNotFlushedM, + input logic CSRMWriteM, MTrapM, + input logic [11:0] CSRAdrM, + input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, + input logic [`XLEN-1:0] CSRWriteValM, + output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW, + (* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW, + output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, (* mark_debug = "true" *) output logic [`XLEN-1:0] MEDELEG_REGW, (* mark_debug = "true" *) output logic [11:0] MIDELEG_REGW, - // 64-bit registers in RV64, or two 32-bit registers in RV32 - //output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0], - output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, - output logic WriteMSTATUSM, WriteMSTATUSHM, - output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM - ); + // 64-bit registers in RV64, or two 32-bit registers in RV32 + //output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0], + output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, + output logic WriteMSTATUSM, WriteMSTATUSHM, + output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM +); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index afe96b258..7c67d09ab 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -45,7 +45,6 @@ module csrs #(parameter // Constants ZERO = {(`XLEN){1'b0}}, SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9) - ) ( input logic clk, reset, input logic InstrValidNotFlushedM, @@ -62,7 +61,7 @@ module csrs #(parameter (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM - ); +); // Supervisor mode CSRs sometimes supported @@ -70,7 +69,7 @@ module csrs #(parameter logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; -(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; + (* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index c0bf8bd5a..a5f6c5ee6 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -43,7 +43,7 @@ module csru #(parameter output logic [2:0] FRM_REGW, output logic WriteFRMM, WriteFFLAGSM, output logic IllegalCSRUAccessM - ); +); // Floating Point CSRs in User Mode only needed if Floating Point is supported if (`F_SUPPORTED | `D_SUPPORTED) begin:csru diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 69acc5227..db6b33b8b 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -32,13 +32,18 @@ module privdec ( input logic clk, reset, input logic StallM, - input logic [31:20] InstrM, - input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, - input logic [1:0] PrivilegeModeW, - input logic STATUS_TSR, STATUS_TVM, STATUS_TW, - output logic IllegalInstrFaultM, - output logic EcallFaultM, BreakpointFaultM, - output logic sretM, mretM, wfiM, sfencevmaM); + input logic [31:20] InstrM, // privileged instruction function field + input logic PrivilegedM, // is this a privileged instruction (from IEU controller) + input logic IllegalIEUInstrFaultM, // Not a legal IEU instruction + input logic IllegalFPUInstrM, // Not a legal FPU instruction + input logic IllegalCSRAccessM, // Not a legal CSR access + input logic [1:0] PrivilegeModeW, // current privilege level + input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits + output logic IllegalInstrFaultM, // Illegal instruction + output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs + output logic sretM, mretM, + output logic wfiM, sfencevmaM +); logic IllegalPrivilegedInstrM; logic WFITimeoutM;