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Fixed FResultSelM to select proper flags

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This commit is contained in:
David Harris 2021-10-27 11:02:42 -07:00
parent 31a2346c37
commit 9cfb8deaab
2 changed files with 16 additions and 16 deletions
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4
wally-pipelined/src/fpu/fpu.sv
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@ -41,7 +41,7 @@ module fpu (
output logic [`XLEN-1:0] FIntResM, // data to be written to integer register output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
output logic [4:0] SetFflagsM // FMA flags (to privileged unit) output logic [4:0] SetFflagsM // FPU flags (to privileged unit)
); );
//*** make everything FLEN at some point //*** make everything FLEN at some point
@ -267,7 +267,7 @@ module fpu (
// BEGIN MEMORY STAGE // BEGIN MEMORY STAGE
// FPU flag selection - to privileged // FPU flag selection - to privileged
mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM); mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
// M/W pipe registers // M/W pipe registers
flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);

28
wally-pipelined/testbench/tests.vh
View File

@ -671,28 +671,28 @@ string imperas32f[] = '{
string arch32f[] = '{ string arch32f[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
// tests repeated up here for basic sanity // tests repeated up here for basic sanity
//"rv32i_m/F/flw-align-01", "2010", // passes "rv32i_m/F/flw-align-01", "2010", // passes
//"rv32i_m/F/fmv.w.x_b25-01", "2090", // passes "rv32i_m/F/fmv.w.x_b25-01", "2090", // passes
"rv32i_m/F/fmadd_b14-01", "23d0", // fails test 1 "rv32i_m/F/fmadd_b14-01", "23d0", // fails test 1
"rv32i_m/F/fcvt.s.w_b25-01", "20a0", // fails test 3 "rv32i_m/F/fcvt.s.w_b25-01", "20a0", // fails test 3
// main tests // main tests
"rv32i_m/F/fadd_b1-01", "7220", // "rv32i_m/F/fadd_b1-01", "7220",
"rv32i_m/F/fadd_b10-01", "2270", // "rv32i_m/F/fadd_b10-01", "2270",
"rv32i_m/F/fadd_b11-01", "3fb40", // "rv32i_m/F/fadd_b11-01", "3fb40",
"rv32i_m/F/fadd_b12-01", "21b0", // "rv32i_m/F/fadd_b12-01", "21b0",
"rv32i_m/F/fadd_b13-01", "3660", // "rv32i_m/F/fadd_b13-01", "3660",
"rv32i_m/F/fadd_b2-01", "38b0", // "rv32i_m/F/fadd_b2-01", "38b0",
"rv32i_m/F/fadd_b3-01", "b320", // "rv32i_m/F/fadd_b3-01", "b320",
"rv32i_m/F/fadd_b4-01", "3480", // "rv32i_m/F/fadd_b4-01", "3480",
"rv32i_m/F/fadd_b5-01", "3700", // "rv32i_m/F/fadd_b5-01", "3700",
"rv32i_m/F/fadd_b7-01", "3520", // "rv32i_m/F/fadd_b7-01", "3520",
"rv32i_m/F/fadd_b8-01", "104a0", // "rv32i_m/F/fadd_b8-01", "104a0",
"rv32i_m/F/fclass_b1-01", "2090", "rv32i_m/F/fclass_b1-01", "2090",
"rv32i_m/F/fcvt.s.w_b25-01", "20a0", "rv32i_m/F/fcvt.s.w_b25-01", "20a0",
"rv32i_m/F/fcvt.s.w_b26-01", "3290", "rv32i_m/F/fcvt.s.w_b26-01", "3290",
"rv32i_m/F/fcvt.s.wu_b25-01", "20a0", "rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
"rv32i_m/F/fcvt.s.wu_b26-01", "3290", "rv32i_m/F/fcvt.s.wu_b26-01", "3290",
"rv32i_m/F/fcvt.w.s_b1-01", "2090", // "rv32i_m/F/fcvt.w.s_b1-01", "2090",
"rv32i_m/F/fcvt.w.s_b22-01", "20b0", "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
"rv32i_m/F/fcvt.w.s_b23-01", "20c0", "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
"rv32i_m/F/fcvt.w.s_b24-01", "21b0", "rv32i_m/F/fcvt.w.s_b24-01", "21b0",