From 9cfb8deaab36c93f98d72967b87a33c5ceb87846 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 27 Oct 2021 11:02:42 -0700
Subject: [PATCH] Fixed FResultSelM to select proper flags

---
 wally-pipelined/src/fpu/fpu.sv     |  4 ++--
 wally-pipelined/testbench/tests.vh | 28 ++++++++++++++--------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index 6ce894be4..91af05095 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -41,7 +41,7 @@ module fpu (
   output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
   output logic 		   FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
   output logic 		   IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
-  output logic [4:0] 	   SetFflagsM        // FMA flags (to privileged unit)
+  output logic [4:0] 	   SetFflagsM        // FPU flags (to privileged unit)
   );
 
   //*** make everything FLEN at some point
@@ -267,7 +267,7 @@ module fpu (
      // BEGIN MEMORY STAGE
      
      // FPU flag selection - to privileged
-     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM);
+     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
   
      // M/W pipe registers
      flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index fbe0d916c..cdebfcb2a 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -671,28 +671,28 @@ string imperas32f[] = '{
   string arch32f[] = '{
     `RISCVARCHTEST,
     // tests repeated up here for basic sanity
-    //"rv32i_m/F/flw-align-01", "2010", // passes
-    //"rv32i_m/F/fmv.w.x_b25-01", "2090", // passes
+    "rv32i_m/F/flw-align-01", "2010", // passes
+    "rv32i_m/F/fmv.w.x_b25-01", "2090", // passes
     "rv32i_m/F/fmadd_b14-01", "23d0", // fails test 1
     "rv32i_m/F/fcvt.s.w_b25-01", "20a0", // fails test 3
     // main tests
-    "rv32i_m/F/fadd_b1-01", "7220",
-    "rv32i_m/F/fadd_b10-01", "2270", 
-    "rv32i_m/F/fadd_b11-01", "3fb40",
-    "rv32i_m/F/fadd_b12-01", "21b0",
-    "rv32i_m/F/fadd_b13-01", "3660",
-    "rv32i_m/F/fadd_b2-01", "38b0",
-    "rv32i_m/F/fadd_b3-01", "b320",
-    "rv32i_m/F/fadd_b4-01", "3480",
-    "rv32i_m/F/fadd_b5-01", "3700",
-    "rv32i_m/F/fadd_b7-01", "3520",
-    "rv32i_m/F/fadd_b8-01", "104a0",
+    // "rv32i_m/F/fadd_b1-01", "7220",
+    // "rv32i_m/F/fadd_b10-01", "2270", 
+    // "rv32i_m/F/fadd_b11-01", "3fb40",
+    // "rv32i_m/F/fadd_b12-01", "21b0",
+    // "rv32i_m/F/fadd_b13-01", "3660",
+    // "rv32i_m/F/fadd_b2-01", "38b0",
+    // "rv32i_m/F/fadd_b3-01", "b320",
+    // "rv32i_m/F/fadd_b4-01", "3480",
+    // "rv32i_m/F/fadd_b5-01", "3700",
+    // "rv32i_m/F/fadd_b7-01", "3520",
+    // "rv32i_m/F/fadd_b8-01", "104a0",
     "rv32i_m/F/fclass_b1-01", "2090",
     "rv32i_m/F/fcvt.s.w_b25-01", "20a0",
     "rv32i_m/F/fcvt.s.w_b26-01", "3290",
     "rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
     "rv32i_m/F/fcvt.s.wu_b26-01", "3290",
-    "rv32i_m/F/fcvt.w.s_b1-01", "2090",
+//    "rv32i_m/F/fcvt.w.s_b1-01", "2090",
     "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
     "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
     "rv32i_m/F/fcvt.w.s_b24-01", "21b0",