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Signal renames.

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This commit is contained in:
Ross Thompson 2021-12-19 22:21:03 -06:00
parent 2f5de7eb82
commit 9c2fc30507
5 changed files with 31 additions and 32 deletions
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4
wally-pipelined/src/cache/dcache.sv vendored
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@ -28,7 +28,7 @@
module dcache module dcache
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallWtoDCache, input logic CPUBusy,
// cpu side // cpu side
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
@ -346,7 +346,7 @@ module dcache
.AtomicM, .AtomicM,
.ExceptionM, .ExceptionM,
.PendingInterruptM, .PendingInterruptM,
.StallWtoDCache, .CPUBusy,
.CacheableM, .CacheableM,
.IgnoreRequest, .IgnoreRequest,
.AHBAck, // from ahb .AHBAck, // from ahb

22
wally-pipelined/src/cache/dcachefsm.sv vendored
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@ -35,7 +35,7 @@ module dcachefsm
// hazard inputs // hazard inputs
input logic ExceptionM, input logic ExceptionM,
input logic PendingInterruptM, input logic PendingInterruptM,
input logic StallWtoDCache, input logic CPUBusy,
input logic CacheableM, input logic CacheableM,
// hptw inputs // hptw inputs
input logic IgnoreRequest, input logic IgnoreRequest,
@ -182,7 +182,7 @@ module dcachefsm
SelAdrM = 2'b10; SelAdrM = 2'b10;
DCacheStall = 1'b0; DCacheStall = 1'b0;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO; NextState = STATE_CPU_BUSY_FINISH_AMO;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -198,7 +198,7 @@ module dcachefsm
DCacheStall = 1'b0; DCacheStall = 1'b0;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -214,7 +214,7 @@ module dcachefsm
SetDirty = 1'b1; SetDirty = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -307,7 +307,7 @@ module dcachefsm
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
if(&MemRWM & AtomicM[1]) begin // amo write if(&MemRWM & AtomicM[1]) begin // amo write
SelAdrM = 2'b10; SelAdrM = 2'b10;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO; NextState = STATE_CPU_BUSY_FINISH_AMO;
end end
else begin else begin
@ -318,7 +318,7 @@ module dcachefsm
end end
end else begin end else begin
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -334,7 +334,7 @@ module dcachefsm
SelAdrM = 2'b10; SelAdrM = 2'b10;
CommittedM = 1'b1; CommittedM = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -361,7 +361,7 @@ module dcachefsm
STATE_CPU_BUSY: begin STATE_CPU_BUSY: begin
CommittedM = 1'b1; CommittedM = 1'b1;
SelAdrM = 2'b00; SelAdrM = 2'b00;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -376,7 +376,7 @@ module dcachefsm
SRAMWordWriteEnableM = 1'b0; SRAMWordWriteEnableM = 1'b0;
SetDirty = 1'b0; SetDirty = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO; NextState = STATE_CPU_BUSY_FINISH_AMO;
end end
else begin else begin
@ -412,7 +412,7 @@ module dcachefsm
STATE_UNCACHED_WRITE_DONE: begin STATE_UNCACHED_WRITE_DONE: begin
CommittedM = 1'b1; CommittedM = 1'b1;
SelAdrM = 2'b00; SelAdrM = 2'b00;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end
@ -425,7 +425,7 @@ module dcachefsm
CommittedM = 1'b1; CommittedM = 1'b1;
SelUncached = 1'b1; SelUncached = 1'b1;
SelAdrM = 2'b00; SelAdrM = 2'b00;
if(StallWtoDCache) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10; SelAdrM = 2'b10;
end end

4
wally-pipelined/src/lsu/lrsc.sv
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@ -29,7 +29,7 @@
module lrsc module lrsc
( (
input logic clk, reset, input logic clk, reset,
input logic FlushW, StallWtoDCache, input logic FlushW, CPUBusy,
input logic MemReadM, input logic MemReadM,
input logic [1:0] MemRWMtoLRSC, input logic [1:0] MemRWMtoLRSC,
output logic [1:0] MemRWMtoDCache, output logic [1:0] MemRWMtoDCache,
@ -57,7 +57,7 @@ module lrsc
end end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW); flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
end else begin // Atomic operations not supported end else begin // Atomic operations not supported
assign SquashSCW = 0; assign SquashSCW = 0;
assign MemRWMtoDCache = MemRWMtoLRSC; assign MemRWMtoDCache = MemRWMtoLRSC;

21
wally-pipelined/src/lsu/lsu.sv
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@ -27,7 +27,6 @@
`include "wally-config.vh" `include "wally-config.vh"
// *** Ross Thompson amo misalignment check?
module lsu module lsu
( (
input logic clk, reset, input logic clk, reset,
@ -100,8 +99,8 @@ module lsu
logic DTLBMissM; logic DTLBMissM;
logic DTLBWriteM; logic DTLBWriteM;
logic HPTWStall; logic HPTWStall;
logic [`PA_BITS-1:0] TranslationPAdr; logic [`PA_BITS-1:0] HPTWAdr;
//logic [`PA_BITS-1:0] TranslationPAdrM; //logic [`PA_BITS-1:0] HPTWAdrM;
logic HPTWRead; logic HPTWRead;
logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoDCache;
logic [1:0] MemRWMtoLRSC; logic [1:0] MemRWMtoLRSC;
@ -109,7 +108,7 @@ module lsu
logic [1:0] AtomicMtoDCache; logic [1:0] AtomicMtoDCache;
logic [`PA_BITS-1:0] MemPAdrNoTranslate; logic [`PA_BITS-1:0] MemPAdrNoTranslate;
logic [11:0] MemAdrE, MemAdrE_RENAME; logic [11:0] MemAdrE, MemAdrE_RENAME;
logic StallWtoDCache; logic CPUBusy;
logic MemReadM; logic MemReadM;
logic DataMisalignedM; logic DataMisalignedM;
logic DCacheStall; logic DCacheStall;
@ -262,7 +261,7 @@ module lsu
.DTLBMissM(DTLBMissM & ~PendingInterruptM), .DTLBMissM(DTLBMissM & ~PendingInterruptM),
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.HPTWReadPTE(ReadDataM), .HPTWReadPTE(ReadDataM),
.DCacheStall, .TranslationPAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM, .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw), .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
.WalkerLoadPageFaultM, .WalkerStorePageFaultM); .WalkerLoadPageFaultM, .WalkerStorePageFaultM);
@ -279,12 +278,12 @@ module lsu
// this is for the d cache SRAM. // this is for the d cache SRAM.
// turns out because we cannot pipeline hptw requests we don't need this register // turns out because we cannot pipeline hptw requests we don't need this register
//flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM); // delay TranslationPAdrM by a cycle //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
assign MemPAdrNoTranslate = SelPTW ? TranslationPAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; assign MemPAdrNoTranslate = SelPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0];
assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0]; assign MemAdrE = SelPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];
assign StallWtoDCache = SelPTW ? 1'b0 : StallW; assign CPUBusy = SelPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker. // always block interrupts when using the hardware page table walker.
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
@ -318,7 +317,7 @@ module lsu
// Move generate from lrsc to outside this module. // Move generate from lrsc to outside this module.
assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
.SquashSCW, .MemRWMtoDCache); .SquashSCW, .MemRWMtoDCache);
// *** BUG, this is most likely wrong // *** BUG, this is most likely wrong
@ -351,7 +350,7 @@ module lsu
dcache dcache(.clk(clk), dcache dcache(.clk(clk),
.reset(reset), .reset(reset),
.StallWtoDCache(StallWtoDCache), .CPUBusy(CPUBusy),
.MemRWM(MemRWMtoDCache), .MemRWM(MemRWMtoDCache),
.Funct3M(Funct3MtoDCache), .Funct3M(Funct3MtoDCache),
.Funct7M(Funct7M), .Funct7M(Funct7M),

12
wally-pipelined/src/mmu/hptw.sv
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@ -5,7 +5,7 @@
// Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification // Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification
// kmacsaigoren@hmc.edu 1 June 2021 // kmacsaigoren@hmc.edu 1 June 2021
// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment // implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
// adding support for terapage encoding, and for setting the TranslationPAdr using the new level, // adding support for terapage encoding, and for setting the HPTWAdr using the new level,
// adding the internal SvMode signal // adding the internal SvMode signal
// //
// Purpose: Page Table Walker // Purpose: Page Table Walker
@ -43,7 +43,7 @@ module hptw
output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [`XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs output logic [1:0] PageType, // page type to TLBs
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
output logic [`PA_BITS-1:0] TranslationPAdr, output logic [`PA_BITS-1:0] HPTWAdr,
output logic HPTWRead, // HPTW requesting to read memory output logic HPTWRead, // HPTW requesting to read memory
output logic [2:0] HPTWSize, // 32 or 64 bit access. output logic [2:0] HPTWSize, // 32 or 64 bit access.
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
@ -118,13 +118,13 @@ module hptw
default: NextPageType = PageType; default: NextPageType = PageType;
endcase endcase
// TranslationPAdr muxing // HPTWAdr muxing
if (`XLEN==32) begin // RV32 if (`XLEN==32) begin // RV32
logic [9:0] VPN; logic [9:0] VPN;
logic [`PPN_BITS-1:0] PPN; logic [`PPN_BITS-1:0] PPN;
assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
assign TranslationPAdr = {PPN, VPN, 2'b00}; assign HPTWAdr = {PPN, VPN, 2'b00};
assign HPTWSize = 3'b010; assign HPTWSize = 3'b010;
end else begin // RV64 end else begin // RV64
logic [8:0] VPN; logic [8:0] VPN;
@ -138,7 +138,7 @@ module hptw
endcase endcase
assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN; (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
assign TranslationPAdr = {PPN, VPN, 3'b000}; assign HPTWAdr = {PPN, VPN, 3'b000};
assign HPTWSize = 3'b011; assign HPTWSize = 3'b011;
end end
@ -211,7 +211,7 @@ module hptw
end else begin // No Virtual memory supported; tie HPTW outputs to 0 end else begin // No Virtual memory supported; tie HPTW outputs to 0
assign HPTWRead = 0; assign HPTWRead = 0;
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
assign TranslationPAdr = 0; assign HPTWAdr = 0;
assign HPTWSize = 3'b000; assign HPTWSize = 3'b000;
end end
endgenerate endgenerate