From 9c2fc305073d4116a26a7f6c52d22ac31a7e5b24 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 19 Dec 2021 22:21:03 -0600 Subject: [PATCH] Signal renames. --- wally-pipelined/src/cache/dcache.sv | 4 ++-- wally-pipelined/src/cache/dcachefsm.sv | 22 +++++++++++----------- wally-pipelined/src/lsu/lrsc.sv | 4 ++-- wally-pipelined/src/lsu/lsu.sv | 21 ++++++++++----------- wally-pipelined/src/mmu/hptw.sv | 12 ++++++------ 5 files changed, 31 insertions(+), 32 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 949e2eb94..1936705e5 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -28,7 +28,7 @@ module dcache (input logic clk, input logic reset, - input logic StallWtoDCache, + input logic CPUBusy, // cpu side input logic [1:0] MemRWM, @@ -346,7 +346,7 @@ module dcache .AtomicM, .ExceptionM, .PendingInterruptM, - .StallWtoDCache, + .CPUBusy, .CacheableM, .IgnoreRequest, .AHBAck, // from ahb diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 607b747fa..eb191b9a8 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -35,7 +35,7 @@ module dcachefsm // hazard inputs input logic ExceptionM, input logic PendingInterruptM, - input logic StallWtoDCache, + input logic CPUBusy, input logic CacheableM, // hptw inputs input logic IgnoreRequest, @@ -182,7 +182,7 @@ module dcachefsm SelAdrM = 2'b10; DCacheStall = 1'b0; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; SelAdrM = 2'b10; end @@ -198,7 +198,7 @@ module dcachefsm DCacheStall = 1'b0; LRUWriteEn = 1'b1; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end @@ -214,7 +214,7 @@ module dcachefsm SetDirty = 1'b1; LRUWriteEn = 1'b1; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end @@ -307,7 +307,7 @@ module dcachefsm LRUWriteEn = 1'b0; if(&MemRWM & AtomicM[1]) begin // amo write SelAdrM = 2'b10; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; end else begin @@ -318,7 +318,7 @@ module dcachefsm end end else begin LRUWriteEn = 1'b1; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end @@ -334,7 +334,7 @@ module dcachefsm SelAdrM = 2'b10; CommittedM = 1'b1; LRUWriteEn = 1'b1; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end @@ -361,7 +361,7 @@ module dcachefsm STATE_CPU_BUSY: begin CommittedM = 1'b1; SelAdrM = 2'b00; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end @@ -376,7 +376,7 @@ module dcachefsm SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; end else begin @@ -412,7 +412,7 @@ module dcachefsm STATE_UNCACHED_WRITE_DONE: begin CommittedM = 1'b1; SelAdrM = 2'b00; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end @@ -425,7 +425,7 @@ module dcachefsm CommittedM = 1'b1; SelUncached = 1'b1; SelAdrM = 2'b00; - if(StallWtoDCache) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdrM = 2'b10; end diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index 64bdbdd4d..a98b7dd5c 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -29,7 +29,7 @@ module lrsc ( input logic clk, reset, - input logic FlushW, StallWtoDCache, + input logic FlushW, CPUBusy, input logic MemReadM, input logic [1:0] MemRWMtoLRSC, output logic [1:0] MemRWMtoDCache, @@ -57,7 +57,7 @@ module lrsc end flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); - flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW); + flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); end else begin // Atomic operations not supported assign SquashSCW = 0; assign MemRWMtoDCache = MemRWMtoLRSC; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 096b1b85f..7b0f564e2 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -27,7 +27,6 @@ `include "wally-config.vh" -// *** Ross Thompson amo misalignment check? module lsu ( input logic clk, reset, @@ -100,8 +99,8 @@ module lsu logic DTLBMissM; logic DTLBWriteM; logic HPTWStall; - logic [`PA_BITS-1:0] TranslationPAdr; - //logic [`PA_BITS-1:0] TranslationPAdrM; + logic [`PA_BITS-1:0] HPTWAdr; + //logic [`PA_BITS-1:0] HPTWAdrM; logic HPTWRead; logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoLRSC; @@ -109,7 +108,7 @@ module lsu logic [1:0] AtomicMtoDCache; logic [`PA_BITS-1:0] MemPAdrNoTranslate; logic [11:0] MemAdrE, MemAdrE_RENAME; - logic StallWtoDCache; + logic CPUBusy; logic MemReadM; logic DataMisalignedM; logic DCacheStall; @@ -262,7 +261,7 @@ module lsu .DTLBMissM(DTLBMissM & ~PendingInterruptM), .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), - .DCacheStall, .TranslationPAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM, + .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM, .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw), .WalkerLoadPageFaultM, .WalkerStorePageFaultM); @@ -279,12 +278,12 @@ module lsu // this is for the d cache SRAM. // turns out because we cannot pipeline hptw requests we don't need this register - //flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM); // delay TranslationPAdrM by a cycle + //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; - assign MemPAdrNoTranslate = SelPTW ? TranslationPAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; - assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0]; - assign StallWtoDCache = SelPTW ? 1'b0 : StallW; + assign MemPAdrNoTranslate = SelPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; + assign MemAdrE = SelPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; + assign CPUBusy = SelPTW ? 1'b0 : StallW; // always block interrupts when using the hardware page table walker. assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; @@ -318,7 +317,7 @@ module lsu // Move generate from lrsc to outside this module. assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; - lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, + lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, .SquashSCW, .MemRWMtoDCache); // *** BUG, this is most likely wrong @@ -351,7 +350,7 @@ module lsu dcache dcache(.clk(clk), .reset(reset), - .StallWtoDCache(StallWtoDCache), + .CPUBusy(CPUBusy), .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv index fa8043d83..462ee7d38 100644 --- a/wally-pipelined/src/mmu/hptw.sv +++ b/wally-pipelined/src/mmu/hptw.sv @@ -5,7 +5,7 @@ // Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification // kmacsaigoren@hmc.edu 1 June 2021 // implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment -// adding support for terapage encoding, and for setting the TranslationPAdr using the new level, +// adding support for terapage encoding, and for setting the HPTWAdr using the new level, // adding the internal SvMode signal // // Purpose: Page Table Walker @@ -43,7 +43,7 @@ module hptw output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry - output logic [`PA_BITS-1:0] TranslationPAdr, + output logic [`PA_BITS-1:0] HPTWAdr, output logic HPTWRead, // HPTW requesting to read memory output logic [2:0] HPTWSize, // 32 or 64 bit access. output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults @@ -118,13 +118,13 @@ module hptw default: NextPageType = PageType; endcase - // TranslationPAdr muxing + // HPTWAdr muxing if (`XLEN==32) begin // RV32 logic [9:0] VPN; logic [`PPN_BITS-1:0] PPN; assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; - assign TranslationPAdr = {PPN, VPN, 2'b00}; + assign HPTWAdr = {PPN, VPN, 2'b00}; assign HPTWSize = 3'b010; end else begin // RV64 logic [8:0] VPN; @@ -138,7 +138,7 @@ module hptw endcase assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN; - assign TranslationPAdr = {PPN, VPN, 3'b000}; + assign HPTWAdr = {PPN, VPN, 3'b000}; assign HPTWSize = 3'b011; end @@ -211,7 +211,7 @@ module hptw end else begin // No Virtual memory supported; tie HPTW outputs to 0 assign HPTWRead = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; - assign TranslationPAdr = 0; + assign HPTWAdr = 0; assign HPTWSize = 3'b000; end endgenerate