Added some documenation about sparse-checkout for verilog-ethernet submodule.

addins/README.md

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+verilog-ethernet contains many ethernet devices.  Wally's synthesizable RVVI interface only requires a small subset of these files.
+To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info
+This will make the working directory only contain the necessary files.

addins/sparse-checkout

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+rtl/eth_mac_mii_fifo.v
+rtl/eth_mac_mii.v
+rtl/mii_phy_if.v
+rtl/ssio_ddr_in.v
+rtl/eth_mac_1g.v
+rtl/axis_gmii_rx.v
+rtl/lfsr.v
+rtl/eth_axis_tx.v
+rtl/mac_ctrl_tx.v
+rtl/axis_gmii_tx.v
+rtl/mac_ctrl_rx.v
+rtl/mac_pause_ctrl_tx.v
+rtl/mac_pause_ctrl_rx.v
+lib/axis/rtl/axis_async_fifo_adapter.v
+lib/axis/rtl/axis_adapter.v
+lib/axis/rtl/axis_async_fifo.v