From 9c1779a2d5ab986990be71e65e4f1cb3fff50ae0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 19 Jul 2024 13:11:48 -0500 Subject: [PATCH] Added some documenation about sparse-checkout for verilog-ethernet submodule. --- addins/README.md | 3 +++ addins/sparse-checkout | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 addins/README.md create mode 100644 addins/sparse-checkout diff --git a/addins/README.md b/addins/README.md new file mode 100644 index 000000000..ba04e05eb --- /dev/null +++ b/addins/README.md @@ -0,0 +1,3 @@ +verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. +To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info +This will make the working directory only contain the necessary files. diff --git a/addins/sparse-checkout b/addins/sparse-checkout new file mode 100644 index 000000000..76eadb284 --- /dev/null +++ b/addins/sparse-checkout @@ -0,0 +1,16 @@ +rtl/eth_mac_mii_fifo.v +rtl/eth_mac_mii.v +rtl/mii_phy_if.v +rtl/ssio_ddr_in.v +rtl/eth_mac_1g.v +rtl/axis_gmii_rx.v +rtl/lfsr.v +rtl/eth_axis_tx.v +rtl/mac_ctrl_tx.v +rtl/axis_gmii_tx.v +rtl/mac_ctrl_rx.v +rtl/mac_pause_ctrl_tx.v +rtl/mac_pause_ctrl_rx.v +lib/axis/rtl/axis_async_fifo_adapter.v +lib/axis/rtl/axis_adapter.v +lib/axis/rtl/axis_async_fifo.v