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Removed SelUncachedAdr

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This commit is contained in:
David Harris 2022-08-25 18:15:59 -07:00
parent f39e62eeea
commit 9bc62ce124
2 changed files with 4 additions and 5 deletions
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2
pipelined/src/lsu/busfsm.sv
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@ -51,7 +51,6 @@ module busfsm #(parameter integer LOGWPL)
output logic [1:0] HTRANS,
output logic CacheBusAck,
output logic BusCommitted,
output logic SelUncachedAdr,
output logic BufferCaptureEn);
logic UnCachedBusRead;
@ -126,5 +125,4 @@ module busfsm #(parameter integer LOGWPL)
assign CacheBusAck = 0;
assign BusCommitted = BusCurrState != STATE_BUS_READY;
assign SelUncachedAdr = 1;
endmodule

7
pipelined/src/lsu/lsu.sv
View File

@ -193,7 +193,6 @@ module lsu (
logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM;
logic [`LLEN-1:0] ReadDataWordMuxM;
logic IgnoreRequest;
logic SelUncachedAdr;
assign IgnoreRequest = IgnoreRequestTLB | TrapM;
// The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently
@ -225,6 +224,8 @@ module lsu (
logic [LOGBWPL-1:0] WordCount;
if(`DCACHE) begin : dcache
logic SelUncachedAdr;
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
@ -261,14 +262,14 @@ module lsu (
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite),
.SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn,
.HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
.CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM), .SelUncachedAdr);
.CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM));
// *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
end
end else begin: nobus // block: bus
assign {LSUHWDATA, SelUncachedAdr} = '0;
assign LSUHWDATA = '0;
assign ReadDataWordMuxM = LittleEndianReadDataWordM;
end