From 9bc62ce12407bcce742dd5dc233c8ca6829a5ecc Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 25 Aug 2022 18:15:59 -0700
Subject: [PATCH] Removed SelUncachedAdr

---
 pipelined/src/lsu/busfsm.sv | 2 --
 pipelined/src/lsu/lsu.sv    | 7 ++++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index a2e4ca89f..8096bfa62 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -51,7 +51,6 @@ module busfsm #(parameter integer LOGWPL)
    output logic [1:0]        HTRANS,
    output logic              CacheBusAck,
    output logic              BusCommitted,
-   output logic              SelUncachedAdr,
    output logic              BufferCaptureEn);
   
   logic 			   UnCachedBusRead;
@@ -126,5 +125,4 @@ module busfsm #(parameter integer LOGWPL)
 
   assign CacheBusAck = 0;
   assign BusCommitted = BusCurrState != STATE_BUS_READY;
-  assign SelUncachedAdr = 1;
 endmodule
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index cd2601af1..4571ccc77 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -193,7 +193,6 @@ module lsu (
   logic [`LLEN-1:0]    ReadDataWordM, LittleEndianReadDataWordM;
   logic [`LLEN-1:0]    ReadDataWordMuxM;
   logic                IgnoreRequest;
-  logic                SelUncachedAdr;
   assign IgnoreRequest = IgnoreRequestTLB | TrapM;
   
   // The LSU allows both a DTIM and bus with cache.  However, the PMA decoding presently 
@@ -225,6 +224,8 @@ module lsu (
     logic [LOGBWPL-1:0]   WordCount;
             
     if(`DCACHE) begin : dcache
+      logic                SelUncachedAdr;
+
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
         .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
@@ -261,14 +262,14 @@ module lsu (
         .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite), 
         .SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn,
         .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), 
-        .CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM), .SelUncachedAdr);
+        .CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM));
     
       // *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
       assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
       assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
     end
   end else begin: nobus // block: bus
-    assign {LSUHWDATA, SelUncachedAdr} = '0; 
+    assign LSUHWDATA = '0; 
     assign ReadDataWordMuxM = LittleEndianReadDataWordM;
   end