Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed SelUncachedAdr

Browse Source
This commit is contained in:
David Harris 2022-08-25 18:15:59 -07:00
parent f39e62eeea
commit 9bc62ce124
2 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/lsu/busfsm.sv
View File

@ -51,7 +51,6 @@ module busfsm #(parameter integer LOGWPL)
output logic [1:0] HTRANS, output logic [1:0] HTRANS,
output logic CacheBusAck, output logic CacheBusAck,
output logic BusCommitted, output logic BusCommitted,
output logic SelUncachedAdr,
output logic BufferCaptureEn); output logic BufferCaptureEn);
logic UnCachedBusRead; logic UnCachedBusRead;
@ -126,5 +125,4 @@ module busfsm #(parameter integer LOGWPL)
assign CacheBusAck = 0; assign CacheBusAck = 0;
assign BusCommitted = BusCurrState != STATE_BUS_READY; assign BusCommitted = BusCurrState != STATE_BUS_READY;
assign SelUncachedAdr = 1;
endmodule endmodule

7
pipelined/src/lsu/lsu.sv
View File

@ -193,7 +193,6 @@ module lsu (
logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM;
logic [`LLEN-1:0] ReadDataWordMuxM; logic [`LLEN-1:0] ReadDataWordMuxM;
logic IgnoreRequest; logic IgnoreRequest;
logic SelUncachedAdr;
assign IgnoreRequest = IgnoreRequestTLB | TrapM; assign IgnoreRequest = IgnoreRequestTLB | TrapM;
// The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently // The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently
@ -225,6 +224,8 @@ module lsu (
logic [LOGBWPL-1:0] WordCount; logic [LOGBWPL-1:0] WordCount;
if(`DCACHE) begin : dcache if(`DCACHE) begin : dcache
logic SelUncachedAdr;
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM), .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
@ -261,14 +262,14 @@ module lsu (
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite),
.SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn, .SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn,
.HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
.CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM), .SelUncachedAdr); .CacheBusAck(DCacheBusAck), .BusCommitted(BusCommittedM));
// *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian // *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
end end
end else begin: nobus // block: bus end else begin: nobus // block: bus
assign {LSUHWDATA, SelUncachedAdr} = '0; assign LSUHWDATA = '0;
assign ReadDataWordMuxM = LittleEndianReadDataWordM; assign ReadDataWordMuxM = LittleEndianReadDataWordM;
end end