Update icache interface

wally-pipelined/src/ifu/icache.sv

@@ -30,7 +30,8 @@ module icache(
   input  logic              StallF, StallD,
   input  logic              FlushD,
   // Fetch
-  input  logic [`XLEN-1:0] PCPF,
+  input  logic [`XLEN-1:12] UpperPCPF,
+  input  logic [11:0]       LowerPCF,
   input  logic [`XLEN-1:0]  InstrInF,
   output logic [`XLEN-1:0]  InstrPAdrF,
   output logic              InstrReadF,
@@ -48,6 +49,10 @@ module icache(
     logic             LastReadDataValidF;
     logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF;
 
+    // Temporary change to bridge the new interface to old behaviors
+    logic [`XLEN-1:0] PCPF;
+    assign PCPF = {UpperPCPF, LowerPCF};
+
     // This flop doesn't stall if StallF is high because we should output a nop
     // when FlushD happens, even if the pipeline is also stalled.
     flopr   #(1)  flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle);

wally-pipelined/src/ifu/ifu.sv

@@ -93,7 +93,12 @@ module ifu (
 
   // jarred 2021-03-14 Add instrution cache block to remove rd2
   assign PCPF = PCF; // Temporary workaround until iTLB is live
-  icache ic(clk, reset, StallF, StallD, FlushD, PCPF, InstrInF, ICacheInstrPAdrF, InstrReadF, CompressedF, ICacheStallF, InstrRawD);
+  icache ic(
+    .*,
+    .InstrPAdrF(ICacheInstrPAdrF),
+    .UpperPCPF(PCPF[`XLEN-1:12]),
+    .LowerPCF(PCF[11:0])
+  );
   // Prioritize the iTLB for reads if it wants one
   mux2 #(`XLEN) instrPAdrMux(ICacheInstrPAdrF, ITLBInstrPAdrF, ITLBMissF, InstrPAdrF);
 

wally-pipelined/testbench/testbench-imperas.sv

@@ -483,7 +483,7 @@ string tests32i[] = {
 
   // initialize the branch predictor
   initial begin
-    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
+    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);    
   end