From 99fa8beef3df485b4dda81bd528a925fb37d9c29 Mon Sep 17 00:00:00 2001
From: Jarred Allen <jaallen@g.hmc.edu>
Date: Mon, 22 Mar 2021 15:04:46 -0400
Subject: [PATCH] Update icache interface

---
 wally-pipelined/src/ifu/icache.sv             | 25 +++++++++++--------
 wally-pipelined/src/ifu/ifu.sv                |  7 +++++-
 .../testbench/testbench-imperas.sv            |  2 +-
 3 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv
index a108ebb0b..6ed1727d8 100644
--- a/wally-pipelined/src/ifu/icache.sv
+++ b/wally-pipelined/src/ifu/icache.sv
@@ -26,18 +26,19 @@
 `include "wally-config.vh"
 
 module icache(
-  input  logic             clk, reset,
-  input  logic             StallF, StallD,
-  input  logic             FlushD,
+  input  logic              clk, reset,
+  input  logic              StallF, StallD,
+  input  logic              FlushD,
   // Fetch
-  input  logic [`XLEN-1:0] PCPF,
-  input  logic [`XLEN-1:0] InstrInF,
-  output logic [`XLEN-1:0] InstrPAdrF,
-  output logic             InstrReadF,
-  output logic             CompressedF,
-  output logic             ICacheStallF,
+  input  logic [`XLEN-1:12] UpperPCPF,
+  input  logic [11:0]       LowerPCF,
+  input  logic [`XLEN-1:0]  InstrInF,
+  output logic [`XLEN-1:0]  InstrPAdrF,
+  output logic              InstrReadF,
+  output logic              CompressedF,
+  output logic              ICacheStallF,
   // Decode
-  output logic [31:0]     InstrRawD
+  output logic [31:0]       InstrRawD
 );
 
     logic             DelayF, DelaySideF, FlushDLastCycle, DelayD, DelaySideD;
@@ -48,6 +49,10 @@ module icache(
     logic             LastReadDataValidF;
     logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF;
 
+    // Temporary change to bridge the new interface to old behaviors
+    logic [`XLEN-1:0] PCPF;
+    assign PCPF = {UpperPCPF, LowerPCF};
+
     // This flop doesn't stall if StallF is high because we should output a nop
     // when FlushD happens, even if the pipeline is also stalled.
     flopr   #(1)  flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle);
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 99bf380fc..c92ff403a 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -93,7 +93,12 @@ module ifu (
 
   // jarred 2021-03-14 Add instrution cache block to remove rd2
   assign PCPF = PCF; // Temporary workaround until iTLB is live
-  icache ic(clk, reset, StallF, StallD, FlushD, PCPF, InstrInF, ICacheInstrPAdrF, InstrReadF, CompressedF, ICacheStallF, InstrRawD);
+  icache ic(
+    .*,
+    .InstrPAdrF(ICacheInstrPAdrF),
+    .UpperPCPF(PCPF[`XLEN-1:12]),
+    .LowerPCF(PCF[11:0])
+  );
   // Prioritize the iTLB for reads if it wants one
   mux2 #(`XLEN) instrPAdrMux(ICacheInstrPAdrF, ITLBInstrPAdrF, ITLBMissF, InstrPAdrF);
 
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index d4682dd20..8b128b17a 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -483,7 +483,7 @@ string tests32i[] = {
 
   // initialize the branch predictor
   initial begin
-    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
+    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);    
   end