mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Improved tlb and controller coverage; fixed exclusions on broken lines
This commit is contained in:
David Harris
parent
376ca68cbb
commit
98fa3a78dd
3
src/cache/cachefsm.sv
vendored
3
src/cache/cachefsm.sv
vendored
@ -106,8 +106,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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// outputs for the performance counters.
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) |
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(CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheMiss = CacheAccess & ~CacheHit;
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// special case on reset. When the fsm first exists reset the
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@ -182,7 +182,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
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((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4 & ENVCFG_CBE[3]) |
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(P.ZICBOM_SUPPORTED & ((InstrD[31:20] == 12'd0 & (ENVCFG_CBE[1:0] != 2'b00))) |
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(InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2) & ENVCFG_CBE[2]));
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// *** need to get with enable bits such as MENVCFG_CBZE
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assign AFunctD = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011);
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assign AMOFunctD = (InstrD[31:27] == 5'b00001) |
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(InstrD[31:27] == 5'b00000) |
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@ -57,8 +57,8 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
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adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
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// Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
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assign CacheableRegion = SelRegions[8] | SelRegions[7] | SelRegions[6];
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assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0; // exclusion-tag: unused-cachable
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assign CacheableRegion = SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-cachable
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assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0;
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// Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
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// I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent
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@ -17,7 +17,7 @@ all: $(OBJECTS)
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# Change many things if bit width isn't 64
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%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
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riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh -mabi=lp64 -mcmodel=medany \
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riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
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-nostartfiles -T../../examples/link/link.ld $<
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riscv64-unknown-elf-objdump -S $@ > $@.objdump
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riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
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@ -47,6 +47,13 @@ main:
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sc.w t0, a1, 0(a0)
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addi t0, t0, 1
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# test prefetch Hints (ori with destination x0)
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ori x0, x0, 0
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ori x0, x0, 1
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ori x0, x0, 2
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ori x0, x0, 3
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# Test illegal instructions are detected
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.word 0x80000033 // illegal R-type instruction
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.word 0x00007003 // illegal Load instruction
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@ -66,6 +73,34 @@ main:
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.word 0x60F0101B // Illegal BMU similar to count word
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.word 0x6080101B // Illegal BMU similar to count word
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.word 0x6030101B // Illegal BMU similar to count word
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.word 0x0000202F // Illegal similar to LR
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.word 0x1010202F // Illegal similar to LR
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.word 0x00402003 // illegal similar to CMO
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.word 0x00202003 // illegal similar to CMO
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.word 0xFF00302F // illegal Atomic instruction
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.word 0xFF00402F // illegal Atomic instruction
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.word 0x00000873 // illegal CSR instruction
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# Illegal CMO instructions because envcfg is 0 and system is in user Mode
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li a0, 0
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ecall # switch to user mode
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cbo.inval (x1)
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cbo.clean (x1)
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cbo.flush (x1)
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cbo.zero (x1)
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li a0, 3
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ecall # switch back to machine mode
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li x1, 0x50
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csrw menvcfg, x1
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csrw senvcfg, x1
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li a0, 0
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ecall # swtich to user mode
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cbo.inval (x2)
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cbo.clean (x3)
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cbo.flush (x1)
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j done
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@ -41,6 +41,7 @@ main:
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li a0, 1
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ecall
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li t4, 0x200000 # address step size
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li t0, 0x80215240 # Test NAPOT pages
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jal a1, looptest
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li t0, 0x80215240 # Test NAPOT pages
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@ -53,12 +54,14 @@ main:
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jal a1, looptest
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li t0, 0x40215240 # Test properly formed pages with 1 in PPN[3] that are not NAPOT
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jal a1, looptest
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li t4, 0x1000 # address step size
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li t0, 0x80216000 # Test NAPOT pages
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jal a1, looptest
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j done
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looptest:
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li t2, 0 # i = 0
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li t3, 33 # Max amount of Loops = 32
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li t4, 0x200000
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li t3, 35 # Max amount of Loops = 34
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li t5, 0x8082 # return instruction opcode
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loop: bge t2, t3, finished # exit loop if i >= loops
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@ -88,7 +91,7 @@ pagetable:
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.8byte 0x00000000200050C1 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN
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# Next page table at 0x80012000
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# Next page table at 0x80012000 for gigapage at 0x80000000
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.align 12
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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@ -125,6 +128,9 @@ pagetable:
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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# Leaf page table at 0x80013000 with NAPOT pages
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.align 12
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@ -197,7 +203,7 @@ pagetable:
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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# Next page table at 0x80014000: mega-sized, pointing to malformed NAPOT
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# Next page table at 0x80014000: mega-sized, pointing to malformed NAPOT for gigapage at 0xC9000000
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.align 12
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.8byte 0x00000000200054C1
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.8byte 0x00000000200054C1
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@ -234,6 +240,9 @@ pagetable:
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.8byte 0x00000000200054C1
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.8byte 0x00000000200054C1
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.8byte 0x00000000200054C1
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.8byte 0x00000000200054C1
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.8byte 0x00000000200054C1
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.8byte 0x00000000200054C1
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# Leaf page table at 0x80015000 with malformed NAPOT pages (wrong PPN) starting at 0xC0000000
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.align 12
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@ -284,7 +293,7 @@ pagetable:
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.8byte 0x80000000200000CF
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# Next page table at 0x80016000: mega-sized, pointing to properly formed PTE with 1 in PPN bit 3
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# Next page table at 0x80016000: mega-sized, pointing to properly formed PTE with 1 in PPN bit 3 for gigapage at 0x40000000
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.align 12
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.8byte 0x0000000020005CC1
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.8byte 0x0000000020005CC1
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@ -321,53 +330,54 @@ pagetable:
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.8byte 0x0000000020005CC1
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.8byte 0x0000000020005CC1
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.8byte 0x0000000020005CC1
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.8byte 0x0000000020005CC1
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.8byte 0x0000000020005CC1
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# Leaf page table at 0x80017000 with properly formed PTE with bit 4 of PPN set but no NAPOT
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.align 12
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#80000000
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200020CF
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.8byte 0x00000000200060CF
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.8byte 0x000000002000A0CF
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.8byte 0x000000002000E0CF
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