From 98fa3a78dd7fcabd25151750eeaa38694b954e05 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 31 Aug 2023 00:27:47 -0700 Subject: [PATCH] Improved tlb and controller coverage; fixed exclusions on broken lines --- src/cache/cachefsm.sv | 3 +- src/ieu/controller.sv | 1 - src/mmu/pmachecker.sv | 4 +-- tests/coverage/Makefile | 2 +- tests/coverage/ieu.S | 35 ++++++++++++++++++ tests/coverage/tlbNAPOT.S | 76 ++++++++++++++++++++++----------------- 6 files changed, 82 insertions(+), 39 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 124b92678..770579b67 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -106,8 +106,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. - assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | - (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW + assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW assign CacheMiss = CacheAccess & ~CacheHit; // special case on reset. When the fsm first exists reset the diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e923f1e3f..32fdba23e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -182,7 +182,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4 & ENVCFG_CBE[3]) | (P.ZICBOM_SUPPORTED & ((InstrD[31:20] == 12'd0 & (ENVCFG_CBE[1:0] != 2'b00))) | (InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2) & ENVCFG_CBE[2])); - // *** need to get with enable bits such as MENVCFG_CBZE assign AFunctD = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011); assign AMOFunctD = (InstrD[31:27] == 5'b00001) | (InstrD[31:27] == 5'b00000) | diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index ce129af51..587f54dbd 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -57,8 +57,8 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions); // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable - assign CacheableRegion = SelRegions[8] | SelRegions[7] | SelRegions[6]; - assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0; // exclusion-tag: unused-cachable + assign CacheableRegion = SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-cachable + assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0; // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly // I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index b2a2544d3..2f6002efc 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,7 +17,7 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh -mabi=lp64 -mcmodel=medany \ + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< riscv64-unknown-elf-objdump -S $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index cb0dae877..1e32a24ab 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -47,6 +47,13 @@ main: sc.w t0, a1, 0(a0) addi t0, t0, 1 + # test prefetch Hints (ori with destination x0) + ori x0, x0, 0 + ori x0, x0, 1 + ori x0, x0, 2 + ori x0, x0, 3 + + # Test illegal instructions are detected .word 0x80000033 // illegal R-type instruction .word 0x00007003 // illegal Load instruction @@ -66,6 +73,34 @@ main: .word 0x60F0101B // Illegal BMU similar to count word .word 0x6080101B // Illegal BMU similar to count word .word 0x6030101B // Illegal BMU similar to count word + .word 0x0000202F // Illegal similar to LR + .word 0x1010202F // Illegal similar to LR + .word 0x00402003 // illegal similar to CMO + .word 0x00202003 // illegal similar to CMO + .word 0xFF00302F // illegal Atomic instruction + .word 0xFF00402F // illegal Atomic instruction + .word 0x00000873 // illegal CSR instruction + + # Illegal CMO instructions because envcfg is 0 and system is in user Mode + li a0, 0 + ecall # switch to user mode + cbo.inval (x1) + cbo.clean (x1) + cbo.flush (x1) + cbo.zero (x1) + + li a0, 3 + ecall # switch back to machine mode + li x1, 0x50 + csrw menvcfg, x1 + csrw senvcfg, x1 + li a0, 0 + ecall # swtich to user mode + cbo.inval (x2) + cbo.clean (x3) + cbo.flush (x1) + + j done diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index f827d503b..282420be9 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -41,6 +41,7 @@ main: li a0, 1 ecall + li t4, 0x200000 # address step size li t0, 0x80215240 # Test NAPOT pages jal a1, looptest li t0, 0x80215240 # Test NAPOT pages @@ -53,12 +54,14 @@ main: jal a1, looptest li t0, 0x40215240 # Test properly formed pages with 1 in PPN[3] that are not NAPOT jal a1, looptest + li t4, 0x1000 # address step size + li t0, 0x80216000 # Test NAPOT pages + jal a1, looptest j done looptest: li t2, 0 # i = 0 - li t3, 33 # Max amount of Loops = 32 - li t4, 0x200000 + li t3, 35 # Max amount of Loops = 34 li t5, 0x8082 # return instruction opcode loop: bge t2, t3, finished # exit loop if i >= loops @@ -88,7 +91,7 @@ pagetable: .8byte 0x00000000200050C1 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN -# Next page table at 0x80012000 +# Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 @@ -125,6 +128,9 @@ pagetable: .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 # Leaf page table at 0x80013000 with NAPOT pages .align 12 @@ -197,7 +203,7 @@ pagetable: .8byte 0x800000002000E0CF .8byte 0x800000002000E0CF -# Next page table at 0x80014000: mega-sized, pointing to malformed NAPOT +# Next page table at 0x80014000: mega-sized, pointing to malformed NAPOT for gigapage at 0xC9000000 .align 12 .8byte 0x00000000200054C1 .8byte 0x00000000200054C1 @@ -234,6 +240,9 @@ pagetable: .8byte 0x00000000200054C1 .8byte 0x00000000200054C1 .8byte 0x00000000200054C1 + .8byte 0x00000000200054C1 + .8byte 0x00000000200054C1 + .8byte 0x00000000200054C1 # Leaf page table at 0x80015000 with malformed NAPOT pages (wrong PPN) starting at 0xC0000000 .align 12 @@ -284,7 +293,7 @@ pagetable: .8byte 0x80000000200000CF -# Next page table at 0x80016000: mega-sized, pointing to properly formed PTE with 1 in PPN bit 3 +# Next page table at 0x80016000: mega-sized, pointing to properly formed PTE with 1 in PPN bit 3 for gigapage at 0x40000000 .align 12 .8byte 0x0000000020005CC1 .8byte 0x0000000020005CC1 @@ -321,53 +330,54 @@ pagetable: .8byte 0x0000000020005CC1 .8byte 0x0000000020005CC1 .8byte 0x0000000020005CC1 + .8byte 0x0000000020005CC1 + .8byte 0x0000000020005CC1 # Leaf page table at 0x80017000 with properly formed PTE with bit 4 of PPN set but no NAPOT .align 12 #80000000 .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x00000000200060CF + .8byte 0x000000002000A0CF + .8byte 0x000000002000E0CF - \ No newline at end of file