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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Removed comments around commented code for verilator.
This commit is contained in:
parent
1bf57e3dd1
commit
987e5a5bf0
@ -247,9 +247,12 @@ module testbench;
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// strings, but uses a load double to read them in. If the last 2 bytes are
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// strings, but uses a load double to read them in. If the last 2 bytes are
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// not initialized the compare results in an 'x' which propagates through
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// not initialized the compare results in an 'x' which propagates through
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// the design.
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// the design.
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/* -----\/----- EXCLUDED -----\/-----
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// **** Must fix for coremark
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if (TEST == "coremark")
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if (TEST == "coremark")
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for (i=MemStartAddr; i<MemEndAddr; i = i+1)
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for (i=MemStartAddr; i<MemEndAddr; i = i+1)
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dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
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dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
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-----/\----- EXCLUDED -----/\----- */
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// read test vectors into memory
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// read test vectors into memory
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pathname = tvpaths[tests[0].atoi()];
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pathname = tvpaths[tests[0].atoi()];
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/* if (tests[0] == `IMPERASTEST)
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/* if (tests[0] == `IMPERASTEST)
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@ -262,24 +265,20 @@ module testbench;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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*/
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// force sdc timers
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// force sdc timers
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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*/
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end else begin
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end else begin
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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*/
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// *** replace this with above
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// *** replace this with above
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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*/
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end
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end
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if (riscofTest) begin
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if (riscofTest) begin
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@ -384,10 +383,9 @@ module testbench;
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while (signature[i] !== 'bx) begin
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while (signature[i] !== 'bx) begin
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/* verilator lint_on WIDTHXZEXPAND */
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/* verilator lint_on WIDTHXZEXPAND */
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logic [`XLEN-1:0] sig;
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logic [`XLEN-1:0] sig;
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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*/
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sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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@ -419,11 +417,11 @@ module testbench;
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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*/
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// *** replace this with the above
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// *** replace this with the above
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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@ -445,7 +443,7 @@ module testbench;
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end // always @ (negedge clk)
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end // always @ (negedge clk)
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
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if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleFirst;
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@ -528,7 +526,7 @@ module testbench;
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end
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end
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end
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end
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end
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end
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*/
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// track the current function or global label
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// track the current function or global label
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@ -566,7 +564,7 @@ module testbench;
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integer adrindex;
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integer adrindex;
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// local history only
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// local history only
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin
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if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin
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always @(*) begin
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always @(*) begin
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if(reset) begin
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if(reset) begin
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@ -576,22 +574,16 @@ module testbench;
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end
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end
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end
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end
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end
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end
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*/
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always @(*) begin
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always @(*) begin
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if(reset) begin
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if(reset) begin
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for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
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for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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=======
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testbench.dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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*/
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>>>>>>> verilator
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end
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end
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for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
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for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
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dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
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*/
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end
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end
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end
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end
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end
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end
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@ -681,9 +673,8 @@ module testbench;
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logic PCSrcM;
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logic PCSrcM;
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string LogFile;
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string LogFile;
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logic resetD, resetEdge;
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logic resetD, resetEdge;
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/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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// *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
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flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
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flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
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*/
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flop #(1) ResetDReg(clk, reset, resetD);
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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assign resetEdge = ~reset & resetD;
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initial begin
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initial begin
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