diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1e35009f1..4fefa2cfe 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -247,9 +247,12 @@ module testbench; // strings, but uses a load double to read them in. If the last 2 bytes are // not initialized the compare results in an 'x' which propagates through // the design. +/* -----\/----- EXCLUDED -----\/----- + // **** Must fix for coremark if (TEST == "coremark") for (i=MemStartAddr; i>>>>>> verilator end for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin - /* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. + // *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; - */ end end end @@ -681,9 +673,8 @@ module testbench; logic PCSrcM; string LogFile; logic resetD, resetEdge; - /* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. + // *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); - */ flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin