update some comments on debug

src/ieu/ieu.sv

@@ -120,6 +120,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   logic       BMUActiveE;                                    // Bit manipulation instruction being executed
   logic [1:0] CZeroE;                                        // {czero.nez, czero.eqz} instructions active
 
+  // Debug Control and Status (debug spec)
   logic DSCR;
            
   controller #(P) c(

src/lsu/lsu.sv

@@ -158,9 +158,10 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic                  IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
   logic                  SelDTIM;                                // Select DTIM rather than bus or D$
   logic [P.XLEN-1:0]     WriteDataZM;
-  logic                  LSULoadPageFaultM, LSUStoreAmoPageFaultM;
+  logic 		 LSULoadPageFaultM;
+  logic                  LSUStoreAmoPageFaultM;
 
-  logic                  DSCR;
+  logic                  DSCR;                                   // Debug Control and Status
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M

src/privileged/csrm.sv

@@ -95,7 +95,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   localparam TDATA2        = 12'h7A2;
   localparam TDATA3        = 12'h7A3;
   localparam DCSR          = 12'h7B0;
-  localparam DPC           = 12'h7B1;
+  localparam DPC           = 12'h7B1;  // Debug PC (DPC)  
   localparam DSCRATCH0     = 12'h7B2;
   localparam DSCRATCH1     = 12'h7B3;
   // Constants