From 97cf2fdd239d922a1488492d31161cd92cf52e8d Mon Sep 17 00:00:00 2001 From: James Stine Date: Sun, 9 Jun 2024 10:32:13 -0500 Subject: [PATCH] update some comments on debug --- src/ieu/ieu.sv | 1 + src/lsu/lsu.sv | 7 ++++--- src/privileged/csrm.sv | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 33fe4f03d..dd5bedcd6 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -120,6 +120,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic BMUActiveE; // Bit manipulation instruction being executed logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active + // Debug Control and Status (debug spec) logic DSCR; controller #(P) c( diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 1fe0c5738..e00e75cad 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -101,7 +101,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( output logic DebugScanOut ); localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED; - localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess + localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer @@ -158,9 +158,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; - logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; + logic LSULoadPageFaultM; + logic LSUStoreAmoPageFaultM; - logic DSCR; + logic DSCR; // Debug Control and Status ///////////////////////////////////////////////////////////////////////////////////////////// // Pipeline for IEUAdr E to M diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 293b918e1..07dcfeffb 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -95,7 +95,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam TDATA2 = 12'h7A2; localparam TDATA3 = 12'h7A3; localparam DCSR = 12'h7B0; - localparam DPC = 12'h7B1; + localparam DPC = 12'h7B1; // Debug PC (DPC) localparam DSCRATCH0 = 12'h7B2; localparam DSCRATCH1 = 12'h7B3; // Constants