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update some comments on debug

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This commit is contained in:
James Stine 2024-06-09 10:32:13 -05:00
parent c3243caacf
commit 97cf2fdd23
3 changed files with 6 additions and 4 deletions
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1
src/ieu/ieu.sv
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@ -120,6 +120,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
logic BMUActiveE; // Bit manipulation instruction being executed
logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active
// Debug Control and Status (debug spec)
logic DSCR;
controller #(P) c(

7
src/lsu/lsu.sv
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@ -101,7 +101,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
output logic DebugScanOut
);
localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
@ -158,9 +158,10 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
logic SelDTIM; // Select DTIM rather than bus or D$
logic [P.XLEN-1:0] WriteDataZM;
logic LSULoadPageFaultM, LSUStoreAmoPageFaultM;
logic LSULoadPageFaultM;
logic LSUStoreAmoPageFaultM;
logic DSCR;
logic DSCR; // Debug Control and Status
/////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline for IEUAdr E to M

2
src/privileged/csrm.sv
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@ -95,7 +95,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
localparam TDATA2 = 12'h7A2;
localparam TDATA3 = 12'h7A3;
localparam DCSR = 12'h7B0;
localparam DPC = 12'h7B1;
localparam DPC = 12'h7B1; // Debug PC (DPC)
localparam DSCRATCH0 = 12'h7B2;
localparam DSCRATCH1 = 12'h7B3;
// Constants