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https://github.com/openhwgroup/cvw
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Revert "Closer to getting subword write misaligned working."
This reverts commit 6a9c2d8dc4
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@ -424,7 +424,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(MISALIGN_SUPPORT) begin
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if(MISALIGN_SUPPORT) begin
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subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .CacheableM, .IMAFWriteDataM, .LittleEndianWriteDataM);
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subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .IMAFWriteDataM, .LittleEndianWriteDataM);
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end else begin
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end else begin
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subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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@ -33,7 +33,6 @@ module subwordwritedouble #(parameter LLEN) (
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input logic [2:0] PAdrM,
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input logic [2:0] PAdrM,
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input logic FpLoadStoreM,
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input logic FpLoadStoreM,
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input logic BigEndianM,
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input logic BigEndianM,
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input logic CacheableM,
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input logic [LLEN-1:0] IMAFWriteDataM,
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input logic [LLEN-1:0] IMAFWriteDataM,
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output logic [LLEN*2-1:0] LittleEndianWriteDataM
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output logic [LLEN*2-1:0] LittleEndianWriteDataM
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);
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);
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@ -44,13 +43,7 @@ module subwordwritedouble #(parameter LLEN) (
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logic [4:0] LengthM;
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logic [4:0] LengthM;
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// Funct3M[2] is the unsigned bit. mask upper bits.
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// Funct3M[2] is the unsigned bit. mask upper bits.
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// Funct3M[1:0] is the size of the memory access.
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// Funct3M[1:0] is the size of the memory access.
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// cacheable, BigEndian
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assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
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// 10: PAdrM[2:0]
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// 11: BigEndianPAdr
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// 00: 00000
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// 01: 00111
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mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {CacheableM, BigEndianM}, PAdrSwap);
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//assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
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/* verilator lint_off WIDTHEXPAND */
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/* verilator lint_off WIDTHEXPAND */
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/* verilator lint_off WIDTHTRUNC */
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/* verilator lint_off WIDTHTRUNC */
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assign BigEndianPAdr = (LLEN/4) - PAdrM - LengthM;
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assign BigEndianPAdr = (LLEN/4) - PAdrM - LengthM;
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