From 9668fdd8686e5afff8750e3552f57a2df9663117 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 6 Mar 2024 15:16:43 -0600 Subject: [PATCH] Revert "Closer to getting subword write misaligned working." This reverts commit 6a9c2d8dc43a1f997cf16969a2901d1e91fd4756. --- src/lsu/lsu.sv | 2 +- src/lsu/subwordwritedouble.sv | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 17c9d0c69..9fdf267b6 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -424,7 +424,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(MISALIGN_SUPPORT) begin subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); - subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .CacheableM, .IMAFWriteDataM, .LittleEndianWriteDataM); + subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .IMAFWriteDataM, .LittleEndianWriteDataM); end else begin subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); diff --git a/src/lsu/subwordwritedouble.sv b/src/lsu/subwordwritedouble.sv index 599d71984..728a4f4aa 100644 --- a/src/lsu/subwordwritedouble.sv +++ b/src/lsu/subwordwritedouble.sv @@ -33,7 +33,6 @@ module subwordwritedouble #(parameter LLEN) ( input logic [2:0] PAdrM, input logic FpLoadStoreM, input logic BigEndianM, - input logic CacheableM, input logic [LLEN-1:0] IMAFWriteDataM, output logic [LLEN*2-1:0] LittleEndianWriteDataM ); @@ -44,13 +43,7 @@ module subwordwritedouble #(parameter LLEN) ( logic [4:0] LengthM; // Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[1:0] is the size of the memory access. - // cacheable, BigEndian - // 10: PAdrM[2:0] - // 11: BigEndianPAdr - // 00: 00000 - // 01: 00111 - mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {CacheableM, BigEndianM}, PAdrSwap); - //assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; + assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; /* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHTRUNC */ assign BigEndianPAdr = (LLEN/4) - PAdrM - LengthM;