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Merge pull request #296 from davidharrishmc/main

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riscof fixes
This commit is contained in:
Ross Thompson 2023-05-22 11:05:34 -04:00 committed by GitHub
commit 962a640d36
25 changed files with 70 additions and 37 deletions
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8
benchmarks/coremark/Makefile
View File

@ -4,14 +4,14 @@
PORT_DIR = $(CURDIR)/riscv64-baremetal PORT_DIR = $(CURDIR)/riscv64-baremetal
cmbase=../../addins/coremark cmbase=../../addins/coremark
work_dir= ../../benchmarks/coremark/work work_dir= ../benchmarks/coremark/work
XLEN ?=64 XLEN ?=64
sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \ $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \ $(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32) ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
ARCH := rv$(XLEN)im ARCH := rv$(XLEN)gc
PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \ -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \ -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
@ -23,7 +23,7 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile
run: run:
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) (cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
cd ../benchmarks/coremark/ # cd ../benchmarks/coremark/
# KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test # KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
python3 coremark-postprocess.py python3 coremark-postprocess.py
@ -33,7 +33,7 @@ $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
extractFunctionRadix.sh $<.elf.objdump extractFunctionRadix.sh $<.elf.objdump
$(work_dir)/coremark.bare.riscv: $(sources) Makefile $(work_dir)/coremark.bare.riscv: $(sources) Makefile
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)" make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV) XCFLAGS="$(PORT_CFLAGS)"
mkdir -p $(work_dir) mkdir -p $(work_dir)
mv $(cmbase)/coremark.bare.riscv $(work_dir) mv $(cmbase)/coremark.bare.riscv $(work_dir)

8
benchmarks/coremark/coremark-postprocess.py
View File

@ -37,6 +37,14 @@ for lineNum in range(len(logLines)):
ICacheAccess = int(contents[-1]) ICacheAccess = int(contents[-1])
ICacheLineNum = lineNum + 2 ICacheLineNum = lineNum + 2
# prevent division by zero
if (dCacheAccess == 0):
dCacheAccess = 1;
if (ICacheAccess == 0):
ICacheAccess = 1;
if (branchesTot == 0):
branchesTot = 1;
# need to add the number of previously added lines to the line number so that they stay in the intedned order. # need to add the number of previously added lines to the line number so that they stay in the intedned order.
logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n") logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n")
logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n") logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")

2
config/shared/wally-shared.vh
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@ -125,7 +125,7 @@
// division constants // division constants
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input `define DIVN ((((`NF+2)<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
`define LOGR ($clog2(`RADIX)) // r = log(R) `define LOGR ($clog2(`RADIX)) // r = log(R)
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc `define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
`define LOGRK ($clog2(`RK)) // log2(r*k) `define LOGRK ($clog2(`RK)) // log2(r*k)

1
setup.sh
View File

@ -17,6 +17,7 @@ echo \$WALLY set to ${WALLY}
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim # Change this for your path to Questa, excluding bin export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim # Change this for your path to Questa, excluding bin
#export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_3/questasim # Change this for your path to Questa, excluding bin
export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
# Path to RISC-V Tools # Path to RISC-V Tools

4
sim/regression-wally
View File

@ -85,7 +85,7 @@ for test in tests64i:
configs.append(tc) configs.append(tc)
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
for test in tests32gc: for test in tests32gc:
tc = TestCase( tc = TestCase(
name=test, name=test,
@ -132,7 +132,7 @@ for test in ahbTests:
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
if (coverage): # delete all but 64gc tests when running coverage if (coverage): # delete all but 64gc tests when running coverage
configs = [] configs = []

4
testbench/testbench.sv
View File

@ -93,6 +93,8 @@ module testbench;
"arch64m": if (`M_SUPPORTED) tests = arch64m; "arch64m": if (`M_SUPPORTED) tests = arch64m;
"arch64f": if (`F_SUPPORTED) tests = arch64f; "arch64f": if (`F_SUPPORTED) tests = arch64f;
"arch64d": if (`D_SUPPORTED) tests = arch64d; "arch64d": if (`D_SUPPORTED) tests = arch64d;
"arch64f_fma": if (`F_SUPPORTED) tests = arch64f_fma;
"arch64d_fma": if (`D_SUPPORTED) tests = arch64d_fma;
"arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi; "arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
"imperas64i": tests = imperas64i; "imperas64i": tests = imperas64i;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64f": if (`F_SUPPORTED) tests = imperas64f;
@ -124,6 +126,8 @@ module testbench;
"arch32m": if (`M_SUPPORTED) tests = arch32m; "arch32m": if (`M_SUPPORTED) tests = arch32m;
"arch32f": if (`F_SUPPORTED) tests = arch32f; "arch32f": if (`F_SUPPORTED) tests = arch32f;
"arch32d": if (`D_SUPPORTED) tests = arch32d; "arch32d": if (`D_SUPPORTED) tests = arch32d;
"arch32f_fma": if (`F_SUPPORTED) tests = arch32f_fma;
"arch32d_fma": if (`D_SUPPORTED) tests = arch32d_fma;
"arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi; "arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
"imperas32i": tests = imperas32i; "imperas32i": tests = imperas32i;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32f": if (`F_SUPPORTED) tests = imperas32f;

42
testbench/tests.vh
View File

@ -1066,6 +1066,14 @@ string imperas32f[] = '{
"rv64i_m/I/src/xori-01.S" "rv64i_m/I/src/xori-01.S"
}; };
string arch64f_fma[] = '{
`RISCVARCHTEST,
//"rv64i_m/F/src/fmadd_b15-01.S",
"rv64i_m/F/src/fmsub_b15-01.S"
// "rv64i_m/F/src/fnmadd_b15-01.S",
// "rv64i_m/F/src/fnmsub_b15-01.S"
};
string arch64f[] = '{ string arch64f[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b1-01.S",
@ -1088,8 +1096,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b7-01.S",
"rv64i_m/F/src/fsqrt_b8-01.S", "rv64i_m/F/src/fsqrt_b8-01.S",
"rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsqrt_b9-01.S",
"rv64i_m/F/src/fadd_b10-01.S", "rv64i_m/F/src/fadd_b10-01.S",
"rv64i_m/F/src/fadd_b1-01.S", "rv64i_m/F/src/fadd_b1-01.S",
"rv64i_m/F/src/fadd_b11-01.S", "rv64i_m/F/src/fadd_b11-01.S",
@ -1140,7 +1146,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/flw-align-01.S", "rv64i_m/F/src/flw-align-01.S",
"rv64i_m/F/src/fmadd_b1-01.S", "rv64i_m/F/src/fmadd_b1-01.S",
"rv64i_m/F/src/fmadd_b14-01.S", "rv64i_m/F/src/fmadd_b14-01.S",
//"rv64i_m/F/src/fmadd_b15-01.S",
"rv64i_m/F/src/fmadd_b16-01.S", "rv64i_m/F/src/fmadd_b16-01.S",
"rv64i_m/F/src/fmadd_b17-01.S", "rv64i_m/F/src/fmadd_b17-01.S",
"rv64i_m/F/src/fmadd_b18-01.S", "rv64i_m/F/src/fmadd_b18-01.S",
@ -1157,7 +1162,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/fmin_b19-01.S", "rv64i_m/F/src/fmin_b19-01.S",
"rv64i_m/F/src/fmsub_b1-01.S", "rv64i_m/F/src/fmsub_b1-01.S",
"rv64i_m/F/src/fmsub_b14-01.S", "rv64i_m/F/src/fmsub_b14-01.S",
"rv64i_m/F/src/fmsub_b15-01.S",
"rv64i_m/F/src/fmsub_b16-01.S", "rv64i_m/F/src/fmsub_b16-01.S",
"rv64i_m/F/src/fmsub_b17-01.S", "rv64i_m/F/src/fmsub_b17-01.S",
"rv64i_m/F/src/fmsub_b18-01.S", "rv64i_m/F/src/fmsub_b18-01.S",
@ -1188,7 +1192,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/fmv.x.w_b29-01.S", "rv64i_m/F/src/fmv.x.w_b29-01.S",
"rv64i_m/F/src/fnmadd_b1-01.S", "rv64i_m/F/src/fnmadd_b1-01.S",
"rv64i_m/F/src/fnmadd_b14-01.S", "rv64i_m/F/src/fnmadd_b14-01.S",
// "rv64i_m/F/src/fnmadd_b15-01.S",
"rv64i_m/F/src/fnmadd_b16-01.S", "rv64i_m/F/src/fnmadd_b16-01.S",
"rv64i_m/F/src/fnmadd_b17-01.S", "rv64i_m/F/src/fnmadd_b17-01.S",
"rv64i_m/F/src/fnmadd_b18-01.S", "rv64i_m/F/src/fnmadd_b18-01.S",
@ -1201,7 +1204,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/fnmadd_b8-01.S", "rv64i_m/F/src/fnmadd_b8-01.S",
"rv64i_m/F/src/fnmsub_b1-01.S", "rv64i_m/F/src/fnmsub_b1-01.S",
"rv64i_m/F/src/fnmsub_b14-01.S", "rv64i_m/F/src/fnmsub_b14-01.S",
// "rv64i_m/F/src/fnmsub_b15-01.S",
"rv64i_m/F/src/fnmsub_b16-01.S", "rv64i_m/F/src/fnmsub_b16-01.S",
"rv64i_m/F/src/fnmsub_b17-01.S", "rv64i_m/F/src/fnmsub_b17-01.S",
"rv64i_m/F/src/fnmsub_b18-01.S", "rv64i_m/F/src/fnmsub_b18-01.S",
@ -1238,6 +1240,13 @@ string imperas32f[] = '{
"rv64i_m/F/src/fsw-align-01.S" "rv64i_m/F/src/fsw-align-01.S"
}; };
string arch64d_fma[] = '{
`RISCVARCHTEST,
//"rv64i_m/D/src/fmadd.d_b15-01.S",
//"rv64i_m/D/src/fmsub.d_b15-01.S",
"rv64i_m/D/src/fnmadd.d_b15-01.S"
// "rv64i_m/D/src/fnmsub.d_b15-01.S"
};
string arch64d[] = '{ string arch64d[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
@ -1262,7 +1271,6 @@ string imperas32f[] = '{
"rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b7-01.S",
"rv64i_m/D/src/fsqrt.d_b8-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S",
"rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fsqrt.d_b9-01.S",
"rv64i_m/D/src/fadd.d_b10-01.S", "rv64i_m/D/src/fadd.d_b10-01.S",
"rv64i_m/D/src/fadd.d_b1-01.S", "rv64i_m/D/src/fadd.d_b1-01.S",
"rv64i_m/D/src/fadd.d_b11-01.S", "rv64i_m/D/src/fadd.d_b11-01.S",
@ -1526,6 +1534,14 @@ string arch64zbs[] = '{
"rv32i_m/M/src/mulhu-01.S" "rv32i_m/M/src/mulhu-01.S"
}; };
string arch32f_fma[] = '{
`RISCVARCHTEST,
"rv32i_m/F/src/fmadd_b15-01.S"
//"rv32i_m/F/src/fmsub_b15-01.S",
// "rv32i_m/F/src/fnmadd_b15-01.S",
// "rv32i_m/F/src/fnmsub_b15-01.S"
};
string arch32f[] = '{ string arch32f[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/F/src/fdiv_b20-01.S", "rv32i_m/F/src/fdiv_b20-01.S",
@ -1579,7 +1595,6 @@ string arch64zbs[] = '{
"rv32i_m/F/src/flw-align-01.S", "rv32i_m/F/src/flw-align-01.S",
"rv32i_m/F/src/fmadd_b1-01.S", "rv32i_m/F/src/fmadd_b1-01.S",
"rv32i_m/F/src/fmadd_b14-01.S", "rv32i_m/F/src/fmadd_b14-01.S",
"rv32i_m/F/src/fmadd_b15-01.S",
"rv32i_m/F/src/fmadd_b16-01.S", "rv32i_m/F/src/fmadd_b16-01.S",
"rv32i_m/F/src/fmadd_b17-01.S", "rv32i_m/F/src/fmadd_b17-01.S",
"rv32i_m/F/src/fmadd_b18-01.S", "rv32i_m/F/src/fmadd_b18-01.S",
@ -1596,7 +1611,6 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fmin_b19-01.S", "rv32i_m/F/src/fmin_b19-01.S",
"rv32i_m/F/src/fmsub_b1-01.S", "rv32i_m/F/src/fmsub_b1-01.S",
"rv32i_m/F/src/fmsub_b14-01.S", "rv32i_m/F/src/fmsub_b14-01.S",
//"rv32i_m/F/src/fmsub_b15-01.S",
"rv32i_m/F/src/fmsub_b16-01.S", "rv32i_m/F/src/fmsub_b16-01.S",
"rv32i_m/F/src/fmsub_b17-01.S", "rv32i_m/F/src/fmsub_b17-01.S",
"rv32i_m/F/src/fmsub_b18-01.S", "rv32i_m/F/src/fmsub_b18-01.S",
@ -1627,7 +1641,6 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fmv.x.w_b29-01.S", "rv32i_m/F/src/fmv.x.w_b29-01.S",
"rv32i_m/F/src/fnmadd_b1-01.S", "rv32i_m/F/src/fnmadd_b1-01.S",
"rv32i_m/F/src/fnmadd_b14-01.S", "rv32i_m/F/src/fnmadd_b14-01.S",
// "rv32i_m/F/src/fnmadd_b15-01.S",
"rv32i_m/F/src/fnmadd_b16-01.S", "rv32i_m/F/src/fnmadd_b16-01.S",
"rv32i_m/F/src/fnmadd_b17-01.S", "rv32i_m/F/src/fnmadd_b17-01.S",
"rv32i_m/F/src/fnmadd_b18-01.S", "rv32i_m/F/src/fnmadd_b18-01.S",
@ -1640,7 +1653,6 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fnmadd_b8-01.S", "rv32i_m/F/src/fnmadd_b8-01.S",
"rv32i_m/F/src/fnmsub_b1-01.S", "rv32i_m/F/src/fnmsub_b1-01.S",
"rv32i_m/F/src/fnmsub_b14-01.S", "rv32i_m/F/src/fnmsub_b14-01.S",
// "rv32i_m/F/src/fnmsub_b15-01.S",
"rv32i_m/F/src/fnmsub_b16-01.S", "rv32i_m/F/src/fnmsub_b16-01.S",
"rv32i_m/F/src/fnmsub_b17-01.S", "rv32i_m/F/src/fnmsub_b17-01.S",
"rv32i_m/F/src/fnmsub_b18-01.S", "rv32i_m/F/src/fnmsub_b18-01.S",
@ -1677,6 +1689,14 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fsw-align-01.S" "rv32i_m/F/src/fsw-align-01.S"
}; };
string arch32d_fma[] = '{
`RISCVARCHTEST,
//"rv32i_m/D/src/fmadd.d_b15-01.S",
//"rv32i_m/D/src/fmsub.d_b15-01.S",
// "rv32i_m/D/src/fnmadd.d_b15-01.S",
"rv32i_m/D/src/fnmsub.d_b15-01.S"
};
string arch32d[] = '{ string arch32d[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/D/src/fadd.d_b10-01.S", "rv32i_m/D/src/fadd.d_b10-01.S",

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
View File

@ -22,7 +22,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
View File

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
View File

@ -36,7 +36,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
View File

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr") RVTEST_ISA("RV32I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout)
.equ UART, 0x10000000 .equ UART, 0x10000000

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
View File

@ -22,7 +22,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
View File

@ -22,7 +22,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
View File

@ -22,7 +22,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
View File

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
View File

@ -35,7 +35,7 @@
#define PLIC_RANGE 0x03FFFFFF #define PLIC_RANGE 0x03FFFFFF
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
View File

@ -22,7 +22,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr_Zifencei")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
INIT_TESTS INIT_TESTS