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https://github.com/openhwgroup/cvw
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Removed obsolete testbench/coverage
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commit
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@ -1,25 +0,0 @@
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typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t;
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covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins);
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option.per_instance = 1;
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option.comment = "Fence.I";
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cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) {
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option.comment = "Number of times instruction is executed";
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bins count[] = {1};
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}
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endgroup
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function void test_fencei_sample(int hart, int issue);
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test_ins_rv64i_t ins;
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case (traceDataQ[hart][issue][0].inst_name)
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"fenci" : begin
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ins = new(hart, issue, traceDataQ);
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test_fencei_cg.sample(ins);
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end
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endcase
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endfunction
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@ -1,4 +0,0 @@
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test_fencei_cg = new(); test_fencei_cg.set_inst_name("obj_fencei");
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// test_fencei_cg = new();
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//test_fencei_cg.set_inst_name("obj_fencei");
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@ -1,108 +0,0 @@
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module test_pmp_coverage import cvw::*; #(parameter cvw_t P) (input clk);
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// Ensure the covergroup is defined correctly
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covergroup cg_priv_mode @(posedge clk);
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coverpoint dut.core.ifu.PrivilegeModeW {
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bins user = {2'b00};
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bins superv = {2'b01};
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bins hyperv = {2'b10};
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bins mach = {2'b11};
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}
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endgroup
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covergroup cg_PMPConfig @(posedge clk);
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coverpoint dut.core.ifu.PMPCFG_ARRAY_REGW[0][0] {
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bins ones = {1};
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bins zeros = {0};
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}
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endgroup
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function bit [1:0] getPMPConfigSlice(int index);
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return dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[index][4:3];
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endfunction
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//if (P.PMP_ENTRIES > 0) begin : pmp
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covergroup cg_pmpcfg_mode @(posedge clk);
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[0][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[1][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[2][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[3][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[4][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[5][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[6][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[7][4:3] {
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bins off = {2'b00};
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bins tor = {2'b01};
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bins na4 = {2'b10};
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bins napot = {2'b11};
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}
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endgroup
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//end
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// Ensure that the instantiation and sampling of covergroups are within the correct procedural context
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initial begin
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cg_priv_mode privmodeCG = new(); // Instantiate the privilege mode covergroup
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cg_PMPConfig pmpconfigCG = new(); // Instantiate the PMP config covergroup
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cg_pmpcfg_mode pmpcfgmodeCG = new();
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forever begin
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@(posedge clk) begin
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privmodeCG.sample(); // Sample the privilege mode covergroup
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pmpconfigCG.sample(); // Sample the PMP config covergroupi
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pmpcfgmodeCG.sample();
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end
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end
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end
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endmodule
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