Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.

Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.

.gitignore

@@ -237,3 +237,4 @@ tests/functcov
 tests/functcov/*
 tests/functcov/*/*
 sim/vcs/simprofile*
+/fpga/rvvidaemon/rvvidaemon

config/derivlist.txt

@@ -56,6 +56,10 @@ EXT_MEM_RANGE       64'h0FFFFFFF
 SDC_SUPPORTED       1
 PLIC_SDC_ID         32'd20
 BPRED_SIZE          32'd12
+RVVI_SYNTH_SUPPORTED 1
+RVVI_INIT_TIME_OUT  32'd100000000
+RVVI_PACKET_DELAY   32'd350
+
 
 # The syn configurations are trimmed down for faster synthesis.  
 deriv   syn_rv32e   rv32e

config/rv32e/config.vh

@@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
 // Memory synthesis configuration
 localparam logic USE_SRAM = 0;
 
+// debug tools
+localparam logic RVVI_SYNTH_SUPPORTED = 0;
+localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
+localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
+
 `include "config-shared.vh"

config/rv32gc/config.vh

@@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd2;
 // Memory synthesis configuration
 localparam logic USE_SRAM = 0;
 
+// debug tools
+localparam logic RVVI_SYNTH_SUPPORTED = 0;
+localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
+localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
+
 `include "config-shared.vh"

config/rv32i/config.vh

@@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
 // Memory synthesis configuration
 localparam logic USE_SRAM = 0;
 
+// debug tools
+localparam logic RVVI_SYNTH_SUPPORTED = 0;
+localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
+localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
+
 `include "config-shared.vh"

config/rv32imc/config.vh

@@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
 // Memory synthesis configuration
 localparam logic USE_SRAM = 0;
 
+// debug tools
+localparam logic RVVI_SYNTH_SUPPORTED = 0;
+localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
+localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
+
 `include "config-shared.vh"

config/rv64gc/config.vh

@@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
 // Memory synthesis configuration
 localparam logic USE_SRAM = 0;
 
+// debug tools
+localparam logic RVVI_SYNTH_SUPPORTED = 0;
+localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
+localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
+
 `include "config-shared.vh"

config/rv64i/config.vh

@@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
 // Memory synthesis configuration
 localparam logic USE_SRAM = 0;
 
+// debug tools
+localparam logic RVVI_SYNTH_SUPPORTED = 0;
+localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
+localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
+
 `include "config-shared.vh"

config/shared/parameter-defs.vh

@@ -199,5 +199,8 @@ localparam cvw_t P = '{
   FPDUR       : FPDUR,
   DURLEN      : DURLEN,
   DIVb        : DIVb,
-  DIVBLEN     : DIVBLEN
+  DIVBLEN     : DIVBLEN,
+  RVVI_SYNTH_SUPPORTED : RVVI_SYNTH_SUPPORTED,
+  RVVI_INIT_TIME_OUT : RVVI_INIT_TIME_OUT,
+  RVVI_PACKET_DELAY : RVVI_PACKET_DELAY
 };

fpga/src/fpgaTopArtyA7.sv

@@ -513,7 +513,7 @@ module fpgaTop
                     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
                     .GPIOIN, .GPIOOUT, .GPIOEN,
-                    .UARTSin, .UARTSout, .SDCIntr, .RVVIStall); 
+                    .UARTSin, .UARTSout, .SDCIntr, .ExternalStall(RVVIStall)); 
 
 
   // ahb lite to axi bridge
@@ -1116,10 +1116,89 @@ module fpgaTop
      .device_temp(device_temp));
   
   localparam MAX_CSRS = 3;
+  localparam TOTAL_CSRS = 36;
+  
+  // pipeline controlls
+  logic                                             StallE, StallM, StallW, FlushE, FlushM, FlushW;
+  // required
+  logic [P.XLEN-1:0]                                PCM;
+  logic                                             InstrValidM;
+  logic [31:0]                                      InstrRawD;
+  logic [63:0]                                      Mcycle, Minstret;
+  logic                                             TrapM;
+  logic [1:0]                                       PrivilegeModeW;
+  // registers gpr and fpr
+  logic                                             GPRWen, FPRWen;
+  logic [4:0]                                       GPRAddr, FPRAddr;
+  logic [P.XLEN-1:0]                                GPRValue, FPRValue;
+  logic [P.XLEN-1:0]                                CSRArray [TOTAL_CSRS-1:0];
+
 (* mark_debug = "true" *)  logic                       valid;
   logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
 
-  rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .valid, .rvvi);
+  assign StallE         = fpgaTop.wallypipelinedsoc.core.StallE;
+  assign StallM         = fpgaTop.wallypipelinedsoc.core.StallM;
+  assign StallW         = fpgaTop.wallypipelinedsoc.core.StallW;
+  assign FlushE         = fpgaTop.wallypipelinedsoc.core.FlushE;
+  assign FlushM         = fpgaTop.wallypipelinedsoc.core.FlushM;
+  assign FlushW         = fpgaTop.wallypipelinedsoc.core.FlushW;
+  assign InstrValidM    = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
+  assign InstrRawD      = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
+  assign PCM            = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
+  assign Mcycle         = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
+  assign Minstret       = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
+  assign TrapM          = fpgaTop.wallypipelinedsoc.core.TrapM;
+  assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
+  assign GPRAddr        = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
+  assign GPRWen         = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
+  assign GPRValue       = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
+  assign FPRAddr        = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
+  assign FPRWen         = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
+  assign FPRValue       = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
+
+  assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
+  assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
+  assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
+  assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
+  assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
+  assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
+  assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
+  assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
+  assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
+  assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
+  assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
+  assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
+  assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
+  assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
+  assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
+  assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
+  assign CSRArray[16] = 0; // 12'hF11
+  assign CSRArray[17] = 0; // 12'hF12
+  assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
+  assign CSRArray[19] = 0; // 12'hF15
+  assign CSRArray[20] = 0; // 12'h34A
+  // supervisor CSRs
+  assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
+  assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
+  assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
+  assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
+  assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
+  assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
+  assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
+  assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
+  assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
+  assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
+  assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
+  assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
+  // user CSRs
+  assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
+  assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
+  assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
+
+  rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
+    .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, 
+    .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
+    .valid, .rvvi);
 
   // axi 4 write data channel
 (* mark_debug = "true" *)  logic [31:0]                                      RvviAxiWdata;

sim/questa/wally.do

@@ -193,7 +193,7 @@ set temp3 [lindex $PlusArgs 3]
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
 
-vlog -lint -work ${WKDIR}  +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles}  ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C}  ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv  ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
+vlog -lint -work ${WKDIR}  +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles}  ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C}  ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv  ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals

sim/verilator/Makefile

@@ -25,7 +25,7 @@ TARGET=$(WORKING_DIR)/target
 # INCLUDE_PATH are pathes that Verilator should search for files it needs
 INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
 # SOURCES are source files
-SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv
 # DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
 DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
 

src/cvw.sv

@@ -294,6 +294,11 @@ typedef struct packed {
   int DURLEN     ;
   int DIVb       ;
   int DIVBLEN    ;
+
+// debug tools
+  logic RVVI_SYNTH_SUPPORTED;
+  logic [31:0] RVVI_INIT_TIME_OUT;
+  logic [31:0] RVVI_PACKET_DELAY; 
 } cvw_t;
 
 endpackage

src/hazard/hazard.sv

@@ -31,7 +31,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
   input  logic  StructuralStallD,
   input  logic  LSUStallM, IFUStallF,
-  input  logic  FPUStallD, RVVIStall,
+  input  logic  FPUStallD, ExternalStall,
   input  logic  DivBusyE, FDivBusyE,
   input  logic  wfiM, IntPendingM,
   // Stall & flush outputs
@@ -89,7 +89,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
   // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
   // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
-  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | RVVIStall;
+  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | ExternalStall;
 
   // Stall each stage for cause or if the next stage is stalled
   // coverage off: StallFCause is always 0

src/rvvi/packetizer.sv

@@ -100,11 +100,8 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   // have to count at least 250 ms after reset pulled to wait for the phy to actually be ready
   // at 20MHz 250 ms is 250e-3 / (1/20e6) = 5,000,000.
   counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount);
-  assign CountFlag = RstCount == 32'd100000000;
+  assign CountFlag = RstCount == P.RVVI_INIT_TIME_OUT;
-  //assign CountFlag = RstCount == 32'd10;
+  assign DelayFlag = RstCount == P.RVVI_PACKET_DELAY;
-  //assign DelayFlag = RstCount == 32'd800;
-  assign DelayFlag = RstCount == 32'd350;
-  //assign DelayFlag = RstCount == 32'd0;
 
   counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount);
    

src/rvvi/rvvisynth.sv

@@ -27,32 +27,38 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`define FPGA 1
+`define FPGA 0
 
 module rvvisynth import cvw::*; #(parameter cvw_t P,
-                                  parameter integer MAX_CSRS)(
+                                  parameter integer MAX_CSRS, TOTAL_CSRS = 36)(
   input logic clk, reset,
+  input logic                                     StallE, StallM, StallW, FlushE, FlushM, FlushW,
+  // required
+  input logic [P.XLEN-1:0]                        PCM,
+  input logic                                     InstrValidM,
+  input logic [31:0]                              InstrRawD,
+  input logic [63:0]                              Mcycle, Minstret,
+  input logic                                     TrapM,
+  input logic [1:0]                               PrivilegeModeW,
+  // registers gpr and fpr
+  input logic                                     GPRWen, FPRWen,
+  input logic [4:0]                               GPRAddr, FPRAddr,
+  input logic [P.XLEN-1:0]                        GPRValue, FPRValue,
+  input logic [P.XLEN-1:0]                        CSRArray [TOTAL_CSRS-1:0],
   output logic valid,
   output logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi
   );
 
-  localparam TOTAL_CSRS = 36;
-  
   // pipeline controlls
-  logic                                     StallE, StallM, StallW, FlushE, FlushM, FlushW;
+
   // required
-  logic [P.XLEN-1:0]                        PCM, PCW;
+  logic [P.XLEN-1:0]                        PCW;
-  logic                                     InstrValidM, InstrValidW;
+  logic                                     InstrValidW;
-  logic [31:0]                              InstrRawD, InstrRawE, InstrRawM, InstrRawW;
+  logic [31:0]                              InstrRawE, InstrRawM, InstrRawW;
-  logic [63:0]                              Mcycle, Minstret;
+  logic                                     TrapW;
-  logic                                     TrapM, TrapW;
+
-  logic [1:0]                               PrivilegeModeW;
   // registers gpr and fpr
-  logic                                     GPRWen, FPRWen;
-  logic [4:0]                               GPRAddr, FPRAddr;
-  logic [P.XLEN-1:0]                        GPRValue, FPRValue;
   logic [P.XLEN-1:0]                        XLENZeros;
-  logic [P.XLEN-1:0]                        CSRArray [TOTAL_CSRS-1:0];
   logic [TOTAL_CSRS-1:0]                    CSRArrayWen;
   logic [P.XLEN-1:0]                        CSRValue [MAX_CSRS-1:0];
   logic [TOTAL_CSRS-1:0]                    CSRWen [MAX_CSRS-1:0];
@@ -65,6 +71,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
      
   // get signals from the core.
    if (`FPGA) begin
+/* -----\/----- EXCLUDED -----\/-----
   assign StallE         = fpgaTop.wallypipelinedsoc.core.StallE;
   assign StallM         = fpgaTop.wallypipelinedsoc.core.StallM;
   assign StallW         = fpgaTop.wallypipelinedsoc.core.StallW;
@@ -123,7 +130,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
   assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
   assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
   assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
+ -----/\----- EXCLUDED -----/\----- */
    end else begin // if (`FPGA)
+/* -----\/----- EXCLUDED -----\/-----
         assign StallE         = dut.core.StallE;
   assign StallM         = dut.core.StallM;
   assign StallW         = dut.core.StallW;
@@ -182,6 +191,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
   assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
   assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
   assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
+ -----/\----- EXCLUDED -----/\----- */
    end
 
   //

src/wally/wallypipelinedcore.sv

@@ -45,7 +45,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
    output logic [3:0]            HPROT,
    output logic [1:0]            HTRANS,
    output logic                  HMASTLOCK,
-   input  logic                  RVVIStall
+   input  logic                  ExternalStall
 );
 
   logic                          StallF, StallD, StallE, StallM, StallW;
@@ -275,7 +275,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
     .StructuralStallD,
     .LSUStallM, .IFUStallF,
-    .FPUStallD, .RVVIStall,
+    .FPUStallD, .ExternalStall,
     .DivBusyE, .FDivBusyE,
     .wfiM, .IntPendingM,
     // Stall & flush outputs

src/wally/wallypipelinedsoc.sv

@@ -37,7 +37,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   output logic                HSELEXT,
   output logic                HSELEXTSDC, 
   // fpga debug signals
-  input  logic                RVVIStall,
+  input  logic                ExternalStall,
   // outputs to external memory, shared with uncore memory
   output logic                HCLK, HRESETn,
   output logic [P.PA_BITS-1:0]  HADDR,
@@ -77,7 +77,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   wallypipelinedcore #(P) core(.clk, .reset,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .RVVIStall
+    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .ExternalStall
    );
 
   // instantiate uncore if a bus interface exists

testbench/common/loggers.sv

@@ -261,11 +261,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
           $fwrite(file, "BEGIN %s\n", memfilename);
           $fwrite(CFIfile, "BEGIN %s\n", memfilename);
         end
-        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+        if(dut.core.ifu.IClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
           direction = PCSrcM ? "t" : "n";
           $fwrite(file, "%h %s\n", dut.core.PCM, direction);
         end
-        if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+        if((|dut.core.ifu.IClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
           direction = PCSrcM ? "t" : "n";
           $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
         end

testbench/testbench.sv

@@ -580,7 +580,8 @@ module testbench;
     assign SDCIntr = 1'b0;
   end
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .RVVIStall, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall), 
+    .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
     .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
     .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); 
@@ -590,12 +591,91 @@ module testbench;
     clk = 1'b1; # 5; clk = 1'b0; # 5;
   end
 
-  if(`RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
+  if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
     localparam MAX_CSRS = 3;
     logic                       valid;
     logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
 
-    rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi);
+    localparam TOTAL_CSRS = 36;
+    
+    // pipeline controlls
+    logic                                             StallE, StallM, StallW, FlushE, FlushM, FlushW;
+    // required
+    logic [P.XLEN-1:0]                                PCM;
+    logic                                             InstrValidM;
+    logic [31:0]                                      InstrRawD;
+    logic [63:0]                                      Mcycle, Minstret;
+    logic                                             TrapM;
+    logic [1:0]                                       PrivilegeModeW;
+    // registers gpr and fpr
+    logic                                             GPRWen, FPRWen;
+    logic [4:0]                                       GPRAddr, FPRAddr;
+    logic [P.XLEN-1:0]                                GPRValue, FPRValue;
+    logic [P.XLEN-1:0]                                CSRArray [TOTAL_CSRS-1:0];
+
+    assign StallE         = dut.core.StallE;
+    assign StallM         = dut.core.StallM;
+    assign StallW         = dut.core.StallW;
+    assign FlushE         = dut.core.FlushE;
+    assign FlushM         = dut.core.FlushM;
+    assign FlushW         = dut.core.FlushW;
+    assign InstrValidM    = dut.core.ieu.InstrValidM;
+    assign InstrRawD      = dut.core.ifu.InstrRawD;
+    assign PCM            = dut.core.ifu.PCM;
+    assign Mcycle         = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
+    assign Minstret       = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
+    assign TrapM          = dut.core.TrapM;
+    assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW;
+    assign GPRAddr        = dut.core.ieu.dp.regf.a3;
+    assign GPRWen         = dut.core.ieu.dp.regf.we3;
+    assign GPRValue       = dut.core.ieu.dp.regf.wd3;
+    assign FPRAddr        = dut.core.fpu.fpu.fregfile.a4;
+    assign FPRWen         = dut.core.fpu.fpu.fregfile.we4;
+    assign FPRValue       = dut.core.fpu.fpu.fregfile.wd4;
+
+    assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
+    assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
+    assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
+    assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
+    assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
+    assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
+    assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
+    assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
+    assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
+    assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
+    assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
+    assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
+    assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
+    assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
+    assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
+    assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
+    assign CSRArray[16] = 0; // 12'hF11
+    assign CSRArray[17] = 0; // 12'hF12
+    assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
+    assign CSRArray[19] = 0; // 12'hF15
+    assign CSRArray[20] = 0; // 12'h34A
+	// supervisor CSRs
+    assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
+    assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
+    assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
+    assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
+    assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
+    assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
+    assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
+    assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
+    assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
+    assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
+    assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
+    assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
+	// user CSRs
+    assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
+    assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
+    assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
+
+    rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
+      .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, 
+      .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
+      .valid, .rvvi);
 
     // axi 4 write data channel
     logic [31:0]                                      RvviAxiWdata;
@@ -618,12 +698,11 @@ module testbench;
       .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1),
       .rx_axis_tlast(), .rx_axis_tuser(),
 
-      // *** update these
+      .mii_rx_clk(clk),
-      .mii_rx_clk(clk), // *** need to be the mii clock
       .mii_rxd('0),
       .mii_rx_dv('0),
       .mii_rx_er('0),
-      .mii_tx_clk(clk), // *** needs to be the mii clock
+      .mii_tx_clk(clk),
       .mii_txd,
       .mii_tx_en,
       .mii_tx_er,

testbench/wallywrapper.sv

@@ -57,7 +57,7 @@ module wallywrapper;
   logic        HREADY;
   logic        HSELEXT;
   logic        HSELEXTSDC;
-  logic        RVVIStall;
+  logic        ExternalStall;
   
   // instantiate device to be tested
   assign GPIOIN = 0;
@@ -67,9 +67,9 @@ module wallywrapper;
     assign HRESPEXT = 0;
     assign HRDATAEXT = 0;
 
-  assign RVVIStall = '0;
+  assign ExternalStall = '0;
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .RVVIStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .ExternalStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
                         .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                         .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
                         .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr);