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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #481 from ross144/main
Fixed the BTB logger so sim_bp correctly reports BTB performance
This commit is contained in:
David Harris
GitHub
commit
94201e993f
@ -52,6 +52,6 @@ do
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# with such long precision bc outputs onto multiple lines
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# must remove \n and \ from string
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Product=`echo "$Product" | tr -d '\n' | tr -d '\\\'`
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GeoMean=`perl -E "say $Product**(1/$Count)"`
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GeoMean=`perl -E "say $Product**(1/$Count) * 100"`
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echo "$Pred$Size $GeoMean"
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done
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@ -43,7 +43,8 @@ TrainLineNumberArray=($TrainLineNumbers)
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BeginLineNumberArray=($BeginLineNumbers)
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EndLineNumberArray=($EndLineNumbers)
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mkdir -p branch
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OutputPath=${File%%.*}
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mkdir -p $OutputPath
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Length=${#EndLineNumberArray[@]}
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for i in $(seq 0 1 $((Length-1)))
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do
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@ -51,5 +52,5 @@ do
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CurrTrain=$((${TrainLineNumberArray[$i]}+1))
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CurrEnd=$((${EndLineNumberArray[$i]}-1))
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echo $CurrName, $CurrTrain, $CurrEnd
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sed -n "${CurrTrain},${CurrEnd}p" $File > branch/${CurrName}_branch.log
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sed -n "${CurrTrain},${CurrEnd}p" $File > $OutputPath/${CurrName}_${File}
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done
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@ -32,10 +32,12 @@ import math
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import numpy as np
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import argparse
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RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
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RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
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('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
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('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
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('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
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RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.11806778745097), ('BTBCModel8', 'BTBCModel', 256, 0.183833943219956), ('BTBCModel10', 'BTBCModel', 1024, 0.0109271020749376),
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('BTBCModel12', 'BTBCModel', 4096, 0.00437600802791213), ('BTBCModel14', 'BTBCModel', 16384, 0.00188756234204305), ('BTBCModel16', 'BTBCModel', 65536, 0.00188756234204305)]
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def ParseBranchListFile(path):
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'''Take the path to the list of Questa Sim log files containing the performance counters outputs. File
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@ -436,7 +438,8 @@ performanceCounterList = BuildDataBase(predictorLogs) # builds a databas
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benchmarkFirstList = ReorderDataBase(performanceCounterList) # reorder first by benchmark then trace
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benchmarkDict = ExtractSelectedData(benchmarkFirstList) # filters to just the desired performance counter metric
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if(args.reference): benchmarkDict['Mean'].extend(RefData)
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if(args.reference and args.direction): benchmarkDict['Mean'].extend(RefDataBP)
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if(args.reference and args.target): benchmarkDict['Mean'].extend(RefDataBTB)
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#print(benchmarkDict['Mean'])
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#print(benchmarkDict['aha-mont64Speed'])
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#print(benchmarkDict)
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@ -31,6 +31,7 @@
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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@ -31,6 +31,7 @@
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-extensions = "svadu";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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@ -114,7 +114,20 @@ def main():
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grepstr="")
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configs.append(tc)
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if(args.target or args.iclass):
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if(args.target):
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# BTB and class size sweep
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bpdSize = [6, 8, 10, 12, 14, 16]
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for CurrBPSize in bpdSize:
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name = 'BTB'+str(CurrBPSize)
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configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+RAS_SIZE=16+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE"
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tc = TestCase(
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name=name,
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variant="rv32gc",
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cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
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grepstr="")
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configs.append(tc)
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if(args.iclass):
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# BTB and class size sweep
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bpdSize = [6, 8, 10, 12, 14, 16]
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for CurrBPSize in bpdSize:
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@ -55,11 +55,13 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
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$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
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$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
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../src/cvw.sv \
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../testbench/testbench-linux-imperas.sv \
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../testbench/common/*.sv ../src/*/*.sv \
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@ -45,7 +45,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
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// performance counter logging
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logic BeginSample;
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logic StartSample, EndSample;
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if(PrintHPMCounters & P.ZICNTR_SUPPORTED) begin : HPMCSample
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if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleDelayed, BeginDelayed;
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@ -213,26 +213,41 @@ module loggers import cvw::*; #(parameter cvw_t P,
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if (P.BPRED_SUPPORTED) begin : BranchLogger
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if (BPRED_LOGGER) begin
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string direction;
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int file;
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int file, CFIfile;
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logic PCSrcM;
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string LogFile;
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string LogFile, CFILogFile;
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logic resetD, resetEdge;
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flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM);
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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initial begin
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LogFile = "branch.log"; // will break some of Ross's research analysis scripts
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CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
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//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
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file = $fopen(LogFile, "w");
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CFIfile = $fopen(CFILogFile, "w");
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end
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(resetEdge) begin
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$fwrite(file, "TRAIN\n");
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$fwrite(CFIfile, "TRAIN\n");
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end
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if(StartSample) begin
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$fwrite(file, "BEGIN %s\n", memfilename);
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$fwrite(CFIfile, "BEGIN %s\n", memfilename);
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end
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if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = PCSrcM ? "t" : "n";
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$fwrite(file, "%h %s\n", dut.core.PCM, direction);
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = PCSrcM ? "t" : "n";
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$fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
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end
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if(EndSample) begin
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$fwrite(file, "END %s\n", memfilename);
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$fwrite(CFIfile, "END %s\n", memfilename);
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end
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end
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end
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end
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@ -226,21 +226,6 @@ module testbench;
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///////////////////////////////////////////////////////////////////////////////
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/////////////////////////////// Cache Issue ///////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Duplicate copy of pipeline registers that are optimized out of some configurations
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logic [31:0] NextInstrE, InstrM;
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mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
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flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
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logic probe;
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if (NO_SPOOFING)
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assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
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& InstrM != 32'h14021273
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& testbench.dut.core.InstrValidM;
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@ -262,6 +247,7 @@ module testbench;
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logic HCLK, HRESETn;
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logic HREADY;
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logic HSELEXT;
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logic HSELEXTSDC;
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logic [P.PA_BITS-1:0] HADDR;
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logic [P.AHBW-1:0] HWDATA;
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logic [P.XLEN/8-1:0] HWSTRB;
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@ -292,6 +278,21 @@ module testbench;
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assign SDCIntr = 0;
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///////////////////////////////////////////////////////////////////////////////
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/////////////////////////////// Cache Issue ///////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Duplicate copy of pipeline registers that are optimized out of some configurations
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logic [31:0] NextInstrE, InstrM;
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mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
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flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
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logic probe;
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if (NO_SPOOFING)
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assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
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& InstrM != 32'h14021273
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& testbench.dut.core.InstrValidM;
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`ifdef USE_IMPERAS_DV
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@ -445,7 +446,7 @@ module testbench;
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wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
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.UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
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// W-stage hardware not needed by Wally itself
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parameter nop = 'h13;
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