From efc1d732d800b87128480d977d1b8e7480dcc43d Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 14 Nov 2023 12:57:44 -0600 Subject: [PATCH 1/8] Fixed the imperas testbench to be compatible with the config changes. --- testbench/testbench-imperas.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv index b503372d4..c27722f9f 100644 --- a/testbench/testbench-imperas.sv +++ b/testbench/testbench-imperas.sv @@ -237,7 +237,7 @@ module testbench; assign HRDATAEXT = 0; end - if(P.FPGA) begin : sdcard + if(P.SDC_SUPPORTED) begin : sdcard // *** fix later /* -----\/----- EXCLUDED -----\/----- sdModel sdcard From 1c54a5698b2ce1f30ac85263b7117d9ec56e7ef6 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 14 Nov 2023 13:54:16 -0600 Subject: [PATCH 2/8] Modified the device trees to include all the minor extensions. --- linux/devicetree/wally-artya7.dts | 1 + linux/devicetree/wally-virt.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 6dab66c7b..1ad559bbc 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -31,6 +31,7 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; + riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; mmu-type = "riscv,sv48"; interrupt-controller { diff --git a/linux/devicetree/wally-virt.dts b/linux/devicetree/wally-virt.dts index 7cc0f757a..edf602df3 100644 --- a/linux/devicetree/wally-virt.dts +++ b/linux/devicetree/wally-virt.dts @@ -31,6 +31,7 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; + riscv,isa-extensions = "svadu"; mmu-type = "riscv,sv48"; interrupt-controller { From feb45b9b591e0848c81184d34468f12bb1798565 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 14 Nov 2023 14:20:13 -0600 Subject: [PATCH 3/8] Patched up linux imperas testbench. --- sim/wally-linux-imperas.do | 2 + testbench/testbench-linux-imperas.sv | 63 ++++++++++++++-------------- 2 files changed, 34 insertions(+), 31 deletions(-) diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do index fcf6ceec4..f173f67c9 100644 --- a/sim/wally-linux-imperas.do +++ b/sim/wally-linux-imperas.do @@ -55,11 +55,13 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \ ../src/cvw.sv \ ../testbench/testbench-linux-imperas.sv \ ../testbench/common/*.sv ../src/*/*.sv \ diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index d38535003..501682fa8 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -226,21 +226,6 @@ module testbench; - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// Cache Issue /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - - // Duplicate copy of pipeline registers that are optimized out of some configurations - logic [31:0] NextInstrE, InstrM; - mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE); - flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM); - - logic probe; - if (NO_SPOOFING) - assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c - & InstrM != 32'h14021273 - & testbench.dut.core.InstrValidM; - @@ -261,19 +246,20 @@ module testbench; logic HREADYEXT, HRESPEXT; logic HCLK, HRESETn; logic HREADY; - logic HSELEXT; + logic HSELEXT; + logic HSELEXTSDC; logic [P.PA_BITS-1:0] HADDR; - logic [P.AHBW-1:0] HWDATA; - logic [P.XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic [31:0] GPIOIN; - logic [31:0] GPIOOUT, GPIOEN; - logic UARTSin, UARTSout; + logic [P.AHBW-1:0] HWDATA; + logic [P.XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic [31:0] GPIOIN; + logic [31:0] GPIOOUT, GPIOEN; + logic UARTSin, UARTSout; // FPGA-specific Stuff logic SDCCLK; @@ -292,6 +278,21 @@ module testbench; assign SDCIntr = 0; + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////// Cache Issue /////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + + // Duplicate copy of pipeline registers that are optimized out of some configurations + logic [31:0] NextInstrE, InstrM; + mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE); + flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM); + + logic probe; + if (NO_SPOOFING) + assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c + & InstrM != 32'h14021273 + & testbench.dut.core.InstrValidM; + `ifdef USE_IMPERAS_DV @@ -442,10 +443,10 @@ module testbench; // Wally - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); // W-stage hardware not needed by Wally itself parameter nop = 'h13; From 5d4a89b27c15e9ac0749fcb2daeb284fa6a29053 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 15 Nov 2023 14:51:47 -0600 Subject: [PATCH 4/8] Fixed bug in the btb branch logging. We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp. --- testbench/common/loggers.sv | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index db259da7a..28845eb45 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -213,26 +213,41 @@ module loggers import cvw::*; #(parameter cvw_t P, if (P.BPRED_SUPPORTED) begin : BranchLogger if (BPRED_LOGGER) begin string direction; - int file; + int file, CFIfile; logic PCSrcM; - string LogFile; + string LogFile, CFILogFile; logic resetD, resetEdge; flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM); flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin LogFile = "branch.log"; // will break some of Ross's research analysis scripts + CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); file = $fopen(LogFile, "w"); + CFIfile = $fopen(CFILogFile, "w"); end always @(posedge clk) begin - if(resetEdge) $fwrite(file, "TRAIN\n"); - if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(resetEdge) begin + $fwrite(file, "TRAIN\n"); + $fwrite(CFIfile, "TRAIN\n"); + end + if(StartSample) begin + $fwrite(file, "BEGIN %s\n", memfilename); + $fwrite(CFIfile, "BEGIN %s\n", memfilename); + end if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin direction = PCSrcM ? "t" : "n"; $fwrite(file, "%h %s\n", dut.core.PCM, direction); end - if(EndSample) $fwrite(file, "END %s\n", memfilename); + if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + direction = PCSrcM ? "t" : "n"; + $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction); + end + if(EndSample) begin + $fwrite(file, "END %s\n", memfilename); + $fwrite(CFIfile, "END %s\n", memfilename); + end end end end From bc935b1b3b83117dbb5f793685075ee531cfeab1 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 15 Nov 2023 14:56:02 -0600 Subject: [PATCH 5/8] Fixed second bug in the logger script when branch logging enabled but counter logger not. --- testbench/common/loggers.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 28845eb45..1cf719085 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -45,7 +45,7 @@ module loggers import cvw::*; #(parameter cvw_t P, // performance counter logging logic BeginSample; logic StartSample, EndSample; - if(PrintHPMCounters & P.ZICNTR_SUPPORTED) begin : HPMCSample + if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; logic StartSampleDelayed, BeginDelayed; From 9a90c15f37277d57d08fa8ed0eca7d971d9d157a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 15 Nov 2023 16:36:49 -0600 Subject: [PATCH 6/8] Extended SeparateBranch to support both just branches and all control flow instructions. --- bin/SeparateBranch.sh | 5 +++-- sim/bpred-sim.py | 15 ++++++++++++++- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index eb4ee4494..c81ba32c9 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -43,7 +43,8 @@ TrainLineNumberArray=($TrainLineNumbers) BeginLineNumberArray=($BeginLineNumbers) EndLineNumberArray=($EndLineNumbers) -mkdir -p branch +OutputPath=${File%%.*} +mkdir -p $OutputPath Length=${#EndLineNumberArray[@]} for i in $(seq 0 1 $((Length-1))) do @@ -51,5 +52,5 @@ do CurrTrain=$((${TrainLineNumberArray[$i]}+1)) CurrEnd=$((${EndLineNumberArray[$i]}-1)) echo $CurrName, $CurrTrain, $CurrEnd - sed -n "${CurrTrain},${CurrEnd}p" $File > branch/${CurrName}_branch.log + sed -n "${CurrTrain},${CurrEnd}p" $File > $OutputPath/${CurrName}_${File} done diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py index 209e21fc4..530fab70c 100755 --- a/sim/bpred-sim.py +++ b/sim/bpred-sim.py @@ -114,7 +114,20 @@ def main(): grepstr="") configs.append(tc) - if(args.target or args.iclass): + if(args.target): + # BTB and class size sweep + bpdSize = [6, 8, 10, 12, 14, 16] + for CurrBPSize in bpdSize: + name = 'BTB'+str(CurrBPSize) + configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+RAS_SIZE=16+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE" + tc = TestCase( + name=name, + variant="rv32gc", + cmd="vsim > {} -c < Date: Wed, 15 Nov 2023 16:39:35 -0600 Subject: [PATCH 7/8] Added btb reference data. --- bin/parseHPMC.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index bb6d2871e..2d6bb9008 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -32,10 +32,12 @@ import math import numpy as np import argparse -RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263), +RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263), ('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009), ('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534), ('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)] +RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 0.00478249129947965), ('BTBCModel8', 'BTBCModel', 256, 0.000398977702713851), ('BTBCModel10', 'BTBCModel', 1024, 2.42019646857733e-05), + ('BTBCModel12', 'BTBCModel', 4096, 8.7805838949138e-06), ('BTBCModel14', 'BTBCModel', 16384, 5.61562278846231e-06), ('BTBCModel16', 'BTBCModel', 65536, 5.61562278846231e-06)] def ParseBranchListFile(path): '''Take the path to the list of Questa Sim log files containing the performance counters outputs. File @@ -436,7 +438,8 @@ performanceCounterList = BuildDataBase(predictorLogs) # builds a databas benchmarkFirstList = ReorderDataBase(performanceCounterList) # reorder first by benchmark then trace benchmarkDict = ExtractSelectedData(benchmarkFirstList) # filters to just the desired performance counter metric -if(args.reference): benchmarkDict['Mean'].extend(RefData) +if(args.reference and args.direction): benchmarkDict['Mean'].extend(RefDataBP) +if(args.reference and args.target): benchmarkDict['Mean'].extend(RefDataBTB) #print(benchmarkDict['Mean']) #print(benchmarkDict['aha-mont64Speed']) #print(benchmarkDict) From 21b2a71bd6b4a7ad8dee00c5db2e77d47b64cf4a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 15 Nov 2023 16:53:44 -0600 Subject: [PATCH 8/8] Updates to btb logger processing. --- bin/CModelBTBAccuracy.sh | 2 +- bin/parseHPMC.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 5cde4238c..e4a26fb85 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -52,6 +52,6 @@ do # with such long precision bc outputs onto multiple lines # must remove \n and \ from string Product=`echo "$Product" | tr -d '\n' | tr -d '\\\'` - GeoMean=`perl -E "say $Product**(1/$Count)"` + GeoMean=`perl -E "say $Product**(1/$Count) * 100"` echo "$Pred$Size $GeoMean" done diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 2d6bb9008..8e274a200 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -36,8 +36,8 @@ RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCM ('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009), ('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534), ('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)] -RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 0.00478249129947965), ('BTBCModel8', 'BTBCModel', 256, 0.000398977702713851), ('BTBCModel10', 'BTBCModel', 1024, 2.42019646857733e-05), - ('BTBCModel12', 'BTBCModel', 4096, 8.7805838949138e-06), ('BTBCModel14', 'BTBCModel', 16384, 5.61562278846231e-06), ('BTBCModel16', 'BTBCModel', 65536, 5.61562278846231e-06)] +RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.11806778745097), ('BTBCModel8', 'BTBCModel', 256, 0.183833943219956), ('BTBCModel10', 'BTBCModel', 1024, 0.0109271020749376), + ('BTBCModel12', 'BTBCModel', 4096, 0.00437600802791213), ('BTBCModel14', 'BTBCModel', 16384, 0.00188756234204305), ('BTBCModel16', 'BTBCModel', 65536, 0.00188756234204305)] def ParseBranchListFile(path): '''Take the path to the list of Questa Sim log files containing the performance counters outputs. File