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Fixed interger divide so it can be interrupted.

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Ross Thompson 2022-01-13 11:16:50 -06:00
parent 000d713cb5
commit 93cb24476f
1 changed files with 1 additions and 1 deletions
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pipelined/src/hazard/hazard.sv
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@ -62,7 +62,7 @@ module hazard(
assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = DivBusyE | FDivBusyE;
assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
assign StallMCause = 0;
assign StallWCause = LSUStall | IFUStallF;