From 93cb24476f0ccef026533eb9c96ab00ea3ec6cac Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 13 Jan 2022 11:16:50 -0600 Subject: [PATCH] Fixed interger divide so it can be interrupted. --- pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 999406a99..d369bd43b 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -62,7 +62,7 @@ module hazard( assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE); assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallECause = DivBusyE | FDivBusyE; + assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); assign StallMCause = 0; assign StallWCause = LSUStall | IFUStallF;