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Merge branch 'main' of https://github.com/openhwgroup/cvw into breker

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Jordan Carlin 2024-12-08 20:57:18 -08:00
commit 93813e8614
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10 changed files with 137 additions and 816 deletions
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1
.gitignore vendored
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@ -12,6 +12,7 @@
*.map
*.elf*
*.list
*.memfile
# General directories to ignore
.vscode/

153
bin/wsim
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@ -13,6 +13,7 @@
import argparse
import os
import sys
# Global variable
WALLY = os.environ.get('WALLY')
@ -31,28 +32,26 @@ def parseArgs():
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
return parser.parse_args()
def validateArgs(args):
if not args.testsuite and not args.elf:
print("Error: Missing test suite or ELF file")
exit(1)
if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot" :
print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
exit(1)
elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]:
sys.exit(1)
if any([args.lockstep, args.lockstepverbose, args.fcov]) and not (args.testsuite.endswith('.elf') or args.elf) and args.testsuite != "buildroot":
print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep or fcov. Must run a single elf or buildroot.")
sys.exit(1)
elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]:
print("Option only supported for Questa and VCS")
exit(1)
sys.exit(1)
elif (args.tb == "testbench_fp" and args.sim != "questa"):
print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench")
exit(1)
sys.exit(1)
elif ("breker" in args.elf or "breker" in args.testsuite) and args.sim != "questa":
print("Error: Breker tests currently only supported by Questa")
exit(1)
sys.exit(1)
def elfFileCheck(args):
ElfFile = ""
@ -60,128 +59,118 @@ def elfFileCheck(args):
ElfFile = f"+ElfFile={os.path.abspath(args.elf)}"
elif args.elf != "":
print(f"ELF file not found: {args.elf}")
exit(1)
sys.exit(1)
elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead
if os.path.isfile(args.testsuite):
ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}"
# extract the elf name from the path to be the test suite
fields = args.testsuite.rsplit('/', 3)
# if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
if ("breker" in args.testsuite):
if "breker" in args.testsuite:
args.testsuite = fields[-1]
elif (len(fields) > 3):
if (fields[2] == "ref"):
elif len(fields) > 3:
if fields[2] == "ref":
args.testsuite = f"{fields[1]}_{fields[3]}"
else:
args.testsuite = f"{fields[2]}_{fields[3]}"
elif ('/' in args.testsuite):
elif '/' in args.testsuite:
args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present
else:
print(f"ELF file not found: {args.testsuite}")
exit(1)
sys.exit(1)
return ElfFile
def prepSim(args, ElfFile):
flags = ""
prefix = ""
paramsList = []
argsList = []
flagsList = []
if args.vcd:
args.args += " -DMAKEVCD=1"
paramsList.append("MAKE_VCD=1")
if args.rvvi:
args.params += " RVVI_SYNTH_SUPPORTED=1 "
paramsList.append("RVVI_SYNTH_SUPPORTED=1")
if args.tb == "testbench_fp":
args.params += f' TEST="{args.testsuite}" '
if ElfFile != "":
args.args += f" {ElfFile}"
paramsList.append(f'TEST="{args.testsuite}"')
if ElfFile:
argsList.append(f"{ElfFile}")
if args.gui and args.tb == "testbench":
paramsList.append("DEBUG=1")
if args.ccov:
flags += " --ccov"
flagsList.append("--ccov")
if args.fcov:
flags += " --fcov"
flagsList.append("--fcov")
if args.gui:
flagsList.append("--gui")
if args.lockstep or args.lockstepverbose:
flagsList.append("--lockstep")
if args.lockstep or args.lockstepverbose or args.fcov:
prefix = lockstepSetup(args)
if "breker" in ElfFile:
flags += " --breker"
prefix, suffix = lockstepSetup(args)
flags += suffix
flagsList.append("--breker")
# Combine into a single string
args.args += " ".join(argsList)
args.params += " ".join(paramsList)
flags = " ".join(flagsList)
return flags, prefix
def lockstepSetup(args):
prefix = ""
suffix = ""
ImperasPlusArgs = ""
imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic")
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath):
print("Error: imperas.ic not found")
sys.exit(1)
prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
return prefix
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
if (args.lockstep or args.lockstepverbose or args.fcov):
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath):
print("Error: imperas.ic not found")
exit(1)
prefix += f"IMPERAS_TOOLS={imperasicPath}"
if (args.lockstep or args.lockstepverbose):
if(args.locksteplog != 0): ImperasPlusArgs = f" +IDV_TRACE2LOG={EnableLog} +IDV_TRACE2LOG_AFTER={args.locksteplog}"
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0"
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = f" +IDV_TRACE2COV={EnableLog} +TRACE2LOG_AFTER={args.covlog} +TRACE2COV_ENABLE={CovEnableStr}"
else:
suffix = "--lockstep"
if(args.lockstepverbose):
prefix += f":{WALLY}/sim/imperas-verbose.ic"
args.args += ImperasPlusArgs
return prefix, suffix
def createDirs(args):
def createDirs(sim):
for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
os.makedirs(os.path.join(WALLY, "sim", args.sim, d), exist_ok=True)
os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True)
def runSim(args, flags, prefix):
if (args.sim == "questa"):
if args.sim == "questa":
runQuesta(args, flags, prefix)
elif (args.sim == "verilator"):
runVerilator(args, flags, prefix)
elif (args.sim == "vcs"):
elif args.sim == "verilator":
runVerilator(args)
elif args.sim == "vcs":
runVCS(args, flags, prefix)
def runQuesta(args, flags, prefix):
# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
prefix = "MTI_VCO_MODE=64 " + prefix
if (args.gui) and (args.tb == "testbench"):
args.params += "DEBUG=1"
if (args.args != ""):
args.args = f' --args \\"{args.args}\\"'
if (args.params != ""):
args.params = f' --params \\"{args.params}\\"'
if args.args != "":
args.args = fr'--args \"{args.args}\"'
if args.params != "":
args.params = fr'--params \"{args.params}\"'
# Questa cannot accept more than 9 arguments. fcov implies lockstep
cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}"
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
cmd = f'cd $WALLY/sim/questa; {prefix} vsim -do "{cmd} +acc"'
else: # launch Questa in batch mode
cmd = f'cd $WALLY/sim/questa; {prefix} vsim -c -do "{cmd}"'
cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
print(f"Running Questa with command: {cmd}")
os.system(cmd)
def runVerilator(args, flags, prefix):
def runVerilator(args):
print(f"Running Verilator on {args.config} {args.testsuite}")
os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"')
def runVCS(args, flags, prefix):
print(f"Running VCS on {args.config} {args.testsuite}")
# if (args.gui):
# flags += " --gui"
if (args.args != ""):
args.args = f' --args "{args.args}" '
if (args.params != ""):
args.params = f' --params "{args.params}" '
if args.args != "":
args.args = f'--args "{args.args}"'
if args.params != "":
args.params = f'--params "{args.params}"'
cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}"
print(cmd)
os.system(cmd)
if __name__ == "__main__":
args = parseArgs()
def main(args):
validateArgs(args)
print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'")
ElfFile = elfFileCheck(args)
flags, prefix = prepSim(args, ElfFile)
createDirs(args)
exit(runSim(args, flags, prefix))
createDirs(args.sim)
sys.exit(runSim(args, flags, prefix))
if __name__ == "__main__":
args = parseArgs()
main(args)

669
fpga/src/axi_sdc_controller.v
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@ -1,669 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
module sdc_controller #(
parameter dma_addr_bits = 32,
parameter fifo_addr_bits = 7,
parameter sdio_card_detect_level = 1,
parameter voltage_controll_reg = 3300,
parameter capabilies_reg = 16'b0000_0000_0000_0011
) (
input wire async_resetn,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *)
input wire clock,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *)
input wire [15:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
output wire s_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
output wire s_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
output reg [1:0] s_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
output reg s_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
input wire [15:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
output wire s_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
output reg [31:0] s_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
output reg [1:0] s_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
output reg s_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output reg [dma_addr_bits-1:0] m_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output reg [7:0] m_axi_awlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output reg m_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31:0] m_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output reg m_axi_wlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output reg m_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1:0] m_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output reg [dma_addr_bits-1:0] m_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output reg [7:0] m_axi_arlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output reg m_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31:0] m_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1:0] m_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready,
// SD BUS
//inout wire sdio_cmd,
//inout wire [3:0] sdio_dat,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *)
(* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *)
output reg sdio_clk,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
output reg sdio_reset,
input wire sdio_cd,
output reg sd_dat_reg_t,
output reg [3:0] sd_dat_reg_o,
input wire [3:0] sd_dat_i,
output reg sd_cmd_reg_t,
output reg sd_cmd_reg_o,
input wire sd_cmd_i,
// Interrupts
output wire interrupt
);
`include "sd_defines.h"
wire reset;
wire go_idle;
reg cmd_start;
wire [1:0] cmd_setting;
wire cmd_start_tx;
wire [39:0] cmd;
wire [119:0] cmd_response;
wire cmd_crc_ok;
wire cmd_index_ok;
wire cmd_finish;
wire d_write;
wire d_read;
wire [31:0] data_in_rx_fifo;
wire en_tx_fifo;
wire en_rx_fifo;
wire sd_data_busy;
(* mark_debug = "true" *) wire data_busy;
wire data_crc_ok;
wire tx_fifo_re;
wire rx_fifo_we;
reg data_start_rx;
reg data_start_tx;
reg data_prepare_tx;
reg cmd_int_rst;
reg data_int_rst;
reg ctrl_rst;
// AXI accessible registers
(* mark_debug = "true" *) reg [31:0] argument_reg;
(* mark_debug = "true" *) reg [`CMD_REG_SIZE-1:0] command_reg;
(* mark_debug = "true" *) reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
(* mark_debug = "true" *) reg [0:0] software_reset_reg;
(* mark_debug = "true" *) wire [31:0] response_0_reg;
(* mark_debug = "true" *) wire [31:0] response_1_reg;
(* mark_debug = "true" *) wire [31:0] response_2_reg;
(* mark_debug = "true" *) wire [31:0] response_3_reg;
(* mark_debug = "true" *) reg [`BLKSIZE_W-1:0] block_size_reg;
(* mark_debug = "true" *) reg [1:0] controller_setting_reg;
(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status;
(* mark_debug = "true" *) reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
(* mark_debug = "true" *) reg [`INT_DATA_SIZE-1:0] data_int_enable_reg;
(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] block_count_reg;
(* mark_debug = "true" *) reg [dma_addr_bits-1:0] dma_addr_reg;
(* mark_debug = "true" *) reg [7:0] clock_divider_reg = 124; // 400KHz
// ------ Clocks and resets
(* ASYNC_REG="true" *)
reg [2:0] reset_sync;
assign reset = reset_sync[2];
always @(posedge clock)
reset_sync <= {reset_sync[1:0], !async_resetn};
reg [7:0] clock_cnt;
(* mark_debug = "true" *) reg clock_state;
(* mark_debug = "true" *) reg clock_posedge;
reg clock_data_in;
wire fifo_almost_full;
wire fifo_almost_empty;
always @(posedge clock) begin
if (reset) begin
clock_posedge <= 0;
clock_data_in <= 0;
clock_state <= 0;
clock_cnt <= 0;
end else if (clock_cnt < clock_divider_reg) begin
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else if (clock_cnt < 124 && data_busy && en_rx_fifo && fifo_almost_full) begin
// Prevent Rx FIFO overflow
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else if (clock_cnt < 124 && data_busy && en_tx_fifo && fifo_almost_empty) begin
// Prevent Tx FIFO underflow
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else begin
clock_state <= !clock_state;
clock_posedge <= !clock_state;
if (clock_divider_reg == 0)
clock_data_in <= !clock_state;
else
clock_data_in <= clock_state;
clock_cnt <= 0;
end
sdio_clk <= sdio_reset || clock_state;
if (reset) sdio_reset <= 0;
else if (clock_posedge) sdio_reset <= controller_setting_reg[1];
end
// ------ SD IO Buffers
// wire sd_cmd_i;
wire sd_cmd_o;
wire sd_cmd_oe;
// reg sd_cmd_reg_o;
// reg sd_cmd_reg_t;
// wire [3:0] sd_dat_i;
wire [3:0] sd_dat_o;
wire sd_dat_oe;
// reg [3:0] sd_dat_reg_o;
// reg sd_dat_reg_t;
// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
always @(negedge sdio_clk) begin
// Output data delayed by 1/2 clock cycle (5ns) to ensure
// required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
if (sdio_reset) begin
sd_cmd_reg_o <= 0;
sd_dat_reg_o <= 0;
sd_cmd_reg_t <= 0;
sd_dat_reg_t <= 0;
end else begin
sd_cmd_reg_o <= sd_cmd_o;
sd_dat_reg_o <= sd_dat_o;
sd_cmd_reg_t <= !sd_cmd_oe;
sd_dat_reg_t <= !(sd_dat_oe || (cmd_start_tx && (command_reg == 0)));
end
end
// ------ SD card detect
reg [25:0] sd_detect_cnt;
wire sd_insert_int = sd_detect_cnt[25];
wire sd_remove_int = !sd_detect_cnt[25];
reg sd_insert_ie;
reg sd_remove_ie;
always @(posedge clock) begin
if (sdio_cd != sdio_card_detect_level) begin
sd_detect_cnt <= 0;
end else if (!sd_insert_int) begin
sd_detect_cnt <= sd_detect_cnt + 1;
end
end
// ------ AXI Slave Interface
reg [15:0] read_addr;
reg [15:0] write_addr;
reg [31:0] write_data;
reg rd_req;
reg [1:0] wr_req;
assign s_axi_arready = !rd_req && !s_axi_rvalid;
assign s_axi_awready = !wr_req[0] && !s_axi_bvalid;
assign s_axi_wready = !wr_req[1] && !s_axi_bvalid;
always @(posedge clock) begin
if (reset) begin
s_axi_rdata <= 0;
s_axi_rresp <= 0;
s_axi_rvalid <= 0;
s_axi_bresp <= 0;
s_axi_bvalid <= 0;
rd_req <= 0;
wr_req <= 0;
read_addr <= 0;
write_addr <= 0;
write_data <= 0;
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
ctrl_rst <= 0;
argument_reg <= 0;
command_reg <= 0;
cmd_timeout_reg <= 0;
data_timeout_reg <= 0;
block_size_reg <= `RESET_BLOCK_SIZE;
controller_setting_reg <= 0;
cmd_int_enable_reg <= 0;
data_int_enable_reg <= 0;
software_reset_reg <= 0;
clock_divider_reg <= `RESET_CLOCK_DIV;
block_count_reg <= 0;
sd_insert_ie <= 0;
sd_remove_ie <= 0;
dma_addr_reg <= 0;
end else begin
if (clock_posedge) begin
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
ctrl_rst <= software_reset_reg[0];
end
if (s_axi_arready && s_axi_arvalid) begin
read_addr <= s_axi_araddr;
rd_req <= 1;
end
if (s_axi_rvalid && s_axi_rready) begin
s_axi_rvalid <= 0;
end else if (!s_axi_rvalid && rd_req) begin
s_axi_rdata <= 0;
if (read_addr[15:8] == 0) begin
case (read_addr[7:0])
`argument : s_axi_rdata <= argument_reg;
`command : s_axi_rdata <= command_reg;
`resp0 : s_axi_rdata <= response_0_reg;
`resp1 : s_axi_rdata <= response_1_reg;
`resp2 : s_axi_rdata <= response_2_reg;
`resp3 : s_axi_rdata <= response_3_reg;
`controller : s_axi_rdata <= controller_setting_reg;
`blksize : s_axi_rdata <= block_size_reg;
`voltage : s_axi_rdata <= voltage_controll_reg;
`capa : s_axi_rdata <= capabilies_reg | (dma_addr_bits << 8);
`clock_d : s_axi_rdata <= clock_divider_reg;
`reset : s_axi_rdata <= { cmd_start, data_int_rst, cmd_int_rst, ctrl_rst };
`cmd_timeout : s_axi_rdata <= cmd_timeout_reg;
`data_timeout : s_axi_rdata <= data_timeout_reg;
`cmd_isr : s_axi_rdata <= cmd_int_status_reg;
`cmd_iser : s_axi_rdata <= cmd_int_enable_reg;
`data_isr : s_axi_rdata <= data_int_status_reg;
`data_iser : s_axi_rdata <= data_int_enable_reg;
`blkcnt : s_axi_rdata <= block_count_reg;
`card_detect : s_axi_rdata <= { sd_remove_int, sd_remove_ie, sd_insert_int, sd_insert_ie };
`dst_src_addr : s_axi_rdata <= dma_addr_reg[31:0];
`dst_src_addr_high : if (dma_addr_bits > 32) s_axi_rdata <= dma_addr_reg[dma_addr_bits-1:32];
endcase
end
s_axi_rresp <= 0;
s_axi_rvalid <= 1;
rd_req <= 0;
end
if (s_axi_awready && s_axi_awvalid) begin
write_addr <= s_axi_awaddr;
wr_req[0] <= 1;
end
if (s_axi_wready && s_axi_wvalid) begin
write_data <= s_axi_wdata;
wr_req[1] <= 1;
end
if (s_axi_bvalid && s_axi_bready) begin
s_axi_bvalid <= 0;
end else if (!s_axi_bvalid && wr_req == 2'b11) begin
if (write_addr[15:8] == 0) begin
case (write_addr[7:0])
`argument : begin argument_reg <= write_data; cmd_start <= 1; end
`command : command_reg <= write_data;
`reset : software_reset_reg <= write_data;
`cmd_timeout : cmd_timeout_reg <= write_data;
`data_timeout : data_timeout_reg <= write_data;
`blksize : block_size_reg <= write_data;
`controller : controller_setting_reg <= write_data;
`cmd_isr : cmd_int_rst <= 1;
`cmd_iser : cmd_int_enable_reg <= write_data;
`clock_d : clock_divider_reg <= write_data;
`data_isr : data_int_rst <= 1;
`data_iser : data_int_enable_reg <= write_data;
`blkcnt : block_count_reg <= write_data;
`card_detect : begin sd_remove_ie <= write_data[2]; sd_insert_ie <= write_data[0]; end
`dst_src_addr : dma_addr_reg[31:0] <= write_data;
`dst_src_addr_high : if (dma_addr_bits > 32) dma_addr_reg[dma_addr_bits-1:32] <= write_data;
endcase
end
s_axi_bresp <= 0;
s_axi_bvalid <= 1;
wr_req <= 0;
end
end
end
// ------ Data FIFO
reg [31:0] fifo_mem [(1<<fifo_addr_bits)-1:0];
reg [fifo_addr_bits-1:0] fifo_inp_pos;
reg [fifo_addr_bits-1:0] fifo_out_pos;
wire [fifo_addr_bits-1:0] fifo_inp_nxt = fifo_inp_pos + 1;
wire [fifo_addr_bits-1:0] fifo_out_nxt = fifo_out_pos + 1;
wire [fifo_addr_bits-1:0] fifo_data_len = fifo_inp_pos - fifo_out_pos;
wire [fifo_addr_bits-1:0] fifo_free_len = fifo_out_pos - fifo_inp_nxt;
wire fifo_full = fifo_inp_nxt == fifo_out_pos;
wire fifo_empty = fifo_inp_pos == fifo_out_pos;
wire fifo_ready = fifo_data_len >= (1 << fifo_addr_bits) / 2;
wire [31:0] fifo_din = en_rx_fifo ? data_in_rx_fifo : m_bus_dat_i;
wire fifo_we = en_rx_fifo ? rx_fifo_we && clock_posedge : m_axi_rready && m_axi_rvalid;
wire fifo_re = en_rx_fifo ? m_axi_wready && m_axi_wvalid : tx_fifo_re && clock_posedge;
reg [31:0] fifo_dout;
assign fifo_almost_full = fifo_data_len > (1 << fifo_addr_bits) * 3 / 4;
assign fifo_almost_empty = fifo_free_len > (1 << fifo_addr_bits) * 3 / 4;
wire tx_stb = en_tx_fifo && fifo_free_len >= (1 << fifo_addr_bits) / 3;
wire rx_stb = en_rx_fifo && m_axi_bresp_cnt != 3'b111 && (fifo_data_len >= (1 << fifo_addr_bits) / 3 || (!fifo_empty && !data_busy));
always @(posedge clock)
if (reset || ctrl_rst || !(en_rx_fifo || en_tx_fifo)) begin
fifo_inp_pos <= 0;
fifo_out_pos <= 0;
end else begin
if (fifo_we && !fifo_full) begin
fifo_mem[fifo_inp_pos] <= fifo_din;
fifo_inp_pos <= fifo_inp_nxt;
if (fifo_empty) fifo_dout <= fifo_din;
end
if (fifo_re && !fifo_empty) begin
if (fifo_we && !fifo_full && fifo_out_nxt == fifo_inp_pos) fifo_dout <= fifo_din;
else fifo_dout <= fifo_mem[fifo_out_nxt];
fifo_out_pos <= fifo_out_nxt;
end
end
// ------ AXI Master Interface
// AXI transaction (DDR access) is over 80 clock cycles
// Must use burst to achive required throughput
reg m_axi_cyc;
wire m_axi_write = en_rx_fifo;
reg [7:0] m_axi_wcnt;
reg [dma_addr_bits-1:2] m_bus_adr_o;
wire [31:0] m_bus_dat_i;
reg [2:0] m_axi_bresp_cnt;
reg m_bus_error;
assign m_axi_bready = m_axi_bresp_cnt != 0;
assign m_axi_rready = m_axi_cyc & !m_axi_write;
assign m_bus_dat_i = {m_axi_rdata[7:0],m_axi_rdata[15:8],m_axi_rdata[23:16],m_axi_rdata[31:24]};
assign m_axi_wdata = {fifo_dout[7:0],fifo_dout[15:8],fifo_dout[23:16],fifo_dout[31:24]};
// AXI burst cannot cross a 4KB boundary
wire [fifo_addr_bits-1:0] tx_burst_len;
wire [fifo_addr_bits-1:0] rx_burst_len;
assign tx_burst_len = m_bus_adr_o[11:2] + fifo_free_len >= m_bus_adr_o[11:2] ? fifo_free_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
assign rx_burst_len = m_bus_adr_o[11:2] + fifo_data_len >= m_bus_adr_o[11:2] ? fifo_data_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
assign data_int_status_reg = { data_int_status[`INT_DATA_SIZE-1:1],
!en_rx_fifo && !en_tx_fifo && !m_axi_cyc && m_axi_bresp_cnt == 0 && data_int_status[0] };
always @(posedge clock) begin
if (reset | ctrl_rst) begin
m_axi_arvalid <= 0;
m_axi_awvalid <= 0;
m_axi_wvalid <= 0;
m_axi_cyc <= 0;
end else if (m_axi_cyc) begin
if (m_axi_awvalid && m_axi_awready) begin
m_axi_awvalid <= 0;
end
if (m_axi_arvalid && m_axi_arready) begin
m_axi_arvalid <= 0;
end
if (m_axi_wvalid && m_axi_wready) begin
if (m_axi_wlast) begin
m_axi_wvalid <= 0;
m_axi_cyc <= 0;
end else begin
m_axi_wlast <= m_axi_wcnt + 1 == m_axi_awlen;
m_axi_wcnt <= m_axi_wcnt + 1;
end
end
if (m_axi_rvalid && m_axi_rready && m_axi_rlast) begin
m_axi_cyc <= 0;
end
end else if (tx_stb || rx_stb) begin
m_axi_cyc <= 1;
m_axi_wcnt <= 0;
if (m_axi_write) begin
m_axi_awaddr <= { m_bus_adr_o, 2'b00 };
m_axi_awlen <= rx_burst_len < 8'hff ? rx_burst_len : 8'hff;
m_axi_wlast <= rx_burst_len == 0;
m_axi_awvalid <= 1;
m_axi_wvalid <= 1;
end else begin
m_axi_araddr <= { m_bus_adr_o, 2'b00 };
m_axi_arlen <= tx_burst_len < 8'hff ? tx_burst_len : 8'hff;
m_axi_arvalid <= 1;
end
end
if (reset | ctrl_rst) begin
m_bus_adr_o <= 0;
end else if ((m_axi_wready && m_axi_wvalid) || (m_axi_rready && m_axi_rvalid)) begin
m_bus_adr_o <= m_bus_adr_o + 1;
end else if (!m_axi_cyc && !en_rx_fifo && !en_tx_fifo) begin
m_bus_adr_o <= dma_addr_reg[dma_addr_bits-1:2];
end
if (reset | ctrl_rst) begin
m_axi_bresp_cnt <= 0;
end else if ((m_axi_awvalid && m_axi_awready) && !(m_axi_bvalid && m_axi_bready)) begin
m_axi_bresp_cnt <= m_axi_bresp_cnt + 1;
end else if (!(m_axi_awvalid && m_axi_awready) && (m_axi_bvalid && m_axi_bready)) begin
m_axi_bresp_cnt <= m_axi_bresp_cnt - 1;
end
if (reset | ctrl_rst | cmd_start) begin
m_bus_error <= 0;
end else if (m_axi_bvalid && m_axi_bready && m_axi_bresp) begin
m_bus_error <= 1;
end else if (m_axi_rvalid && m_axi_rready && m_axi_rresp) begin
m_bus_error <= 1;
end
if (reset | ctrl_rst) begin
data_start_tx <= 0;
data_start_rx <= 0;
data_prepare_tx <= 0;
end else if (clock_posedge) begin
data_start_tx <= 0;
data_start_rx <= 0;
if (cmd_start) begin
data_prepare_tx <= 0;
if (command_reg[`CMD_WITH_DATA] == 2'b01) data_start_rx <= 1;
else if (command_reg[`CMD_WITH_DATA] != 2'b00) data_prepare_tx <= 1;
end else if (data_prepare_tx) begin
if (cmd_int_status_reg[`INT_CMD_CC]) begin
data_prepare_tx <= 0;
data_start_tx <= 1;
end else if (cmd_int_status_reg[`INT_CMD_EI]) begin
data_prepare_tx <= 0;
end
end
end
end
// ------ SD Card Interface
sd_cmd_master sd_cmd_master0(
.clock (clock),
.clock_posedge (clock_posedge),
.reset (reset | ctrl_rst),
.start (cmd_start),
.int_status_rst (cmd_int_rst),
.setting (cmd_setting),
.start_xfr (cmd_start_tx),
.go_idle (go_idle),
.cmd (cmd),
.response (cmd_response),
.crc_error (!cmd_crc_ok),
.index_ok (cmd_index_ok),
.busy (sd_data_busy),
.finish (cmd_finish),
.argument (argument_reg),
.command (command_reg),
.timeout (cmd_timeout_reg),
.int_status (cmd_int_status_reg),
.response_0 (response_0_reg),
.response_1 (response_1_reg),
.response_2 (response_2_reg),
.response_3 (response_3_reg)
);
sd_cmd_serial_host cmd_serial_host0(
.clock (clock),
.clock_posedge (clock_posedge),
.clock_data_in (clock_data_in),
.reset (reset | ctrl_rst | go_idle),
.setting (cmd_setting),
.cmd (cmd),
.start (cmd_start_tx),
.finish (cmd_finish),
.response (cmd_response),
.crc_ok (cmd_crc_ok),
.index_ok (cmd_index_ok),
.cmd_i (sd_cmd_i),
.cmd_o (sd_cmd_o),
.cmd_oe (sd_cmd_oe)
);
sd_data_master sd_data_master0(
.clock (clock),
.clock_posedge (clock_posedge),
.reset (reset | ctrl_rst),
.start_tx (data_start_tx),
.start_rx (data_start_rx),
.timeout (data_timeout_reg),
.d_write (d_write),
.d_read (d_read),
.en_tx_fifo (en_tx_fifo),
.en_rx_fifo (en_rx_fifo),
.fifo_empty (fifo_empty),
.fifo_ready (fifo_ready),
.fifo_full (fifo_full),
.bus_cycle (m_axi_cyc || m_axi_bresp_cnt != 0),
.xfr_complete (!data_busy),
.crc_error (!data_crc_ok),
.bus_error (m_bus_error),
.int_status (data_int_status),
.int_status_rst (data_int_rst)
);
sd_data_serial_host sd_data_serial_host0(
.clock (clock),
.clock_posedge (clock_posedge),
.clock_data_in (clock_data_in),
.reset (reset | ctrl_rst),
.data_in (fifo_dout),
.rd (tx_fifo_re),
.data_out (data_in_rx_fifo),
.we (rx_fifo_we),
.dat_oe (sd_dat_oe),
.dat_o (sd_dat_o),
.dat_i (sd_dat_i),
.blksize (block_size_reg),
.bus_4bit (controller_setting_reg[0]),
.blkcnt (block_count_reg),
.start ({d_read, d_write}),
.byte_alignment (dma_addr_reg[1:0]),
.sd_data_busy (sd_data_busy),
.busy (data_busy),
.crc_ok (data_crc_ok)
);
assign interrupt =
|(cmd_int_status_reg & cmd_int_enable_reg) ||
|(data_int_status_reg & data_int_enable_reg) ||
(sd_insert_int & sd_insert_ie) ||
(sd_remove_int & sd_remove_ie);
endmodule

6
sim/questa/wally.do
View File

@ -8,7 +8,7 @@
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [+acc] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"]
# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"]
# Example: do wally.do rv64gc arch64i testbench
# Use this wally.do file to run this example.
@ -41,7 +41,6 @@ set TESTSUITE_NO_ELF [file rootname ${TESTSUITE}]
set TESTBENCH ${3}
set WKDIR wkdir/${CFG}_${TESTSUITE}
set WALLY $::env(WALLY)
set IMPERAS_HOME $::env(IMPERAS_HOME)
set CONFIG ${WALLY}/config
set SRC ${WALLY}/src
set TB ${WALLY}/testbench
@ -98,7 +97,7 @@ echo "number of args = $argc"
echo "lst = $lst"
# if +acc found set flag and remove from list
if {[lcheck lst "+acc"]} {
if {[lcheck lst "--gui"]} {
set GUI 1
set accFlag "+acc"
}
@ -123,6 +122,7 @@ if {[lcheck lst "--fcov"]} {
# if --lockstep or --fcov found set flag and remove from list
if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} {
set IMPERAS_HOME $::env(IMPERAS_HOME)
set lockstep 1
set lockstepvlog "+define+USE_IMPERAS_DV \
+incdir+${IMPERAS_HOME}/ImpPublic/include/host \

8
sim/vcs/run_vcs
View File

@ -24,8 +24,8 @@ parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
@ -65,7 +65,7 @@ else:
LOCKSTEP_SIMV = ""
# coverage mode
if (args.coverage):
if (args.ccov):
COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage"
else:
COV_OPTIONS = ""
@ -93,6 +93,6 @@ SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args +
print("Executing: " + str(VCS) )
subprocess.run(VCS, shell=True)
subprocess.run(SIMV_CMD, shell=True)
if (args.coverage):
if (args.ccov):
COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite
subprocess.run(COV_RUN, shell=True)

16
sim/verilator/Makefile
View File

@ -17,12 +17,10 @@ EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS))
WALLYCONF?=rv64gc
TEST?=arch64i
TESTBENCH?=testbench
TESTBENCH?=testbench
# constants
# assume WALLY variable is correctly configured in the shell environment
WORKING_DIR=${WALLY}/sim/verilator
TARGET=$(WORKING_DIR)/target
# INCLUDE_PATH are pathes that Verilator should search for files it needs
INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
# SOURCES are source files
@ -30,6 +28,8 @@ SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbenc
# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
WORKDIR = $(VERILATOR_DIR)/wkdir/$(WALLYCONF)_$(TEST)
# regular testbench requires a wrapper defining getenvval
ifeq ($(TESTBENCH), testbench)
WRAPPER=${WALLY}/sim/verilator/wrapper.c
@ -41,9 +41,9 @@ endif
default: run
run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
run: $(WORKDIR)/V${TESTBENCH}
mkdir -p $(VERILATOR_DIR)/logs
wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
$(WORKDIR)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
@ -54,10 +54,10 @@ profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES)
mkdir -p wkdir/$(WALLYCONF)_$(TEST)
$(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES)
mkdir -p $(WORKDIR)
verilator \
--Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \
--Mdir $(WORKDIR) -o V${TESTBENCH} \
--binary --trace \
$(OPT) $(PARAMS) $(NONPROF) \
--top-module ${TESTBENCH} --relative-includes \

8
src/uncore/spi_apb.sv
View File

@ -174,16 +174,12 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
SPI_CSMODE: ChipSelectMode <= Din[1:0];
SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]};
SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
SPI_TXMARK: TransmitWatermark <= Din[2:0];
SPI_RXMARK: ReceiveWatermark <= Din[2:0];
SPI_IE: InterruptEnable <= Din[1:0];
endcase
if (Memwrite)
case(Entry)
SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
endcase
/* verilator lint_on CASEINCOMPLETE */
// According to FU540 spec: Once interrupt is pending, it will remain set until number

41
src/uncore/spi_controller.sv
View File

@ -75,6 +75,7 @@ module spi_controller (
logic ShiftEdgePulse;
logic SampleEdgePulse;
logic EndOfFramePulse;
logic InvertClock;
// Frame stuff
logic [3:0] BitNum;
@ -107,8 +108,8 @@ module spi_controller (
logic [7:0] DelayCounter;
logic DelayIsNext;
logic DelayState;
logic DelayState;
// Convenient Delay Reg Names
assign cssck = Delay0[7:0];
assign sckcs = Delay0[15:8];
@ -130,10 +131,6 @@ module spi_controller (
assign EndOfDelay = EndOfCSSCK | EndOfSCKCS | EndOfINTERCS | EndOfINTERXFR;
// Clock Signal Stuff -----------------------------------------------
// I'm going to handle all clock stuff here, including ShiftEdge and
// SampleEdge. This makes sure that SPICLK is an output of a register
// and it properly synchronizes signals.
// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
@ -166,12 +163,14 @@ module spi_controller (
end
// SPICLK Logic
// We only want to trigger the clock during Transmission.
// If Phase == 1, then we want to trigger as soon as NextState == TRANSMIT
// Otherwise, only trigger the clock when the CurrState is TRANSMIT.
// We never want to trigger the clock if the NextState is NOT TRANSMIT
if (TransmitStart & ~DelayState) begin
SPICLK <= SckMode[1];
end else if (SCLKenable) begin
if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
end else if (SCLKenable) begin
SPICLK <= (NextState == TRANSMIT) & (~Phase & Transmitting | Phase) ? ~SPICLK : SckMode[1];
end
// Reset divider
@ -201,32 +200,25 @@ module spi_controller (
// Possible pulses for all edge types. Combined with SPICLK to get
// edges for different phase and polarity modes.
assign ShiftEdgePulse = EdgePulse & ~LastBit;
assign SampleEdgePulse = EdgePulse & ~DelayIsNext;
assign SampleEdgePulse = EdgePulse & (NextState == TRANSMIT);
assign EndOfFramePulse = EdgePulse & LastBit;
// Delay ShiftEdge and SampleEdge by a half PCLK period
// Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
// Sweeeeeeeeeet...
assign InvertClock = ^SckMode;
always_ff @(posedge ~PCLK) begin
if (~PRESETn | TransmitStart) begin
ShiftEdge <= 0;
SampleEdge <= 0;
EndOfFrame <= 0;
end else if (^SckMode) begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse;
SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse;
end else begin
ShiftEdge <= SPICLK & ShiftEdgePulse;
SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse;
end
end else begin
ShiftEdge <= (InvertClock ^ SPICLK) & ShiftEdgePulse;
SampleEdge <= (InvertClock ^ ~SPICLK) & SampleEdgePulse;
EndOfFrame <= (InvertClock ^ SPICLK) & EndOfFramePulse;
end
end
// Logic for continuing to transmit through Delay states after end of frame
assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
assign CurrentEndDelay = CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR;
always_ff @(posedge PCLK) begin
if (~PRESETn) begin
CurrState <= INACTIVE;
@ -305,7 +297,6 @@ module spi_controller (
end
assign Transmitting = CurrState == TRANSMIT;
assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
assign DelayState = (CurrState == CSSCK | CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR);
assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS;

42
testbench/common/wallyTracer.sv
View File

@ -44,6 +44,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
logic InstrValidM, InstrValidW;
logic StallE, StallM, StallW;
logic GatedStallW;
logic FlushD, FlushE, FlushM, FlushW;
logic TrapM, TrapW;
logic HaltM, HaltW;
@ -69,6 +70,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW;
logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW;
logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW;
logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW;
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
@ -89,6 +91,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign StallE = testbench.dut.core.StallE;
assign StallM = testbench.dut.core.StallM;
assign StallW = testbench.dut.core.StallW;
assign GatedStallW = testbench.dut.core.lsu.GatedStallW;
assign FlushD = testbench.dut.core.FlushD;
assign FlushE = testbench.dut.core.FlushE;
assign FlushM = testbench.dut.core.FlushM;
@ -121,6 +124,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign PageType_iM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
logic valid;
@ -355,21 +360,28 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
//for VM Verification
flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW);
flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
// *** what is this used for?
flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD);
flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);
flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM);
flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW);
flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); //Virtual Address for IMMU
flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); //Virtual Address for DMMU
flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); //Physical Address for IMMU
flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); //Physical Address for DMMU
flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); //PTE for IMMU
flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); //PTE for DMMU
flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); //Page Type (kilo, mega, giga, tera) from IMMU
flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); //Page Type (kilo, mega, giga, tera) from DMMU
flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU
flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess
flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess
flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access
flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access
flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access
flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access
// Initially connecting the writeback stage signals, but may need to use M stage
// and gate on ~FlushW.

9
testbench/testbench.sv
View File

@ -44,6 +44,7 @@ module testbench;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
parameter RVVI_SYNTH_SUPPORTED=0;
parameter MAKE_VCD=0;
`ifdef USE_TREK_DV
event trek_start;
@ -237,10 +238,10 @@ module testbench;
end
$finish;
end
`ifdef MAKEVCD
$dumpfile("testbench.vcd");
$dumpvars;
`endif
if (MAKE_VCD) begin
$dumpfile("testbench.vcd");
$dumpvars;
end
end // initial begin
// Model the testbench as an fsm.