From 2ee4525ba9859fbc1dcd726b0680c7ac4e3cce2b Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Sat, 16 Nov 2024 11:34:31 -0600
Subject: [PATCH 01/28] Made minor changes to the controller to clean up the
 logic. Still need to simplify the first always block.

---
 src/uncore/spi_controller.sv | 41 ++++++++++++++----------------------
 1 file changed, 16 insertions(+), 25 deletions(-)

diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv
index dee3d3c99..0ed8e57be 100644
--- a/src/uncore/spi_controller.sv
+++ b/src/uncore/spi_controller.sv
@@ -75,6 +75,7 @@ module spi_controller (
   logic ShiftEdgePulse;
   logic SampleEdgePulse;
   logic EndOfFramePulse;
+  logic InvertClock;
 
   // Frame stuff
   logic [3:0] BitNum;
@@ -107,8 +108,8 @@ module spi_controller (
   
   logic [7:0] DelayCounter;
 
-  logic       DelayIsNext;
-  logic       DelayState;       
+  logic       DelayState;
+  
   // Convenient Delay Reg Names
   assign cssck = Delay0[7:0];
   assign sckcs = Delay0[15:8];
@@ -130,10 +131,6 @@ module spi_controller (
   assign EndOfDelay = EndOfCSSCK | EndOfSCKCS | EndOfINTERCS | EndOfINTERXFR;
   
   // Clock Signal Stuff -----------------------------------------------
-  // I'm going to handle all clock stuff here, including ShiftEdge and
-  // SampleEdge. This makes sure that SPICLK is an output of a register
-  // and it properly synchronizes signals.
-
   // SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
   // Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
   // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
@@ -166,12 +163,14 @@ module spi_controller (
       end
       
       // SPICLK Logic
-      
+      // We only want to trigger the clock during Transmission.
+      // If Phase == 1, then we want to trigger as soon as NextState == TRANSMIT
+      // Otherwise, only trigger the clock when the CurrState is TRANSMIT.
+      // We never want to trigger the clock if the NextState is NOT TRANSMIT
       if (TransmitStart & ~DelayState) begin
         SPICLK <= SckMode[1];
-      end else if (SCLKenable) begin
-        if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
-        else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
+        end else if (SCLKenable) begin
+        SPICLK <= (NextState == TRANSMIT) & (~Phase & Transmitting | Phase) ? ~SPICLK : SckMode[1];
       end
       
       // Reset divider 
@@ -201,32 +200,25 @@ module spi_controller (
   // Possible pulses for all edge types. Combined with SPICLK to get
   // edges for different phase and polarity modes.
   assign ShiftEdgePulse = EdgePulse & ~LastBit;
-  assign SampleEdgePulse = EdgePulse & ~DelayIsNext;
+  assign SampleEdgePulse = EdgePulse & (NextState == TRANSMIT);
   assign EndOfFramePulse = EdgePulse & LastBit;
 
   // Delay ShiftEdge and SampleEdge by a half PCLK period
   // Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
   // Sweeeeeeeeeet...
+  assign InvertClock = ^SckMode;
   always_ff @(posedge ~PCLK) begin
     if (~PRESETn | TransmitStart) begin
       ShiftEdge <= 0;
       SampleEdge <= 0;
       EndOfFrame <= 0;
-      end else if (^SckMode) begin
-          ShiftEdge <= ~SPICLK & ShiftEdgePulse;
-          SampleEdge <= SPICLK & SampleEdgePulse;
-          EndOfFrame <= ~SPICLK & EndOfFramePulse;
-      end else begin 
-          ShiftEdge <= SPICLK & ShiftEdgePulse;
-          SampleEdge <= ~SPICLK & SampleEdgePulse;
-          EndOfFrame <= SPICLK & EndOfFramePulse;
-      end 
+    end else begin 
+      ShiftEdge <= (InvertClock ^ SPICLK) & ShiftEdgePulse;
+      SampleEdge <= (InvertClock ^ ~SPICLK) & SampleEdgePulse;
+      EndOfFrame <= (InvertClock ^ SPICLK) & EndOfFramePulse;
     end 
+  end 
 
-  // Logic for continuing to transmit through Delay states after end of frame
-  assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
-  assign CurrentEndDelay = CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR;
-  
   always_ff @(posedge PCLK) begin
     if (~PRESETn) begin
       CurrState <= INACTIVE;
@@ -305,7 +297,6 @@ module spi_controller (
   end
 
   assign Transmitting = CurrState == TRANSMIT;
-  assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
   assign DelayState = (CurrState == CSSCK | CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR);
   assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS;
   

From dda3cd6beaf474d1c8ab4594d06f207615d35344 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Sat, 16 Nov 2024 14:29:58 -0600
Subject: [PATCH 02/28] Removed unnecessary separate if statement.

---
 src/uncore/spi_apb.sv | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index 9b15839e7..04c3d3c97 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -174,16 +174,12 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
           SPI_CSMODE:  ChipSelectMode <= Din[1:0];
           SPI_DELAY0:  Delay0 <= {Din[23:16], Din[7:0]};
           SPI_DELAY1:  Delay1 <= {Din[23:16], Din[7:0]};
-          SPI_FMT:     Format <= {Din[19:16], Din[2]};                    
+          SPI_FMT:     Format <= {Din[19:16], Din[2]};
+          SPI_TXDATA:  if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
           SPI_TXMARK:  TransmitWatermark <= Din[2:0];
           SPI_RXMARK:  ReceiveWatermark <= Din[2:0];
           SPI_IE:      InterruptEnable <= Din[1:0];
         endcase
-
-      if (Memwrite)
-        case(Entry)
-          SPI_TXDATA:  if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
-        endcase
       /* verilator lint_off CASEINCOMPLETE */
       
       // According to FU540 spec: Once interrupt is pending, it will remain set until number 

From 78e11ed9f3cbe1f2fe0121ad3462bfc3a7da0dee Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Mon, 2 Dec 2024 15:24:46 -0600
Subject: [PATCH 03/28] Remove old unused file.

---
 fpga/src/axi_sdc_controller.v | 669 ----------------------------------
 1 file changed, 669 deletions(-)
 delete mode 100644 fpga/src/axi_sdc_controller.v

diff --git a/fpga/src/axi_sdc_controller.v b/fpga/src/axi_sdc_controller.v
deleted file mode 100644
index c32a6a783..000000000
--- a/fpga/src/axi_sdc_controller.v
+++ /dev/null
@@ -1,669 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2013-2022 Authors                              ////
-////                                                              ////
-//// Based on original work by                                    ////
-////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
-////                                                              ////
-////     Copyright (C) 2009 Authors                               ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE. See the GNU Lesser General Public License for more  ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from https://www.gnu.org/licenses/                           ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-module sdc_controller #(
-    parameter dma_addr_bits = 32,
-    parameter fifo_addr_bits = 7,
-    parameter sdio_card_detect_level = 1,
-    parameter voltage_controll_reg = 3300,
-    parameter capabilies_reg = 16'b0000_0000_0000_0011
-) (
-    input wire                     async_resetn,
-
-    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
-    (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *)
-    input wire                     clock,
-
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
-    (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *)
-    input wire [15:0]              s_axi_awaddr,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
-    input wire                     s_axi_awvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
-    output wire                    s_axi_awready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
-    input wire [31:0]              s_axi_wdata,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
-    input wire                     s_axi_wvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
-    output wire                    s_axi_wready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
-    output reg [1:0]               s_axi_bresp,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
-    output reg                     s_axi_bvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
-    input wire                     s_axi_bready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
-    input wire [15:0]              s_axi_araddr,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
-    input wire                     s_axi_arvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
-    output wire                    s_axi_arready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
-    output reg [31:0]              s_axi_rdata,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
-    output reg [1:0]               s_axi_rresp,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
-    output reg                     s_axi_rvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
-    input wire                     s_axi_rready,
-
-    (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *)
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-    output reg [dma_addr_bits-1:0] m_axi_awaddr,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
-    output reg [7:0]               m_axi_awlen,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-    output reg                     m_axi_awvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-    input wire                     m_axi_awready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-    output wire [31:0]             m_axi_wdata,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
-    output reg                     m_axi_wlast,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-    output reg                     m_axi_wvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-    input wire                     m_axi_wready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-    input wire [1:0]               m_axi_bresp,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-    input wire                     m_axi_bvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-    output wire                    m_axi_bready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
-    output reg [dma_addr_bits-1:0] m_axi_araddr,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
-    output reg [7:0]               m_axi_arlen,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
-    output reg                     m_axi_arvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
-    input wire                     m_axi_arready,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
-    input wire [31:0]              m_axi_rdata,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
-    input wire                     m_axi_rlast,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
-    input wire [1:0]               m_axi_rresp,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
-    input wire                     m_axi_rvalid,
-    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
-    output wire                    m_axi_rready,
-
-    // SD BUS
-    //inout wire                     sdio_cmd,
-    //inout wire [3:0]               sdio_dat,
-    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *)
-    (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *)
-    output reg                     sdio_clk,
-    (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *)
-    (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
-    output reg                     sdio_reset,
-    input wire                     sdio_cd,
-
-    output reg                     sd_dat_reg_t,
-    output reg [3:0]               sd_dat_reg_o,
-    input wire [3:0]               sd_dat_i,
-
-    output reg                     sd_cmd_reg_t,
-    output reg                     sd_cmd_reg_o,
-    input wire                     sd_cmd_i,
-
-    // Interrupts
-    output wire                    interrupt
-);
-
-`include "sd_defines.h"
-
-wire reset;
-
-wire go_idle;
-reg  cmd_start;
-wire [1:0] cmd_setting;
-wire cmd_start_tx;
-wire [39:0] cmd;
-wire [119:0] cmd_response;
-wire cmd_crc_ok;
-wire cmd_index_ok;
-wire cmd_finish;
-
-wire d_write;
-wire d_read;
-wire [31:0] data_in_rx_fifo;
-wire en_tx_fifo;
-wire en_rx_fifo;
-wire sd_data_busy;
-(* mark_debug = "true" *) wire data_busy;
-wire data_crc_ok;
-wire tx_fifo_re;
-wire rx_fifo_we;
-
-reg data_start_rx;
-reg data_start_tx;
-reg data_prepare_tx;
-reg  cmd_int_rst;
-reg  data_int_rst;
-reg  ctrl_rst;
-
-// AXI accessible registers
-(* mark_debug = "true" *) reg  [31:0] argument_reg;
-(* mark_debug = "true" *) reg  [`CMD_REG_SIZE-1:0] command_reg;
-(* mark_debug = "true" *) reg  [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
-(* mark_debug = "true" *) reg  [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
-(* mark_debug = "true" *) reg  [0:0] software_reset_reg;
-(* mark_debug = "true" *) wire [31:0] response_0_reg;
-(* mark_debug = "true" *) wire [31:0] response_1_reg;
-(* mark_debug = "true" *) wire [31:0] response_2_reg;
-(* mark_debug = "true" *) wire [31:0] response_3_reg;
-(* mark_debug = "true" *) reg  [`BLKSIZE_W-1:0] block_size_reg;
-(* mark_debug = "true" *) reg  [1:0] controller_setting_reg;
-(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
-(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
-(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status;
-(* mark_debug = "true" *) reg  [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
-(* mark_debug = "true" *) reg  [`INT_DATA_SIZE-1:0] data_int_enable_reg;
-(* mark_debug = "true" *) reg  [`BLKCNT_W-1:0] block_count_reg;
-(* mark_debug = "true" *) reg  [dma_addr_bits-1:0] dma_addr_reg;
-(* mark_debug = "true" *) reg  [7:0] clock_divider_reg = 124; // 400KHz
-
-// ------ Clocks and resets
-
-(* ASYNC_REG="true" *)
-reg  [2:0] reset_sync;
-assign reset = reset_sync[2];
-
-always @(posedge clock)
-    reset_sync <= {reset_sync[1:0], !async_resetn};
-
-reg [7:0] clock_cnt;
-(* mark_debug = "true" *)   reg clock_state;
-(* mark_debug = "true" *) reg clock_posedge;
-reg clock_data_in;
-wire fifo_almost_full;
-wire fifo_almost_empty;
-
-always @(posedge clock) begin
-    if (reset) begin
-        clock_posedge <= 0;
-        clock_data_in <= 0;
-        clock_state <= 0;
-        clock_cnt <= 0;
-    end else if (clock_cnt < clock_divider_reg) begin
-        clock_posedge <= 0;
-        clock_data_in <= 0;
-        clock_cnt <= clock_cnt + 1;
-    end else if (clock_cnt < 124 && data_busy && en_rx_fifo && fifo_almost_full) begin
-        // Prevent Rx FIFO overflow
-        clock_posedge <= 0;
-        clock_data_in <= 0;
-        clock_cnt <= clock_cnt + 1;
-    end else if (clock_cnt < 124 && data_busy && en_tx_fifo && fifo_almost_empty) begin
-        // Prevent Tx FIFO underflow
-        clock_posedge <= 0;
-        clock_data_in <= 0;
-        clock_cnt <= clock_cnt + 1;
-    end else begin
-        clock_state <= !clock_state;
-        clock_posedge <= !clock_state;
-        if (clock_divider_reg == 0)
-            clock_data_in <= !clock_state;
-        else
-            clock_data_in <= clock_state;
-        clock_cnt <= 0;
-    end
-    sdio_clk <= sdio_reset || clock_state;
-
-    if (reset) sdio_reset <= 0;
-    else if (clock_posedge) sdio_reset <= controller_setting_reg[1];
-end
-
-// ------ SD IO Buffers
-
-// wire sd_cmd_i;
-wire sd_cmd_o;
-wire sd_cmd_oe;
-// reg  sd_cmd_reg_o;
-// reg  sd_cmd_reg_t;
-// wire [3:0] sd_dat_i;
-wire [3:0] sd_dat_o;
-wire sd_dat_oe;
-// reg  [3:0] sd_dat_reg_o;
-// reg  sd_dat_reg_t;
-
-// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
-// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
-// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
-// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
-// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
-
-always @(negedge sdio_clk) begin
-    // Output data delayed by 1/2 clock cycle (5ns) to ensure
-    // required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
-    if (sdio_reset) begin
-        sd_cmd_reg_o <= 0;
-        sd_dat_reg_o <= 0;
-        sd_cmd_reg_t <= 0;
-        sd_dat_reg_t <= 0;
-    end else begin
-        sd_cmd_reg_o <= sd_cmd_o;
-        sd_dat_reg_o <= sd_dat_o;
-        sd_cmd_reg_t <= !sd_cmd_oe;
-        sd_dat_reg_t <= !(sd_dat_oe || (cmd_start_tx && (command_reg == 0)));
-    end
-end
-
-// ------ SD card detect
-
-reg [25:0] sd_detect_cnt;
-wire sd_insert_int = sd_detect_cnt[25];
-wire sd_remove_int = !sd_detect_cnt[25];
-reg sd_insert_ie;
-reg sd_remove_ie;
-
-always @(posedge clock) begin
-    if (sdio_cd != sdio_card_detect_level) begin
-        sd_detect_cnt <= 0;
-    end else if (!sd_insert_int) begin
-        sd_detect_cnt <= sd_detect_cnt + 1;
-    end
-end
-
-// ------ AXI Slave Interface
-
-reg [15:0] read_addr;
-reg [15:0] write_addr;
-reg [31:0] write_data;
-reg rd_req;
-reg [1:0] wr_req;
-
-assign s_axi_arready = !rd_req && !s_axi_rvalid;
-assign s_axi_awready = !wr_req[0] && !s_axi_bvalid;
-assign s_axi_wready = !wr_req[1] && !s_axi_bvalid;
-
-always @(posedge clock) begin
-    if (reset) begin
-        s_axi_rdata <= 0;
-        s_axi_rresp <= 0;
-        s_axi_rvalid <= 0;
-        s_axi_bresp <= 0;
-        s_axi_bvalid <= 0;
-        rd_req <= 0;
-        wr_req <= 0;
-        read_addr <= 0;
-        write_addr <= 0;
-        write_data <= 0;
-        cmd_start <= 0;
-        data_int_rst <= 0;
-        cmd_int_rst <= 0;
-        ctrl_rst <= 0;
-        argument_reg <= 0;
-        command_reg <= 0;
-        cmd_timeout_reg <= 0;
-        data_timeout_reg <= 0;
-        block_size_reg <= `RESET_BLOCK_SIZE;
-        controller_setting_reg <= 0;
-        cmd_int_enable_reg <= 0;
-        data_int_enable_reg <= 0;
-        software_reset_reg <= 0;
-        clock_divider_reg <= `RESET_CLOCK_DIV;
-        block_count_reg <= 0;
-        sd_insert_ie <= 0;
-        sd_remove_ie <= 0;
-        dma_addr_reg <= 0;
-    end else begin
-        if (clock_posedge) begin
-            cmd_start <= 0;
-            data_int_rst <= 0;
-            cmd_int_rst <= 0;
-            ctrl_rst <= software_reset_reg[0];
-        end
-        if (s_axi_arready && s_axi_arvalid) begin
-            read_addr <= s_axi_araddr;
-            rd_req <= 1;
-        end
-        if (s_axi_rvalid && s_axi_rready) begin
-            s_axi_rvalid <= 0;
-        end else if (!s_axi_rvalid && rd_req) begin
-            s_axi_rdata <= 0;
-            if (read_addr[15:8] == 0) begin
-                case (read_addr[7:0])
-                    `argument     : s_axi_rdata <= argument_reg;
-                    `command      : s_axi_rdata <= command_reg;
-                    `resp0        : s_axi_rdata <= response_0_reg;
-                    `resp1        : s_axi_rdata <= response_1_reg;
-                    `resp2        : s_axi_rdata <= response_2_reg;
-                    `resp3        : s_axi_rdata <= response_3_reg;
-                    `controller   : s_axi_rdata <= controller_setting_reg;
-                    `blksize      : s_axi_rdata <= block_size_reg;
-                    `voltage      : s_axi_rdata <= voltage_controll_reg;
-                    `capa         : s_axi_rdata <= capabilies_reg | (dma_addr_bits << 8);
-                    `clock_d      : s_axi_rdata <= clock_divider_reg;
-                    `reset        : s_axi_rdata <= { cmd_start, data_int_rst, cmd_int_rst, ctrl_rst };
-                    `cmd_timeout  : s_axi_rdata <= cmd_timeout_reg;
-                    `data_timeout : s_axi_rdata <= data_timeout_reg;
-                    `cmd_isr      : s_axi_rdata <= cmd_int_status_reg;
-                    `cmd_iser     : s_axi_rdata <= cmd_int_enable_reg;
-                    `data_isr     : s_axi_rdata <= data_int_status_reg;
-                    `data_iser    : s_axi_rdata <= data_int_enable_reg;
-                    `blkcnt       : s_axi_rdata <= block_count_reg;
-                    `card_detect  : s_axi_rdata <= { sd_remove_int, sd_remove_ie, sd_insert_int, sd_insert_ie };
-                    `dst_src_addr : s_axi_rdata <= dma_addr_reg[31:0];
-                    `dst_src_addr_high : if (dma_addr_bits > 32) s_axi_rdata <= dma_addr_reg[dma_addr_bits-1:32];
-                endcase
-            end
-            s_axi_rresp <= 0;
-            s_axi_rvalid <= 1;
-            rd_req <= 0;
-        end
-        if (s_axi_awready && s_axi_awvalid) begin
-            write_addr <= s_axi_awaddr;
-            wr_req[0] <= 1;
-        end
-        if (s_axi_wready && s_axi_wvalid) begin
-            write_data <= s_axi_wdata;
-            wr_req[1] <= 1;
-        end
-        if (s_axi_bvalid && s_axi_bready) begin
-            s_axi_bvalid <= 0;
-        end else if (!s_axi_bvalid && wr_req == 2'b11) begin
-            if (write_addr[15:8] == 0) begin
-                case (write_addr[7:0])
-                    `argument     : begin argument_reg <= write_data; cmd_start <= 1; end
-                    `command      : command_reg <= write_data;
-                    `reset        : software_reset_reg <= write_data;
-                    `cmd_timeout  : cmd_timeout_reg <= write_data;
-                    `data_timeout : data_timeout_reg <= write_data;
-                    `blksize      : block_size_reg <= write_data;
-                    `controller   : controller_setting_reg <= write_data;
-                    `cmd_isr      : cmd_int_rst <= 1;
-                    `cmd_iser     : cmd_int_enable_reg <= write_data;
-                    `clock_d      : clock_divider_reg <= write_data;
-                    `data_isr     : data_int_rst <= 1;
-                    `data_iser    : data_int_enable_reg <= write_data;
-                    `blkcnt       : block_count_reg <= write_data;
-                    `card_detect  : begin sd_remove_ie <= write_data[2]; sd_insert_ie <= write_data[0]; end
-                    `dst_src_addr : dma_addr_reg[31:0] <= write_data;
-                    `dst_src_addr_high : if (dma_addr_bits > 32) dma_addr_reg[dma_addr_bits-1:32] <= write_data;
-                endcase
-            end
-            s_axi_bresp <= 0;
-            s_axi_bvalid <= 1;
-            wr_req <= 0;
-        end
-    end
-end
-
-// ------ Data FIFO
-
-reg  [31:0] fifo_mem [(1<<fifo_addr_bits)-1:0];
-reg  [fifo_addr_bits-1:0] fifo_inp_pos;
-reg  [fifo_addr_bits-1:0] fifo_out_pos;
-wire [fifo_addr_bits-1:0] fifo_inp_nxt = fifo_inp_pos + 1;
-wire [fifo_addr_bits-1:0] fifo_out_nxt = fifo_out_pos + 1;
-wire [fifo_addr_bits-1:0] fifo_data_len = fifo_inp_pos - fifo_out_pos;
-wire [fifo_addr_bits-1:0] fifo_free_len = fifo_out_pos - fifo_inp_nxt;
-wire fifo_full = fifo_inp_nxt == fifo_out_pos;
-wire fifo_empty = fifo_inp_pos == fifo_out_pos;
-wire fifo_ready = fifo_data_len >= (1 << fifo_addr_bits) / 2;
-wire [31:0] fifo_din = en_rx_fifo ? data_in_rx_fifo : m_bus_dat_i;
-wire fifo_we = en_rx_fifo ? rx_fifo_we && clock_posedge : m_axi_rready && m_axi_rvalid;
-wire fifo_re = en_rx_fifo ? m_axi_wready && m_axi_wvalid : tx_fifo_re && clock_posedge;
-reg [31:0] fifo_dout;
-
-assign fifo_almost_full = fifo_data_len > (1 << fifo_addr_bits) * 3 / 4;
-assign fifo_almost_empty = fifo_free_len > (1 << fifo_addr_bits) * 3 / 4;
-
-wire tx_stb = en_tx_fifo && fifo_free_len >= (1 << fifo_addr_bits) / 3;
-wire rx_stb = en_rx_fifo && m_axi_bresp_cnt != 3'b111 && (fifo_data_len >= (1 << fifo_addr_bits) / 3 || (!fifo_empty && !data_busy));
-
-always @(posedge clock)
-    if (reset || ctrl_rst || !(en_rx_fifo || en_tx_fifo)) begin
-        fifo_inp_pos <= 0;
-        fifo_out_pos <= 0;
-    end else begin
-        if (fifo_we && !fifo_full) begin
-            fifo_mem[fifo_inp_pos] <= fifo_din;
-            fifo_inp_pos <= fifo_inp_nxt;
-            if (fifo_empty) fifo_dout <= fifo_din;
-        end
-        if (fifo_re && !fifo_empty) begin
-            if (fifo_we && !fifo_full && fifo_out_nxt == fifo_inp_pos) fifo_dout <= fifo_din;
-            else fifo_dout <= fifo_mem[fifo_out_nxt];
-            fifo_out_pos <= fifo_out_nxt;
-        end
-    end
-
-// ------ AXI Master Interface
-
-// AXI transaction (DDR access) is over 80 clock cycles
-// Must use burst to achive required throughput
-
-reg m_axi_cyc;
-wire m_axi_write = en_rx_fifo;
-reg [7:0] m_axi_wcnt;
-reg [dma_addr_bits-1:2] m_bus_adr_o;
-wire [31:0] m_bus_dat_i;
-reg [2:0] m_axi_bresp_cnt;
-reg m_bus_error;
-
-assign m_axi_bready = m_axi_bresp_cnt != 0;
-assign m_axi_rready = m_axi_cyc & !m_axi_write;
-assign m_bus_dat_i = {m_axi_rdata[7:0],m_axi_rdata[15:8],m_axi_rdata[23:16],m_axi_rdata[31:24]};
-assign m_axi_wdata = {fifo_dout[7:0],fifo_dout[15:8],fifo_dout[23:16],fifo_dout[31:24]};
-
-// AXI burst cannot cross a 4KB boundary
-wire [fifo_addr_bits-1:0] tx_burst_len;
-wire [fifo_addr_bits-1:0] rx_burst_len;
-assign tx_burst_len = m_bus_adr_o[11:2] + fifo_free_len >= m_bus_adr_o[11:2] ? fifo_free_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
-assign rx_burst_len = m_bus_adr_o[11:2] + fifo_data_len >= m_bus_adr_o[11:2] ? fifo_data_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
-
-assign data_int_status_reg = { data_int_status[`INT_DATA_SIZE-1:1],
-    !en_rx_fifo && !en_tx_fifo && !m_axi_cyc && m_axi_bresp_cnt == 0 && data_int_status[0] };
-
-always @(posedge clock) begin
-    if (reset | ctrl_rst) begin
-        m_axi_arvalid <= 0;
-        m_axi_awvalid <= 0;
-        m_axi_wvalid <= 0;
-        m_axi_cyc <= 0;
-    end else if (m_axi_cyc) begin
-        if (m_axi_awvalid && m_axi_awready) begin
-            m_axi_awvalid <= 0;
-        end
-        if (m_axi_arvalid && m_axi_arready) begin
-            m_axi_arvalid <= 0;
-        end
-        if (m_axi_wvalid && m_axi_wready) begin
-            if (m_axi_wlast) begin
-                m_axi_wvalid <= 0;
-                m_axi_cyc <= 0;
-            end else begin
-                m_axi_wlast <= m_axi_wcnt + 1 == m_axi_awlen;
-                m_axi_wcnt <= m_axi_wcnt + 1;
-            end
-        end
-        if (m_axi_rvalid && m_axi_rready && m_axi_rlast) begin
-            m_axi_cyc <= 0;
-        end
-    end else if (tx_stb || rx_stb) begin
-        m_axi_cyc <= 1;
-        m_axi_wcnt <= 0;
-        if (m_axi_write) begin
-            m_axi_awaddr <= { m_bus_adr_o, 2'b00 };
-            m_axi_awlen <= rx_burst_len < 8'hff ? rx_burst_len : 8'hff;
-            m_axi_wlast <= rx_burst_len == 0;
-            m_axi_awvalid <= 1;
-            m_axi_wvalid <= 1;
-        end else begin
-            m_axi_araddr <= { m_bus_adr_o, 2'b00 };
-            m_axi_arlen <= tx_burst_len < 8'hff ? tx_burst_len : 8'hff;
-            m_axi_arvalid <= 1;
-        end
-    end
-    if (reset | ctrl_rst) begin
-        m_bus_adr_o <= 0;
-    end else if ((m_axi_wready && m_axi_wvalid) || (m_axi_rready && m_axi_rvalid)) begin
-        m_bus_adr_o <= m_bus_adr_o + 1;
-    end else if (!m_axi_cyc && !en_rx_fifo && !en_tx_fifo) begin
-        m_bus_adr_o <= dma_addr_reg[dma_addr_bits-1:2];
-    end
-    if (reset | ctrl_rst) begin
-        m_axi_bresp_cnt <= 0;
-    end else if ((m_axi_awvalid && m_axi_awready) && !(m_axi_bvalid && m_axi_bready)) begin
-        m_axi_bresp_cnt <= m_axi_bresp_cnt + 1;
-    end else if (!(m_axi_awvalid && m_axi_awready) && (m_axi_bvalid && m_axi_bready)) begin
-        m_axi_bresp_cnt <= m_axi_bresp_cnt - 1;
-    end
-    if (reset | ctrl_rst | cmd_start) begin
-        m_bus_error <= 0;
-    end else if (m_axi_bvalid && m_axi_bready && m_axi_bresp) begin
-        m_bus_error <= 1;
-    end else if (m_axi_rvalid && m_axi_rready && m_axi_rresp) begin
-        m_bus_error <= 1;
-    end
-    if (reset | ctrl_rst) begin
-        data_start_tx <= 0;
-        data_start_rx <= 0;
-        data_prepare_tx <= 0;
-    end else if (clock_posedge) begin
-        data_start_tx <= 0;
-        data_start_rx <= 0;
-        if (cmd_start) begin
-            data_prepare_tx <= 0;
-            if (command_reg[`CMD_WITH_DATA] == 2'b01) data_start_rx <= 1;
-            else if (command_reg[`CMD_WITH_DATA] != 2'b00) data_prepare_tx <= 1;
-        end else if (data_prepare_tx) begin
-            if (cmd_int_status_reg[`INT_CMD_CC]) begin
-                data_prepare_tx <= 0;
-                data_start_tx <= 1;
-            end else if (cmd_int_status_reg[`INT_CMD_EI]) begin
-                data_prepare_tx <= 0;
-            end
-        end
-    end
-end
-
-// ------ SD Card Interface
-
-sd_cmd_master sd_cmd_master0(
-    .clock            (clock),
-    .clock_posedge    (clock_posedge),
-    .reset            (reset | ctrl_rst),
-    .start            (cmd_start),
-    .int_status_rst   (cmd_int_rst),
-    .setting          (cmd_setting),
-    .start_xfr        (cmd_start_tx),
-    .go_idle          (go_idle),
-    .cmd              (cmd),
-    .response         (cmd_response),
-    .crc_error        (!cmd_crc_ok),
-    .index_ok         (cmd_index_ok),
-    .busy             (sd_data_busy),
-    .finish           (cmd_finish),
-    .argument         (argument_reg),
-    .command          (command_reg),
-    .timeout          (cmd_timeout_reg),
-    .int_status       (cmd_int_status_reg),
-    .response_0       (response_0_reg),
-    .response_1       (response_1_reg),
-    .response_2       (response_2_reg),
-    .response_3       (response_3_reg)
-    );
-
-sd_cmd_serial_host cmd_serial_host0(
-    .clock            (clock),
-    .clock_posedge    (clock_posedge),
-    .clock_data_in    (clock_data_in),
-    .reset            (reset | ctrl_rst | go_idle),
-    .setting          (cmd_setting),
-    .cmd              (cmd),
-    .start            (cmd_start_tx),
-    .finish           (cmd_finish),
-    .response         (cmd_response),
-    .crc_ok           (cmd_crc_ok),
-    .index_ok         (cmd_index_ok),
-    .cmd_i            (sd_cmd_i),
-    .cmd_o            (sd_cmd_o),
-    .cmd_oe           (sd_cmd_oe)
-    );
-
-sd_data_master sd_data_master0(
-    .clock            (clock),
-    .clock_posedge    (clock_posedge),
-    .reset            (reset | ctrl_rst),
-    .start_tx         (data_start_tx),
-    .start_rx         (data_start_rx),
-    .timeout          (data_timeout_reg),
-    .d_write          (d_write),
-    .d_read           (d_read),
-    .en_tx_fifo       (en_tx_fifo),
-    .en_rx_fifo       (en_rx_fifo),
-    .fifo_empty       (fifo_empty),
-    .fifo_ready       (fifo_ready),
-    .fifo_full        (fifo_full),
-    .bus_cycle        (m_axi_cyc || m_axi_bresp_cnt != 0),
-    .xfr_complete     (!data_busy),
-    .crc_error        (!data_crc_ok),
-    .bus_error        (m_bus_error),
-    .int_status       (data_int_status),
-    .int_status_rst   (data_int_rst)
-    );
-
-sd_data_serial_host sd_data_serial_host0(
-    .clock            (clock),
-    .clock_posedge    (clock_posedge),
-    .clock_data_in    (clock_data_in),
-    .reset            (reset | ctrl_rst),
-    .data_in          (fifo_dout),
-    .rd               (tx_fifo_re),
-    .data_out         (data_in_rx_fifo),
-    .we               (rx_fifo_we),
-    .dat_oe           (sd_dat_oe),
-    .dat_o            (sd_dat_o),
-    .dat_i            (sd_dat_i),
-    .blksize          (block_size_reg),
-    .bus_4bit         (controller_setting_reg[0]),
-    .blkcnt           (block_count_reg),
-    .start            ({d_read, d_write}),
-    .byte_alignment   (dma_addr_reg[1:0]),
-    .sd_data_busy     (sd_data_busy),
-    .busy             (data_busy),
-    .crc_ok           (data_crc_ok)
-    );
-
-assign interrupt =
-    |(cmd_int_status_reg & cmd_int_enable_reg) ||
-    |(data_int_status_reg & data_int_enable_reg) ||
-    (sd_insert_int & sd_insert_ie) ||
-    (sd_remove_int & sd_remove_ie);
-
-endmodule

From d5159d35a2bd69eb85ca5f0cf9caadc49f491867 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Mon, 2 Dec 2024 13:32:23 -0800
Subject: [PATCH 04/28] Remove locksteplog

---
 bin/wsim | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 91f8e30ab..740193e0f 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -31,7 +31,6 @@ def parseArgs():
     parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
     parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
     parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
-    parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
     parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
     parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
     parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
@@ -99,8 +98,6 @@ def lockstepSetup(args):
     suffix = ""
     ImperasPlusArgs = ""
 
-    if(int(args.locksteplog) >= 1): EnableLog = 1
-    else: EnableLog = 0
     if (args.lockstep or args.lockstepverbose or args.fcov):
         imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
         if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
@@ -111,7 +108,6 @@ def lockstepSetup(args):
         prefix += f"IMPERAS_TOOLS={imperasicPath}"
 
     if (args.lockstep or args.lockstepverbose):
-        if(args.locksteplog != 0): ImperasPlusArgs = f" +IDV_TRACE2LOG={EnableLog} +IDV_TRACE2LOG_AFTER={args.locksteplog}"
         if(args.fcov):
             CovEnableStr = "1" if int(args.covlog) > 0  else "0"
             if(args.covlog >= 1): EnableLog = 1

From 783b81f8b8fcca56483167d1b86bedaa871dd1ad Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Mon, 2 Dec 2024 13:52:44 -0800
Subject: [PATCH 05/28] VCD support in all simulators

---
 bin/wsim               | 2 +-
 testbench/testbench.sv | 9 +++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 740193e0f..9defcc1c9 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -78,7 +78,7 @@ def elfFileCheck(args):
 def prepSim(args, ElfFile):
     flags = ""
     if args.vcd:
-        args.args += " -DMAKEVCD=1"
+        args.params += " MAKE_VCD=1 "
     if args.rvvi:
         args.params += " RVVI_SYNTH_SUPPORTED=1 "
     if args.tb == "testbench_fp":
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index c777fdf3f..40f5410ef 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -44,6 +44,7 @@ module testbench;
   parameter I_CACHE_ADDR_LOGGER=0;
   parameter D_CACHE_ADDR_LOGGER=0;
   parameter RVVI_SYNTH_SUPPORTED=0;
+  parameter MAKE_VCD=0;
 
   `ifdef USE_IMPERAS_DV
     import idvPkg::*;
@@ -230,10 +231,10 @@ module testbench;
       end
       $finish;
     end
-`ifdef MAKEVCD
-    $dumpfile("testbench.vcd");
-    $dumpvars;
-`endif
+    if (MAKE_VCD) begin
+      $dumpfile("testbench.vcd");
+      $dumpvars;
+    end
   end // initial begin
 
   // Model the testbench as an fsm.

From edf96a7211763ebdd5f413d417121eacd76b3e9d Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Mon, 2 Dec 2024 13:56:34 -0800
Subject: [PATCH 06/28] Move wsim debug flag to common flags section

---
 bin/wsim | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 9defcc1c9..8766957b1 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -85,6 +85,8 @@ def prepSim(args, ElfFile):
         args.params += f' TEST="{args.testsuite}" '
     if ElfFile != "":
         args.args += f" {ElfFile}"
+    if args.gui and args.tb == "testbench":
+        args.params += " DEBUG=1 "
     if args.ccov:
         flags += " --ccov"
     if args.fcov:
@@ -135,8 +137,6 @@ def runSim(args, flags, prefix):
 def runQuesta(args, flags, prefix):
     # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
     prefix = "MTI_VCO_MODE=64 " + prefix
-    if (args.gui) and (args.tb == "testbench"):
-        args.params += "DEBUG=1"
     if (args.args != ""):
         args.args = f' --args \\"{args.args}\\"'
     if (args.params != ""):

From 479c6667fe7a0d408ba4e27e874e19e9a9873650 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Mon, 2 Dec 2024 14:02:33 -0800
Subject: [PATCH 07/28] Generalize wsim gui flag and simplify questa launch
 command

---
 bin/wsim            | 9 +++------
 sim/questa/wally.do | 4 ++--
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 8766957b1..512ee5e42 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -91,6 +91,8 @@ def prepSim(args, ElfFile):
         flags += " --ccov"
     if args.fcov:
         flags += " --fcov"
+    if args.gui:
+        flags += " --gui"
     prefix, suffix = lockstepSetup(args)
     flags += suffix
     return flags, prefix
@@ -143,10 +145,7 @@ def runQuesta(args, flags, prefix):
         args.params = f' --params \\"{args.params}\\"'
     # Questa cannot accept more than 9 arguments.  fcov implies lockstep
     cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}"
-    if (args.gui):  # launch Questa with GUI; add +acc to keep variables accessible
-        cmd = f'cd $WALLY/sim/questa; {prefix} vsim -do "{cmd}  +acc"'
-    else: # launch Questa in batch mode
-        cmd = f'cd $WALLY/sim/questa; {prefix} vsim -c -do "{cmd}"'
+    cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
     print(f"Running Questa with command: {cmd}")
     os.system(cmd)
 
@@ -156,8 +155,6 @@ def runVerilator(args, flags, prefix):
 
 def runVCS(args, flags, prefix):
     print(f"Running VCS on {args.config} {args.testsuite}")
-    # if (args.gui):
-    #     flags += " --gui"
     if (args.args != ""):
         args.args = f' --args "{args.args}" '
     if (args.params != ""):
diff --git a/sim/questa/wally.do b/sim/questa/wally.do
index f42bf4930..3935d7a25 100644
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@@ -8,7 +8,7 @@
 #
 # Takes 1:10 to run RV64IC tests using gui
 
-# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [+acc] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"]
+# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"]
 # Example: do wally.do rv64gc arch64i testbench
 
 # Use this wally.do file to run this example.
@@ -91,7 +91,7 @@ echo "number of args = $argc"
 echo "lst = $lst"
 
 # if +acc found set flag and remove from list
-if {[lcheck lst "+acc"]} {
+if {[lcheck lst "--gui"]} {
     set GUI 1
     set accFlag "+acc"
 }

From bd9ca6ada6d0fac5dd67b3ac7a1cedc31c1ac91e Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Tue, 3 Dec 2024 00:18:00 -0800
Subject: [PATCH 08/28] Remove covlog

---
 bin/wsim | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 512ee5e42..1b0a848bf 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -32,7 +32,6 @@ def parseArgs():
     parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
     parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
     parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
-    parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
     parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
     return parser.parse_args()
 
@@ -113,10 +112,7 @@ def lockstepSetup(args):
 
     if (args.lockstep or args.lockstepverbose):
         if(args.fcov):
-            CovEnableStr = "1" if int(args.covlog) > 0  else "0"
-            if(args.covlog >= 1): EnableLog = 1
-            else: EnableLog = 0
-            ImperasPlusArgs = f" +IDV_TRACE2COV={EnableLog} +TRACE2LOG_AFTER={args.covlog} +TRACE2COV_ENABLE={CovEnableStr}"
+            ImperasPlusArgs = f" +IDV_TRACE2COV={0} +TRACE2LOG_AFTER={0} +TRACE2COV_ENABLE={0}"
         else:
             suffix = "--lockstep"
         if(args.lockstepverbose):

From 9f92572f2bd9fe3c4061a36a3b612761154072a4 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Tue, 3 Dec 2024 01:26:31 -0800
Subject: [PATCH 09/28] Significantly simplify lockstepSetup function now that
 covlog and locksteplog are removed

---
 bin/wsim | 38 ++++++++++++++------------------------
 1 file changed, 14 insertions(+), 24 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 1b0a848bf..0db6bb68d 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -76,6 +76,7 @@ def elfFileCheck(args):
 
 def prepSim(args, ElfFile):
     flags = ""
+    prefix = ""
     if args.vcd:
         args.params += " MAKE_VCD=1 "
     if args.rvvi:
@@ -92,33 +93,22 @@ def prepSim(args, ElfFile):
         flags += " --fcov"
     if args.gui:
         flags += " --gui"
-    prefix, suffix = lockstepSetup(args)
-    flags += suffix
+    if args.lockstep or args.lockstepverbose:
+        flags += " --lockstep"
+    if args.lockstep or args.lockstepverbose or args.fcov:
+        prefix = lockstepSetup(args)
     return flags, prefix
 
 def lockstepSetup(args):
-    prefix = ""
-    suffix = ""
-    ImperasPlusArgs = ""
-
-    if (args.lockstep or args.lockstepverbose or args.fcov):
-        imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
-        if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
-            imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
-            if not os.path.isfile(imperasicPath):
-                print("Error: imperas.ic not found")
-                exit(1)
-        prefix += f"IMPERAS_TOOLS={imperasicPath}"
-
-    if (args.lockstep or args.lockstepverbose):
-        if(args.fcov):
-            ImperasPlusArgs = f" +IDV_TRACE2COV={0} +TRACE2LOG_AFTER={0} +TRACE2COV_ENABLE={0}"
-        else:
-            suffix = "--lockstep"
-        if(args.lockstepverbose):
-            prefix += f":{WALLY}/sim/imperas-verbose.ic"
-    args.args += ImperasPlusArgs
-    return prefix, suffix
+    imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic")
+    imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
+    if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
+        imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
+        if not os.path.isfile(imperasicPath):
+            print("Error: imperas.ic not found")
+            exit(1)
+    prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''} "
+    return prefix
 
 def createDirs(args):
     for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:

From c1e6283201f736c43ae81e69c320ff4e59405f39 Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Tue, 3 Dec 2024 03:54:36 -0800
Subject: [PATCH 10/28] Added another signal for VM Coverage

---
 testbench/common/wallyTracer.sv | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 51f0d302a..7f7919ee3 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -69,6 +69,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [(P.XLEN-1):0]     PTE_iM,PTE_dM,PTE_iW,PTE_dW;
   logic [(P.PA_BITS-1):0]  PAIM,PADM,PAIW,PADW;
   logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW;
+  logic [1:0]              PageType_iM, PageType_iW, PageType_dM, PageType_dW;
   logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
   logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
 
@@ -121,6 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
   assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
   assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
+  assign PageType_iM    = testbench.dut.core.lsu.PageType;
+  assign PageType_dM    = testbench.dut.core.lsu.PageType;
 
   logic valid;
   
@@ -359,10 +362,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
   flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
   flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
-  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
-  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
+  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW);
+  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW);
   flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
   flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
+  flopenrc #(2)     PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW);
+  flopenrc #(2)     PageType_dWReg (clk, reset, FlushW, ~StallW, PageType_dM, PageType_dW);
   flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
   flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
   // *** what is this used for?

From 4591d625d52abee228c5a478f94d22f1596a4d0e Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Tue, 3 Dec 2024 03:54:36 -0800
Subject: [PATCH 11/28] Added another signal for VM Coverage

---
 testbench/common/wallyTracer.sv | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 51f0d302a..7f7919ee3 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -69,6 +69,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [(P.XLEN-1):0]     PTE_iM,PTE_dM,PTE_iW,PTE_dW;
   logic [(P.PA_BITS-1):0]  PAIM,PADM,PAIW,PADW;
   logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW;
+  logic [1:0]              PageType_iM, PageType_iW, PageType_dM, PageType_dW;
   logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
   logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
 
@@ -121,6 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
   assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
   assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
+  assign PageType_iM    = testbench.dut.core.lsu.PageType;
+  assign PageType_dM    = testbench.dut.core.lsu.PageType;
 
   logic valid;
   
@@ -359,10 +362,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
   flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
   flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
-  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
-  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
+  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW);
+  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW);
   flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
   flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
+  flopenrc #(2)     PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW);
+  flopenrc #(2)     PageType_dWReg (clk, reset, FlushW, ~StallW, PageType_dM, PageType_dW);
   flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
   flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
   // *** what is this used for?

From 8bd4b8b235bb8e843ccf9d54a6e12eabbb6944d3 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Tue, 3 Dec 2024 04:08:23 -0800
Subject: [PATCH 12/28] Simplify wsim createDirs function

---
 bin/wsim | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 0db6bb68d..a2527205a 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -110,9 +110,9 @@ def lockstepSetup(args):
     prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''} "
     return prefix
 
-def createDirs(args):
+def createDirs(sim):
     for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
-        os.makedirs(os.path.join(WALLY, "sim", args.sim, d), exist_ok=True)
+        os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True)
 
 def runSim(args, flags, prefix):
     if (args.sim == "questa"):
@@ -155,5 +155,5 @@ if __name__ == "__main__":
     print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'")
     ElfFile = elfFileCheck(args)
     flags, prefix = prepSim(args, ElfFile)
-    createDirs(args)
+    createDirs(args.sim)
     exit(runSim(args, flags, prefix))

From ffdaca2760c390e15a8827b4c9190203f759f3a0 Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Tue, 3 Dec 2024 04:09:11 -0800
Subject: [PATCH 13/28] Removing debug signals

---
 testbench/common/wallyTracer.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 7f7919ee3..0e691741c 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
   assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
   assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
-  assign PageType_iM    = testbench.dut.core.lsu.PageType;
-  assign PageType_dM    = testbench.dut.core.lsu.PageType;
+  assign PageType_iM    = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
+  assign PageType_dM    = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
 
   logic valid;
   
@@ -362,8 +362,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
   flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
   flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
-  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW);
-  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW);
+  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
+  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
   flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
   flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
   flopenrc #(2)     PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW);

From 54e09df77cdbf5c2a6acf77661f8e211340ed3d6 Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Tue, 3 Dec 2024 04:10:22 -0800
Subject: [PATCH 14/28] Removing debug signals

---
 testbench/common/wallyTracer.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 0e691741c..fbe5d0163 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
   assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
   assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
-  assign PageType_iM    = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
-  assign PageType_dM    = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
+  assign PageType_iM    = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
+  assign PageType_dM    = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
 
   logic valid;
   

From 3c848cd16c98fb5b4df1b9eae3cb173e9c5681ea Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Tue, 3 Dec 2024 09:56:03 -0600
Subject: [PATCH 15/28] Fixed bug in the wally tracer to support hptw pte
 accesses.

---
 testbench/common/wallyTracer.sv | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 51f0d302a..c873d5819 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -44,6 +44,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [31:0]           InstrRawD, InstrRawE, InstrRawM, InstrRawW;
   logic                  InstrValidM, InstrValidW;
   logic                  StallE, StallM, StallW;
+  logic                  GatedStallW;
   logic                  FlushD, FlushE, FlushM, FlushW;
   logic                  TrapM, TrapW;
   logic                  HaltM, HaltW;
@@ -89,6 +90,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign StallE         = testbench.dut.core.StallE;
   assign StallM         = testbench.dut.core.StallM;
   assign StallW         = testbench.dut.core.StallW;
+  assign GatedStallW         = testbench.dut.core.lsu.GatedStallW;
   assign FlushD         = testbench.dut.core.FlushD;
   assign FlushE         = testbench.dut.core.FlushE;
   assign FlushM         = testbench.dut.core.FlushM;
@@ -359,12 +361,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
   flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
   flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
-  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
-  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
-  flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
-  flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
-  flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
-  flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
+  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW);
+  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW);
+  flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW);
+  flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW);
+  flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW);
+  flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW);
   // *** what is this used for?
   flopenrc #(1)  ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD);
   flopenrc #(1)  ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);

From c1eab9e77894f8cb8072867cbcd3d5eb61604043 Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Thu, 5 Dec 2024 06:55:23 -0800
Subject: [PATCH 16/28] Updates to WallyTracer

---
 testbench/common/wallyTracer.sv | 39 +++++++++++++++++++--------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 70ed2b159..f74fb3d06 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -360,23 +360,28 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(1)     CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
 
   //for VM Verification
-  flopenrc #(P.XLEN)     VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW);
-  flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
-  flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
-  flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
-  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW);
-  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW);
-  flopenrc #(2)     PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW);
-  flopenrc #(2)     PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW);
-  flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW);
-  flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW);
-  flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW);
-  flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW);
-  // *** what is this used for?
-  flopenrc #(1)  ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD);
-  flopenrc #(1)  ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);
-  flopenrc #(1)  ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM);
-  flopenrc #(1)  ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW);
+  flopenrc #(P.XLEN)     VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); //Virtual Address for IMMU
+  flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); //Virtual Address for DMMU
+
+  flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); //Physical Address for IMMU
+  flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); //Physical Address for DMMU
+
+  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); //PTE for IMMU
+  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); //PTE for DMMU
+
+  flopenrc #(2)     PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); //Page Type (kilo, mega, giga, tera) from IMMU
+  flopenrc #(2)     PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); //Page Type (kilo, mega, giga, tera) from DMMU
+
+  flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU
+  flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU
+
+  flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess
+  flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess
+
+  flopenrc #(1)  ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access
+  flopenrc #(1)  ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access
+  flopenrc #(1)  ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access
+  flopenrc #(1)  ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access
 
   // Initially connecting the writeback stage signals, but may need to use M stage
   // and gate on ~FlushW.

From a3cd2669672f8566e6710cf7277632ad93c8f7a9 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 12:54:51 -0800
Subject: [PATCH 17/28] Fix run_vcs code coverage flag

---
 sim/vcs/run_vcs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs
index 1234ac4c8..fb04d0fd2 100755
--- a/sim/vcs/run_vcs
+++ b/sim/vcs/run_vcs
@@ -24,8 +24,8 @@ parser = argparse.ArgumentParser()
 parser.add_argument("config", help="Configuration file")
 parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
 parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
-parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
-parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
+parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
+parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true")
 parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
 parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
 parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
@@ -65,7 +65,7 @@ else:
     LOCKSTEP_SIMV = ""
 
 # coverage mode
-if (args.coverage):
+if (args.ccov):
     COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage"
 else:
     COV_OPTIONS = ""
@@ -93,6 +93,6 @@ SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args +
 print("Executing: " + str(VCS) )
 subprocess.run(VCS, shell=True)
 subprocess.run(SIMV_CMD, shell=True)
-if (args.coverage):
+if (args.ccov):
     COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite
     subprocess.run(COV_RUN, shell=True)

From 14ad03cde13b3d33cd6d56f538d6ccf00baca3c4 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 12:55:48 -0800
Subject: [PATCH 18/28] Add .memfile to gitignore

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 9a0f35cc1..1a8b66e80 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,6 +12,7 @@
 *.map
 *.elf*
 *.list
+*.memfile
 
 # General directories to ignore
 .vscode/

From 95a5070a729915f7bd56330e7e88746a48802ba4 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 12:56:12 -0800
Subject: [PATCH 19/28] Move IMPERAS_HOME in wally.do to avoid issue if not set

---
 sim/questa/wally.do | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/questa/wally.do b/sim/questa/wally.do
index 3935d7a25..6e073ea87 100644
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@@ -40,7 +40,6 @@ set TESTSUITE ${2}
 set TESTBENCH ${3}
 set WKDIR wkdir/${CFG}_${TESTSUITE}
 set WALLY $::env(WALLY)
-set IMPERAS_HOME $::env(IMPERAS_HOME)
 set CONFIG ${WALLY}/config
 set SRC ${WALLY}/src
 set TB ${WALLY}/testbench
@@ -118,6 +117,7 @@ if {[lcheck lst "--fcov"]} {
 
 # if --lockstep or --fcov found set flag and remove from list
 if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} {
+    set IMPERAS_HOME $::env(IMPERAS_HOME)
     set lockstep 1
     set lockstepvlog "+define+USE_IMPERAS_DV \
                       +incdir+${IMPERAS_HOME}/ImpPublic/include/host \

From 25cdf83aaee202eeb4c4c371f090efe0552ef884 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:13:35 -0800
Subject: [PATCH 20/28] Remove extra spaces and use lists for assembling args
 and params

---
 bin/wsim | 40 +++++++++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 17 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index a2527205a..1fde4eda1 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -39,7 +39,7 @@ def validateArgs(args):
     if not args.testsuite and not args.elf:
         print("Error: Missing test suite or ELF file")
         exit(1)
-    if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot" :
+    if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot":
         print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
         exit(1)
     elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]:
@@ -75,28 +75,34 @@ def elfFileCheck(args):
     return ElfFile
 
 def prepSim(args, ElfFile):
-    flags = ""
     prefix = ""
+    params = []
+    args = []
+    flags = []
     if args.vcd:
-        args.params += " MAKE_VCD=1 "
+        params.append("MAKE_VCD=1")
     if args.rvvi:
-        args.params += " RVVI_SYNTH_SUPPORTED=1 "
+        params.append("RVVI_SYNTH_SUPPORTED=1")
     if args.tb == "testbench_fp":
-        args.params += f' TEST="{args.testsuite}" '
-    if ElfFile != "":
-        args.args += f" {ElfFile}"
+        params.append(f'TEST="{args.testsuite}"')
+    if ElfFile:
+        args.append += f"{ElfFile}"
     if args.gui and args.tb == "testbench":
-        args.params += " DEBUG=1 "
+        params.append("DEBUG=1")
     if args.ccov:
-        flags += " --ccov"
+        flags.append("--ccov")
     if args.fcov:
-        flags += " --fcov"
+        flags.append("--fcov")
     if args.gui:
-        flags += " --gui"
+        flags.append("--gui")
     if args.lockstep or args.lockstepverbose:
-        flags += " --lockstep"
+        flags.append("--lockstep")
     if args.lockstep or args.lockstepverbose or args.fcov:
         prefix = lockstepSetup(args)
+    # Combine into a single string
+    args.args += " ".join(args)
+    args.params += " ".join(params)
+    flags = " ".join(flags)
     return flags, prefix
 
 def lockstepSetup(args):
@@ -107,7 +113,7 @@ def lockstepSetup(args):
         if not os.path.isfile(imperasicPath):
             print("Error: imperas.ic not found")
             exit(1)
-    prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''} "
+    prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
     return prefix
 
 def createDirs(sim):
@@ -126,9 +132,9 @@ def runQuesta(args, flags, prefix):
     # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
     prefix = "MTI_VCO_MODE=64 " + prefix
     if (args.args != ""):
-        args.args = f' --args \\"{args.args}\\"'
+        args.args = fr'--args \"{args.args}\"'
     if (args.params != ""):
-        args.params = f' --params \\"{args.params}\\"'
+        args.params = fr'--params \"{args.params}\"'
     # Questa cannot accept more than 9 arguments.  fcov implies lockstep
     cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}"
     cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
@@ -142,9 +148,9 @@ def runVerilator(args, flags, prefix):
 def runVCS(args, flags, prefix):
     print(f"Running VCS on {args.config} {args.testsuite}")
     if (args.args != ""):
-        args.args = f' --args "{args.args}" '
+        args.args = f'--args "{args.args}"'
     if (args.params != ""):
-        args.params = f' --params "{args.params}" '
+        args.params = f'--params "{args.params}"'
     cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}"
     print(cmd)
     os.system(cmd)

From bdc20243a6d183ca73bd8d7d9e317c46becdf551 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:18:03 -0800
Subject: [PATCH 21/28] Fix overriding args

---
 bin/wsim | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 1fde4eda1..9bc3252bc 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -76,33 +76,33 @@ def elfFileCheck(args):
 
 def prepSim(args, ElfFile):
     prefix = ""
-    params = []
-    args = []
-    flags = []
+    paramsList = []
+    argsList = []
+    flagsList = []
     if args.vcd:
-        params.append("MAKE_VCD=1")
+        paramsList.append("MAKE_VCD=1")
     if args.rvvi:
-        params.append("RVVI_SYNTH_SUPPORTED=1")
+        paramsList.append("RVVI_SYNTH_SUPPORTED=1")
     if args.tb == "testbench_fp":
-        params.append(f'TEST="{args.testsuite}"')
+        paramsList.append(f'TEST="{args.testsuite}"')
     if ElfFile:
-        args.append += f"{ElfFile}"
+        argsList.append += f"{ElfFile}"
     if args.gui and args.tb == "testbench":
-        params.append("DEBUG=1")
+        paramsList.append("DEBUG=1")
     if args.ccov:
-        flags.append("--ccov")
+        flagsList.append("--ccov")
     if args.fcov:
-        flags.append("--fcov")
+        flagsList.append("--fcov")
     if args.gui:
-        flags.append("--gui")
+        flagsList.append("--gui")
     if args.lockstep or args.lockstepverbose:
-        flags.append("--lockstep")
+        flagsList.append("--lockstep")
     if args.lockstep or args.lockstepverbose or args.fcov:
         prefix = lockstepSetup(args)
     # Combine into a single string
-    args.args += " ".join(args)
-    args.params += " ".join(params)
-    flags = " ".join(flags)
+    args.args += " ".join(argsList)
+    args.params += " ".join(paramsList)
+    flags = " ".join(flagsList)
     return flags, prefix
 
 def lockstepSetup(args):

From 59bedb78c58377df3844d27cdafcf97e65226856 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:24:10 -0800
Subject: [PATCH 22/28] Cleanup verilator paths

---
 sim/verilator/Makefile | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
index 6a6ad267a..666516c2d 100644
--- a/sim/verilator/Makefile
+++ b/sim/verilator/Makefile
@@ -17,12 +17,10 @@ EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS))
 
 WALLYCONF?=rv64gc
 TEST?=arch64i
-TESTBENCH?=testbench 	
+TESTBENCH?=testbench
 
 # constants
 # assume WALLY variable is correctly configured in the shell environment
-WORKING_DIR=${WALLY}/sim/verilator
-TARGET=$(WORKING_DIR)/target
 # INCLUDE_PATH are pathes that Verilator should search for files it needs
 INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
 # SOURCES are source files
@@ -30,6 +28,8 @@ SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbenc
 # DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
 DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
 
+WORKDIR = $(VERILATOR_DIR)/wkdir/$(WALLYCONF)_$(TEST)
+
 # regular testbench requires a wrapper defining getenvval
 ifeq ($(TESTBENCH), testbench)
 	WRAPPER=${WALLY}/sim/verilator/wrapper.c
@@ -41,9 +41,9 @@ endif
 
 default: run
 
-run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
+run: $(WORKDIR)/V${TESTBENCH}
 	mkdir -p $(VERILATOR_DIR)/logs
-	wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
+	$(WORKDIR)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
 
 profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
 	$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
@@ -54,10 +54,10 @@ profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
 	mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
 	echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
 
-wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES)
-	mkdir -p wkdir/$(WALLYCONF)_$(TEST)
+$(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES)
+	mkdir -p $(WORKDIR)
 	verilator \
-	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \
+	--Mdir $(WORKDIR) -o V${TESTBENCH} \
 	--binary --trace \
 	$(OPT) $(PARAMS) $(NONPROF) \
 	--top-module ${TESTBENCH}  --relative-includes \

From 8b2a053bd430972b74122ef935359500d1b0bc17 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:32:56 -0800
Subject: [PATCH 23/28] Remove unnecessary parentheses in wsim

---
 bin/wsim | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 9bc3252bc..597d7f111 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -121,19 +121,19 @@ def createDirs(sim):
         os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True)
 
 def runSim(args, flags, prefix):
-    if (args.sim == "questa"):
+    if args.sim == "questa":
         runQuesta(args, flags, prefix)
-    elif (args.sim == "verilator"):
+    elif args.sim == "verilator":
         runVerilator(args, flags, prefix)
-    elif (args.sim == "vcs"):
+    elif args.sim == "vcs":
         runVCS(args, flags, prefix)
 
 def runQuesta(args, flags, prefix):
     # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
     prefix = "MTI_VCO_MODE=64 " + prefix
-    if (args.args != ""):
+    if args.args != "":
         args.args = fr'--args \"{args.args}\"'
-    if (args.params != ""):
+    if args.params != "":
         args.params = fr'--params \"{args.params}\"'
     # Questa cannot accept more than 9 arguments.  fcov implies lockstep
     cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}"

From 8fc907a4966a0ace4998d9d681e492cf759eee3c Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:33:14 -0800
Subject: [PATCH 24/28] Switch to sys.exit in wsim

---
 bin/wsim | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 597d7f111..95bbda312 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -13,6 +13,7 @@
 
 import argparse
 import os
+import sys
 
 # Global variable
 WALLY = os.environ.get('WALLY')
@@ -38,16 +39,16 @@ def parseArgs():
 def validateArgs(args):
     if not args.testsuite and not args.elf:
         print("Error: Missing test suite or ELF file")
-        exit(1)
+        sys.exit(1)
     if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot":
         print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
-        exit(1)
+        sys.exit(1)
     elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]:
         print("Option only supported for Questa and VCS")
-        exit(1)
+        sys.exit(1)
     elif (args.tb == "testbench_fp" and args.sim != "questa"):
         print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench")
-        exit(1)
+        sys.exit(1)
 
 def elfFileCheck(args):
     ElfFile = ""
@@ -55,23 +56,23 @@ def elfFileCheck(args):
         ElfFile = f"+ElfFile={os.path.abspath(args.elf)}"
     elif args.elf != "":
         print(f"ELF file not found: {args.elf}")
-        exit(1)
+        sys.exit(1)
     elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead
         if os.path.isfile(args.testsuite):
             ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}"
             # extract the elf name from the path to be the test suite
             fields = args.testsuite.rsplit('/', 3)
             # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
-            if (len(fields) > 3):
-                if (fields[2] == "ref"):
+            if len(fields) > 3:
+                if fields[2] == "ref":
                     args.testsuite = f"{fields[1]}_{fields[3]}"
                 else:
                     args.testsuite = f"{fields[2]}_{fields[3]}"
-            elif ('/' in args.testsuite):
+            elif '/' in args.testsuite:
                 args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present
         else:
             print(f"ELF file not found: {args.testsuite}")
-            exit(1)
+            sys.exit(1)
     return ElfFile
 
 def prepSim(args, ElfFile):
@@ -112,7 +113,7 @@ def lockstepSetup(args):
         imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
         if not os.path.isfile(imperasicPath):
             print("Error: imperas.ic not found")
-            exit(1)
+            sys.exit(1)
     prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
     return prefix
 
@@ -147,9 +148,9 @@ def runVerilator(args, flags, prefix):
 
 def runVCS(args, flags, prefix):
     print(f"Running VCS on {args.config} {args.testsuite}")
-    if (args.args != ""):
+    if args.args != "":
         args.args = f'--args "{args.args}"'
-    if (args.params != ""):
+    if args.params != "":
         args.params = f'--params "{args.params}"'
     cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}"
     print(cmd)
@@ -162,4 +163,4 @@ if __name__ == "__main__":
     ElfFile = elfFileCheck(args)
     flags, prefix = prepSim(args, ElfFile)
     createDirs(args.sim)
-    exit(runSim(args, flags, prefix))
+    sys.exit(runSim(args, flags, prefix))

From c178180b0f50cda7de4098e46a2d51fdddc2491e Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:53:18 -0800
Subject: [PATCH 25/28] A bit more cleanup

---
 bin/wsim | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 95bbda312..dbe106280 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -43,7 +43,7 @@ def validateArgs(args):
     if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot":
         print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
         sys.exit(1)
-    elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]:
+    elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]:
         print("Option only supported for Questa and VCS")
         sys.exit(1)
     elif (args.tb == "testbench_fp" and args.sim != "questa"):
@@ -125,7 +125,7 @@ def runSim(args, flags, prefix):
     if args.sim == "questa":
         runQuesta(args, flags, prefix)
     elif args.sim == "verilator":
-        runVerilator(args, flags, prefix)
+        runVerilator(args)
     elif args.sim == "vcs":
         runVCS(args, flags, prefix)
 
@@ -142,7 +142,7 @@ def runQuesta(args, flags, prefix):
     print(f"Running Questa with command: {cmd}")
     os.system(cmd)
 
-def runVerilator(args, flags, prefix):
+def runVerilator(args):
     print(f"Running Verilator on {args.config} {args.testsuite}")
     os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"')
 

From c9885ff495ad6f314cb6bfddeb888336db6008b8 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:54:47 -0800
Subject: [PATCH 26/28] Change wsim main function for potential use as imported
 module in regression-wally

---
 bin/wsim | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index dbe106280..55ca015e6 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -156,11 +156,14 @@ def runVCS(args, flags, prefix):
     print(cmd)
     os.system(cmd)
 
-if __name__ == "__main__":
-    args = parseArgs()
+def main(args):
     validateArgs(args)
     print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'")
     ElfFile = elfFileCheck(args)
     flags, prefix = prepSim(args, ElfFile)
     createDirs(args.sim)
     sys.exit(runSim(args, flags, prefix))
+
+if __name__ == "__main__":
+    args = parseArgs()
+    main(args)

From 464a516e989309a2a134e3be48bcb6da47666147 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 13:58:45 -0800
Subject: [PATCH 27/28] Disable fcov on testsuite

---
 bin/wsim | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bin/wsim b/bin/wsim
index 55ca015e6..e8862ec95 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -40,8 +40,8 @@ def validateArgs(args):
     if not args.testsuite and not args.elf:
         print("Error: Missing test suite or ELF file")
         sys.exit(1)
-    if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot":
-        print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
+    if any([args.lockstep, args.lockstepverbose, args.fcov]) and not (args.testsuite.endswith('.elf') or args.elf) and args.testsuite != "buildroot":
+        print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep or fcov. Must run a single elf or buildroot.")
         sys.exit(1)
     elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]:
         print("Option only supported for Questa and VCS")

From 256211e4dcc3bfb806ba5d97ea25886aa06a8f4d Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 7 Dec 2024 14:06:31 -0800
Subject: [PATCH 28/28] Fix wsim elfile handling

---
 bin/wsim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bin/wsim b/bin/wsim
index e8862ec95..ebee44883 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -87,7 +87,7 @@ def prepSim(args, ElfFile):
     if args.tb == "testbench_fp":
         paramsList.append(f'TEST="{args.testsuite}"')
     if ElfFile:
-        argsList.append += f"{ElfFile}"
+        argsList.append(f"{ElfFile}")
     if args.gui and args.tb == "testbench":
         paramsList.append("DEBUG=1")
     if args.ccov: