Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

fixed some lint bugs.

Browse Source
This commit is contained in:
Ross Thompson 2021-09-09 12:38:57 -05:00
parent 8141a515bb
commit 90f2821bea
2 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
wally-pipelined/src/cache/cacheway.sv vendored
View File

@ -54,6 +54,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
logic [TAGLEN-1:0] ReadTag;
logic Valid;
logic Dirty;
logic SelectedWay;
genvar words;
@ -63,7 +64,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
.WIDTH(NUMLINES))
CacheDataMem(.clk(clk),
.Addr(RAdr),
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN]),
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end

2
wally-pipelined/src/cache/icache.sv vendored
View File

@ -142,7 +142,7 @@ module icache
.RAdr(RAdr),
.PAdr(PCTagF),
.WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable('1),
.WriteWordEnable({NUMWAYS{1'b1}}),
.TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable),