diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index 4d3641693..cb596846e 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -54,7 +54,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   logic [TAGLEN-1:0] 		      ReadTag;
   logic 			      Valid;
   logic 			      Dirty;
-
+  logic 			      SelectedWay;
+  
   genvar 			      words;
 
   generate
@@ -63,7 +64,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 		.WIDTH(NUMLINES))
       CacheDataMem(.clk(clk),
 		   .Addr(RAdr),
-		   .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN]),
+		   .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
 		   .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
 		   .WriteEnable(WriteEnable & WriteWordEnable[words]));
     end
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 7992c56c5..10f077c7a 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -142,7 +142,7 @@ module icache
 			 .RAdr(RAdr),
 			 .PAdr(PCTagF),
 			 .WriteEnable(SRAMWayWriteEnable), 
-			 .WriteWordEnable('1),
+			 .WriteWordEnable({NUMWAYS{1'b1}}),
 			 .TagWriteEnable(SRAMWayWriteEnable),
 			 .WriteData(ICacheMemWriteData),
 			 .SetValid(ICacheMemWriteEnable),