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fixed some lint bugs.

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This commit is contained in:
Ross Thompson 2021-09-09 12:38:57 -05:00
parent 8141a515bb
commit 90f2821bea
2 changed files with 4 additions and 3 deletions
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3
wally-pipelined/src/cache/cacheway.sv vendored
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@ -54,6 +54,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
logic [TAGLEN-1:0] ReadTag; logic [TAGLEN-1:0] ReadTag;
logic Valid; logic Valid;
logic Dirty; logic Dirty;
logic SelectedWay;
genvar words; genvar words;
@ -63,7 +64,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
.WIDTH(NUMLINES)) .WIDTH(NUMLINES))
CacheDataMem(.clk(clk), CacheDataMem(.clk(clk),
.Addr(RAdr), .Addr(RAdr),
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN]), .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words])); .WriteEnable(WriteEnable & WriteWordEnable[words]));
end end

2
wally-pipelined/src/cache/icache.sv vendored
View File

@ -142,7 +142,7 @@ module icache
.RAdr(RAdr), .RAdr(RAdr),
.PAdr(PCTagF), .PAdr(PCTagF),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable('1), .WriteWordEnable({NUMWAYS{1'b1}}),
.TagWriteEnable(SRAMWayWriteEnable), .TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData), .WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable), .SetValid(ICacheMemWriteEnable),