Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.

2025-02-11 06:05:49 +00:00 · 2021-04-02 06:27:37 -05:00 · 2021-04-02 06:27:37 -05:00 · 9026357350
commit 9026357350
parent 59dee5580c
15 changed files with 310 additions and 239 deletions
--- a/wally-pipelined/regression/vish_stacktrace.vstf
+++ b/wally-pipelined/regression/vish_stacktrace.vstf
@ -0,0 +1,3 @@
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
--- a/wally-pipelined/regression/wally-pipelined-muldiv.do
+++ b/wally-pipelined/regression/wally-pipelined-muldiv.do
@ -42,7 +42,7 @@ vsim workopt
 view wave

 -- display input and output signals as hexidecimal values
-do ./wave-dos/ahb-waves.do
+do ./wave-dos/ahb-muldiv.do

 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
--- a/wally-pipelined/regression/wave-dos/ahb-muldiv.do
+++ b/wally-pipelined/regression/wave-dos/ahb-muldiv.do
@ -0,0 +1,96 @@
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+
+#add wave /testbench/dut/hart/ebu/IReadF
+add wave -noupdate -divider -height 32 "Stalls"
+add wave /testbench/dut/hart/DataStall
+add wave /testbench/dut/hart/InstrStall
+add wave /testbench/dut/hart/StallF
+add wave /testbench/dut/hart/StallD
+add wave /testbench/dut/hart/StallE
+add wave /testbench/dut/hart/StallM
+add wave /testbench/dut/hart/StallW
+add wave /testbench/dut/hart/FlushD
+add wave /testbench/dut/hart/FlushE
+add wave /testbench/dut/hart/FlushM
+add wave /testbench/dut/hart/FlushW
+
+add wave -noupdate -divider -height 32 "MulDiv"
+add wave -hex /testbench/dut/hart/mdu/*
+
+add wave -noupdate -divider -height 32 "Integer Divider"
+add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
+add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/NEXT_STATE
+add wave -hex /testbench/dut/hart/mdu/genblk1/div/*
+
+
+
+add wave -noupdate -divider -height 32 "RF"
+add wave -hex /testbench/dut/hart/ieu/dp/regf/*
+add wave -hex /testbench/dut/hart/ieu/dp/regf/rf
+
+
+add wave -divider
+add wave -hex /testbench/dut/hart/ifu/PCF
+add wave -hex /testbench/dut/hart/ifu/PCD
+add wave -hex /testbench/dut/hart/ifu/InstrD
+
+add wave /testbench/InstrDName
+add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD
+add wave -hex /testbench/dut/hart/ifu/ic/AlignedInstrD
+add wave -divider
+add wave -hex /testbench/dut/hart/ifu/ic/InstrPAdrF
+add wave /testbench/dut/hart/ifu/ic/DelayF
+add wave /testbench/dut/hart/ifu/ic/DelaySideF
+add wave /testbench/dut/hart/ifu/ic/DelayD
+add wave -hex /testbench/dut/hart/ifu/ic/MisalignedHalfInstrD
+add wave -divider
+
+add wave -hex /testbench/dut/hart/ifu/PCE
+add wave -hex /testbench/dut/hart/ifu/InstrE
+add wave /testbench/InstrEName
+add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
+add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
+add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
+#add wave /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -divider
+
+add wave -hex /testbench/dut/hart/ifu/PCM
+add wave -hex /testbench/dut/hart/ifu/InstrM
+add wave /testbench/InstrMName
+add wave /testbench/dut/uncore/dtim/memwrite
+add wave -hex /testbench/dut/uncore/HADDR
+add wave -hex /testbench/dut/uncore/HWDATA
+add wave -divider
+
+add wave -hex /testbench/dut/hart/ebu/MemReadM
+add wave -hex /testbench/dut/hart/ebu/InstrReadF
+add wave -hex /testbench/dut/hart/ebu/BusState
+add wave -hex /testbench/dut/hart/ebu/NextBusState
+add wave -hex /testbench/dut/hart/ebu/HADDR
+add wave -hex /testbench/dut/hart/ebu/HREADY
+add wave -hex /testbench/dut/hart/ebu/HTRANS
+add wave -hex /testbench/dut/hart/ebu/HRDATA
+add wave -hex /testbench/dut/hart/ebu/HWRITE
+add wave -hex /testbench/dut/hart/ebu/HWDATA
+add wave -hex /testbench/dut/hart/ebu/CaptureDataM
+add wave -hex /testbench/dut/hart/ebu/InstrStall
+add wave -divider
+
+add wave -hex /testbench/dut/uncore/dtim/*
+add wave -divider
+
+add wave -hex /testbench/dut/hart/ifu/PCW
+add wave -hex /testbench/dut/hart/ifu/InstrW
+add wave /testbench/InstrWName
+add wave /testbench/dut/hart/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/hart/ebu/ReadDataW
+add wave -hex /testbench/dut/hart/ieu/dp/ResultW
+add wave -hex /testbench/dut/hart/ieu/dp/RdW
+add wave -divider
+
+add wave -hex /testbench/dut/uncore/dtim/*
+add wave -divider
+
+add wave -hex -r /testbench/*
--- a/wally-pipelined/regression/wave-osu.do
+++ b/wally-pipelined/regression/wave-osu.do
@ -1,75 +0,0 @@
-# wally-pipelined.do 
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# Use this wally-pipelined.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
-# do wally-pipelined.do ../config/rv32ic
-switch $argc {
-    0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
-    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
-}
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt +acc work.testbench -o workopt 
-vsim workopt
-
-view wave
-
-- display input and output signals as hexidecimal values
-# Diplays All Signals recursively
-- display input and output signals as hexidecimal values
-# Diplays All Signals recursively
-add wave /testbench/clk
-add wave /testbench/reset
-add wave -noupdate -divider -height 32 "Datapath"
-add wave -hex /testbench/dut/hart/ieu/dp/*
-add wave -noupdate -divider -height 32 "RF"
-add wave -hex /testbench/dut/hart/ieu/dp/regf/*
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf
-add wave -noupdate -divider -height 32 "Control"
-add wave -hex /testbench/dut/hart/ieu/c/*
-add wave -noupdate -divider -height 32 "Multiply/Divide"
-add wave -hex /testbench/dut/hart/mdu/*
-
-- Set Wave Output Items 
-TreeUpdate [SetDefaultTree]
-WaveRestoreZoom {0 ps} {100 ps}
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 120
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-set DefaultRadix hexadecimal
-
-- Run the Simulation 
-#run 1000
-run -all
-#quit
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@ -76,7 +76,7 @@ module hazard(
  // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
  assign FlushF = BPPredWrongE;
  assign FlushD = FirstUnstalledD || BranchFlushDE;  // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
-  assign FlushE = FirstUnstalledE || BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM;
+  assign FlushE = FirstUnstalledE || BranchFlushDE;  // LoadStallD | PCSrcE | RetM | TrapM;
  assign FlushM = FirstUnstalledM || RetM || TrapM;
  assign FlushW = FirstUnstalledW | TrapM;
 endmodule
--- a/wally-pipelined/src/ieu/forward.sv
+++ b/wally-pipelined/src/ieu/forward.sv
@ -30,7 +30,7 @@ module forward(
  input logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
  input logic 	     MemReadE, MulDivE, CSRReadE,
  input logic 	     RegWriteM, RegWriteW,
-  input logic 	     DivDoneW,
+  input logic 	     DivDoneE, DivBusyE,
  // Forwarding controls
  output logic [1:0] ForwardAE, ForwardBE,
  output logic 	     LoadStallD, MulDivStallD, CSRRdStallD
@ -50,7 +50,7 @@ module forward(

  // Stall on dependent operations that finish in Mem Stage and can't bypass in time
   assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));  
-   assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE&~DivDoneW; // *** extend with stalls for divide
+   assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE | DivBusyE; // *** extend with stalls for divide
   assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));

 endmodule
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@ -56,8 +56,8 @@ module ieu (
  input logic 		   FlushE, FlushM, FlushW,
  output logic 		   LoadStallD, MulDivStallD, CSRRdStallD,
  output logic 		   PCSrcE,
-  input logic 		   DivDoneW,
-
+  input logic 		   DivDoneE,
+  input logic 		   DivBusyE,
  output logic 		   CSRReadM, CSRWriteM, PrivilegedM,
  output logic 		   CSRWritePendingDEM
 );
--- a/wally-pipelined/src/muldiv/div.sv
+++ b/wally-pipelined/src/muldiv/div.sv
@ -23,7 +23,7 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////

-module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
+module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);

   input logic [63:0]  N, D;
   input logic 	       clk;
@ -33,9 +33,10 @@ module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
   output logic [63:0] Q;
   output logic [63:0] rem0;
   output logic        div0;
-   output logic        divdone;   
+   output logic        done;
+   output logic        divBusy;   

-   logic 	       done;   
+   logic 	       divdone;   
   logic 	       enable;
   logic 	       state0;
   logic 	       V;   
@ -86,7 +87,7 @@ module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
   // FSM to control integer divider
   //   assume inputs are postive edge and
   //   datapath (divider) is negative edge
-   fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov,
+   fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov, divBusyv,
 	       start, div0, NumIter, ~clk, reset);

   flopr #(1) rega (~clk, reset, donev, done);
@ -94,6 +95,7 @@ module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
   flopr #(1) regc (~clk, reset, otfzerov, otfzero);
   flopr #(1) regd (~clk, reset, enablev, enable);
   flopr #(1) rege (~clk, reset, state0v, state0);
+   flopr #(1) regf (~clk, reset, divBusyv, divBusy);      
   
   // To obtain a correct remainder the last bit of the
   // quotient has to be aligned with a radix-r boundary.
@ -460,7 +462,7 @@ endmodule // lz64

 // FSM Control for Integer Divider

-module fsm64 (en, state0, done, divdone, otfzero,
+module fsm64 (en, state0, done, divdone, otfzero, divBusy,
 	      start, error, NumIter, clk, reset);

   input logic [5:0]  NumIter;   
@ -474,6 +476,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
   output logic       state0;
   output logic       divdone;
   output logic       otfzero;
+   output logic       divBusy;   
   
   logic 	      LT, EQ;
   logic 	      Divide0;   
@ -519,6 +522,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 		 begin
 		    otfzero = 1'b1;   
 		    en = 1'b0;
+		    divBusy = 1'b0;		    
 		    state0 = 1'b0;
 		    divdone = 1'b0;		    
 		    done = 1'b0;
@ -528,6 +532,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 		 begin
 		    otfzero = 1'b0;	       		    
 		    en = 1'b1;
+		    divBusy = 1'b1;		    		    
 		    state0 = 1'b1;
 		    if (EQ)
 		      divdone = 1'b1;		    
@ -541,6 +546,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S1:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -564,6 +570,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S2:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -587,6 +594,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S3:
 	    begin	       
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -610,6 +618,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S4:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -633,6 +642,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S5:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -656,6 +666,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S6:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -679,6 +690,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S7:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -702,6 +714,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S8:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -725,6 +738,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S9:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -748,6 +762,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S10:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -771,6 +786,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S11:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -794,6 +810,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S12:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -817,6 +834,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S13:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -840,6 +858,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S14:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -863,6 +882,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S15:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -886,6 +906,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S16:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -909,6 +930,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S17:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -932,6 +954,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S18:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -955,6 +978,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S19:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -978,6 +1002,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S20:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1001,6 +1026,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S21:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1024,6 +1050,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S22:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1047,6 +1074,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S23:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1070,6 +1098,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S24:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1093,6 +1122,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S25:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1116,6 +1146,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S26:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1139,6 +1170,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S27:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1162,6 +1194,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S28:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1185,6 +1218,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S29:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1208,6 +1242,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S30:
 	    begin
 	       otfzero = 1'b0;
+     	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1231,6 +1266,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S31:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1254,6 +1290,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S32:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1277,6 +1314,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S33:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1300,6 +1338,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S34:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1323,6 +1362,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S35:
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       if (LT|EQ)
 		 begin
 		    en = 1'b1;
@ -1346,6 +1386,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  S36:
 	    begin
 	       otfzero = 1'b1;
+	       divBusy = 1'b1;	       
 	       state0 = 1'b0;
 	       done = 1'b1;
 	       if (EQ)
@ -1363,6 +1404,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
 	  default: 
 	    begin
 	       otfzero = 1'b0;
+	       divBusy = 1'b1;	       
 	       en = 1'b0;
 	       state0 = 1'b0;
 	       done = 1'b0;
--- a/wally-pipelined/src/muldiv/div/div
+++ b/wally-pipelined/src/muldiv/div/div
--- a/wally-pipelined/src/muldiv/div/div.c
+++ b/wally-pipelined/src/muldiv/div/div.c
@ -8,8 +8,12 @@ int main() {
  uint64_t D;
  uint64_t Q;

-  N = 0xc9649f05a8e1a8bb;
-  D = 0x82f6747f707af2c0;
+  //N = 0xc9649f05a8e1a8bb;
+  //D = 0x82f6747f707af2c0;
+  //N = 0x10fd3dedadea5195;
+  //D = 0xdf7f3844121bcc23;
+  N = 0x4;
+  D = 0xbfffffffffffffff;
  Q = N/D;

  printf("N = %" PRIx64 "\n", N);
--- a/wally-pipelined/src/muldiv/div/div64.out
+++ b/wally-pipelined/src/muldiv/div/div64.out
@ -1,107 +1,67 @@
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-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
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--- a/wally-pipelined/src/muldiv/div/test_int64div.sv
+++ b/wally-pipelined/src/muldiv/div/test_int64div.sv
@ -17,7 +17,16 @@ module tb;

   logic [7:0] 	 count [0:15];

+   bit [63:0] 	 Ncomp;
+   bit [63:0] 	 Dcomp;
+   bit [63:0] 	 Qcomp;
+   bit [63:0] 	 Rcomp;      
+
   int64div dut (Q, done, divdone, rem, div0, N, D, clk, reset, start);
+   assign Ncomp = N;
+   assign Dcomp = D;
+   assign Qcomp = Ncomp/Dcomp;
+   assign Rcomp = Ncomp%Dcomp;	        

   initial 
     begin	
@ -30,6 +39,19 @@ module tb;
 	#800 $finish;		
     end

+      initial
+     begin
+	handle3 = $fopen("div64.out");
+	desc3 = handle3;
+     end
+
+   always 
+     begin
+	desc3 = handle3;
+	#5 $fdisplay(desc3, "%h %h | %h %h | %h %h %b %b",
+		     N, D, Q, rem, Qcomp, Rcomp, 
+		       (Q==Qcomp), (rem==Rcomp));	
+     end

   initial
     begin
@ -38,10 +60,8 @@ module tb;
 	#0  start = 1'b0;	
 	#0  reset = 1'b1;
 	#22 reset = 1'b0;	
-	//#25 N = 64'h0000_0000_9830_07C0;
-	//#0  D = 64'h0000_0000_0000_000C;
-	#25 N = 64'h0000_0000_06b9_7b0d;	
-	#0  D = 64'h0000_0000_46df_998d;
+	#25 N = 64'h10fd_3ded_adea_5195;
+	#0  D = 64'hdf7f_3844_121b_cc23;	
 	#0  start = 1'b1;
 	#50 start = 1'b0;	

--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@ -36,7 +36,8 @@ module muldiv (
 	       // Writeback stage
 	       output logic [`XLEN-1:0] MulDivResultW,
 	       // Divide Done
-	       output logic 		DivDoneW, 
+	       output logic 		DivDoneE,
+	       output logic 		DivBusyE, 
 	       // hazards
 	       input logic 		StallM, StallW, FlushM, FlushW 
 	       );
@ -48,10 +49,16 @@ module muldiv (
 	 logic [`XLEN-1:0] QuotE, RemE;
 	 logic [`XLEN*2-1:0] ProdE;
 	 
+	 logic 		     DivStartE;
+	 logic 		     startDivideE;
+
 	 // Multiplier
 	 mul mul(.*);
 	 // Divide
-	 div div (QuotE, RemE, DivDoneE, div0error, SrcAE, SrcBE, clk, reset, MulDivE);	 
+	 div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, SrcAE, SrcBE, clk, reset, startDivideE);
+
+	 // Added for debugging of start signal for divide
+	 assign startDivideE = MulDivE&DivStartE&~DivBusyE;

 	 // Select result
 	 always_comb
@ -64,6 +71,19 @@ module muldiv (
             3'b101: PrelimResultE = QuotE;
             3'b110: PrelimResultE = RemE;
             3'b111: PrelimResultE = RemE;
+           endcase // case (Funct3E)
+
+	 // Start Divide process
+	 always_comb
+           case (Funct3E)
+             3'b000: DivStartE = 1'b0;
+             3'b001: DivStartE = 1'b0;
+             3'b010: DivStartE = 1'b0;
+             3'b011: DivStartE = 1'b0;
+             3'b100: DivStartE = 1'b1;
+             3'b101: DivStartE = 1'b1;
+             3'b110: DivStartE = 1'b1;
+             3'b111: DivStartE = 1'b1;
           endcase
 	 
 	 // Handle sign extension for W-type instructions
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@ -84,7 +84,8 @@ module wallypipelinedhart (
  logic        PCSrcE;
  logic        CSRWritePendingDEM;
  logic        LoadStallD, MulDivStallD, CSRRdStallD;
-   logic       DivDoneW;   
+   logic       DivDoneE;
+   logic       DivBusyE;   
  logic [4:0] SetFflagsM;
  logic [2:0] FRM_REGW;
  logic       FloatRegWriteW;
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@ -54,9 +54,9 @@ module testbench();
                    "rv64m/I-MULH-01", "3000",
                    "rv64m/I-MULHSU-01", "3000",
                    "rv64m/I-MULHU-01", "3000",
-                    "rv64m/I-MULW-01", "3000"
+                    "rv64m/I-MULW-01", "3000",
 //                    "rv64m/I-DIV-01", "3000",
-//                    "rv64m/I-DIVU-01", "3000"
+                    "rv64m/I-DIVU-01", "3000"
 //                   "rv64m/I-DIVUW-01", "3000",
 //                   "rv64m/I-DIVW-01", "3000",
 //                    "rv64m/I-REM-01", "3000",