Updated email address authorship for my files.

bin/CModelBTBAccuracy.sh

@@ -1,7 +1,7 @@
 #!/bin/bash
 
 ###########################################
-## Written: ross1728@gmail.com
+## Written: rose@rosethompson.net
 ## Created: 23 October 2023
 ## Modified: 
 ##

bin/CModelBranchAccuracy.sh

@@ -1,7 +1,7 @@
 #!/bin/bash
 
 ###########################################
-## Written: ross1728@gmail.com
+## Written: rose@rosethompson.net
 ## Created: 12 March 2023
 ## Modified: 
 ##

bin/SeparateBranch.sh

@@ -1,7 +1,7 @@
 #!/bin/bash
 
 ###########################################
-## Written: ross1728@gmail.com
+## Written: rose@rosethompson.net
 ## Created: 12 March 2023
 ## Modified: 
 ##

bin/extractFunctionRadix.sh

@@ -4,7 +4,7 @@
 ## extractFunctionRadix.sh
 ##
 ## Written: Rose Thompson
-## email: ross1728@gmail.com
+## email: rose@rosethompson.net
 ## Created: March 1, 2021
 ## Modified: March 10, 2021
 ##

bin/parseHPMC.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ###########################################
-## Written: Rose Thompson ross1728@gmail.com
+## Written: Rose Thompson rose@rosethompson.net
 ## Created: 20 September 2023
 ## Modified: 
 ##

bin/wally-tool-chain-install.sh

@@ -2,7 +2,7 @@
 ###########################################
 ## Tool chain install script.
 ##
-## Written: Rose Thompson ross1728@gmail.com
+## Written: Rose Thompson rose@rosethompson.net
 ## Created: 18 January 2023
 ## Modified: 22 January 2023
 ## Modified: 23 March 2023

fpga/rvvidaemon/rvvidaemon.c

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // rvvi daemon
 //
-// Written: Rose Thomposn ross1728@gmail.com
+// Written: Rose Thomposn rose@rosethompson.net
 // Created: 31 May 2024
 // Modified: 31 May 2024
 //

fpga/src/fpgaTop.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fpgaTop.sv
 //
-// Written: ross1728@gmail.com November 17, 2021
+// Written: rose@rosethompson.net November 17, 2021
 // Modified: 
 //
 // Purpose: This is a top level for the fpga's implementation of wally.

fpga/src/fpgaTopArtyA7.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fpgaTop.sv
 //
-// Written: ross1728@gmail.com November 17, 2021
+// Written: rose@rosethompson.net November 17, 2021
 // Modified: 
 //
 // Purpose: This is a top level for the fpga's implementation of wally.

fpga/src/wallypipelinedsocwrapper.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // wallypipelinedsocwrapper.sv
 //
-// Written: Rose Thompson ross1728@gmail.com 16 June 2023
+// Written: Rose Thompson rose@rosethompson.net 16 June 2023
 // Modified: 
 //
 // Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,

src/cache/cache.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // cache.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 7 July 2021
 // Modified: 20 January 2023
 //

src/cache/cacheLRU.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // cacheLRU.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 20 July 2021
 // Modified: 20 January 2023
 //

src/cache/cachefsm.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // cachefsm.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 25 August 2021
 // Modified: 20 January 2023
 //

src/cache/cacheway.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // cacheway
 //
-// Written: Rose Thompson ross1728@gmail.com 
+// Written: Rose Thompson rose@rosethompson.net 
 // Created: 7 July 2021
 // Modified: 20 January 2023
 //

src/cache/subcachelineread.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // subcachelineread.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 4 February 2022
 // Modified: 20 January 2023
 //

src/ebu/ahbcacheinterface.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // ahbcacheinterface.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: August 29, 2022
 // Modified: 18 January 2023
 //

src/ebu/ahbinterface.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // ahbinterface.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: August 29, 2022
 // Modified: 18 January 2023
 //

src/ebu/buscachefsm.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // busfsm.sv
 //
-// Written: Rose Thompson ross1728@gmail.com 
+// Written: Rose Thompson rose@rosethompson.net 
 // Created: December 29, 2021
 // Modified: 18 January 2023 
 //

src/ebu/busfsm.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // busfsm.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: December 29, 2021
 // Modified: 18 January 2023
 //

src/ebu/controllerinput.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // controllerinput.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created:  August 31, 2022
 // Modified: 18 January 2023
 //

src/ebu/ebu.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // abhmulticontroller
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: August 29, 2022
 // Modified: 18 January 2023
 //

src/ebu/ebufsmarb.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // ebufsmarb.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 23 January 2023
 // Modified: 23 January 2023
 //

src/generic/arrs.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // arrs.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Modified: November 12, 2021
 //
 // Purpose: resets are typically asynchronous but need to be synchronized to

src/generic/binencoder.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // binencoder.sv
 //
-// Written: ross1728@gmail.com November 14, 2022
+// Written: rose@rosethompson.net November 14, 2022
 //
 // Purpose: one-hot to binary encoding.
 //

src/generic/mem/ram1p1rwbe.sv

@@ -2,7 +2,7 @@
 // ram1p1r2be.sv
 // 1 port sram with byte enables
 //
-// Written: ross1728@gmail.com
+// Written: rose@rosethompson.net
 // Created: 3 May 2021
 // Modified: 20 January 2023
 //

src/generic/mem/ram1p1rwe.sv

@@ -2,7 +2,7 @@
 // ram1p1rwe.sv
 // 1 port sram.
 //
-// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com)
+// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net)
 // Created: 04 April 2023
 //
 // Purpose: ram1p1wre, but without byte-enable. Used for icache data.

src/generic/mem/ram2p1r1wbe.sv

@@ -2,7 +2,7 @@
 // ram2p1r1wbe.sv
 // 2 port sram.
 //
-// Written: ross1728@gmail.com May 3, 2021
+// Written: rose@rosethompson.net May 3, 2021
 //          Two port SRAM 1 read port and 1 write port.
 //          When clk rises Addr and LineWriteData are sampled.
 //          Following the clk edge read data is output from the sampled Addr.

src/generic/onehotdecoder.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // onehotdecoder.sv
 //
-// Written: ross1728@gmail.com July 09, 2021
+// Written: rose@rosethompson.net July 09, 2021
 // Modified: 
 //
 // Purpose: Bin to one hot decoder. Power of 2 only.

src/ifu/bpred/RASPredictor.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // RASPredictor.sv
 //
-// Written: Rose Thomposn ross1728@gmail.com
+// Written: Rose Thomposn rose@rosethompson.net
 // Created: 15 February 2021
 // Modified: 25 January 2023
 //

src/ifu/bpred/bpred.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // bpred.sv
 //
-// Written: Rose Thomposn ross1728@gmail.com
+// Written: Rose Thomposn rose@rosethompson.net
 // Created: 12 February 2021
 // Modified: 19 January 2023
 //

src/ifu/bpred/btb.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // btb.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: February 15, 2021
 // Modified: 24 January 2023 
 //

src/ifu/bpred/gshare.sv

@@ -2,7 +2,7 @@
 // gshare.sv
 //
 // Written: Rose Thompson
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: 16 March 2021
 // Adapted from ssanghai@hmc.edu (Shreya Sanghai)
 // Modified: 20 February 2023

src/ifu/bpred/gsharebasic.sv

@@ -2,7 +2,7 @@
 // gsharebasic.sv
 //
 // Written: Rose Thompson
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: 16 March 2021
 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
 // Modified: 20 February 2023 

src/ifu/bpred/icpred.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // icpred.sv
 //
-// Written: Rose Thomposn ross1728@gmail.com
+// Written: Rose Thomposn rose@rosethompson.net
 // Created: February 26, 2023
 // Modified: February 26, 2023
 //

src/ifu/bpred/localaheadbp.sv

@@ -2,7 +2,7 @@
 // localaheadbp
 //
 // Written: Rose Thompson
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: 16 March 2021
 //
 // Purpose: local history branch predictor with ahead pipelining and SRAM memories.

src/ifu/bpred/localbpbasic.sv

@@ -2,7 +2,7 @@
 // localbpbasic
 //
 // Written: Rose Thompson
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: 16 March 2021
 //
 // Purpose: Local history branch predictor. Basic implementation without any repair and flop memories.

src/ifu/bpred/localrepairbp.sv

@@ -2,7 +2,7 @@
 // localrepairbp
 //
 // Written: Rose Thompson
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: 15 April 2023
 //
 // Purpose: Local history branch predictor with speculation and repair using CBH.

src/ifu/bpred/satCounter2.sv

@@ -2,7 +2,7 @@
 // satCounter2.sv
 //
 // Written: Rose Thomposn
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: February 13, 2021
 // Modified: 
 //

src/ifu/bpred/twoBitPredictor.sv

@@ -2,7 +2,7 @@
 // twoBitPredictor.sv
 //
 // Written: Rose Thomposn
-// Email: ross1728@gmail.com
+// Email: rose@rosethompson.net
 // Created: February 14, 2021
 // Modified: 
 //

src/ifu/irom.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // irom.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 30 January 2022
 // Modified: 18 January 2023
 //

src/ifu/spill.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // spill.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 28 January 2022
 // Modified: 19 January 2023
 //

src/lsu/align.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // spill.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 26 October 2023
 // Modified: 26 October 2023
 //

src/lsu/atomic.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // atomic.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 31 January 2022
 // Modified: 18 January 2023
 //

src/lsu/dtim.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // dtim.sv
 //
-// Written: Rose Thompson ross1728@gmail.com 
+// Written: Rose Thompson rose@rosethompson.net 
 // Created: 30 January 2022
 // Modified: 18 January 2023
 //

src/lsu/lsu.sv

@@ -1,7 +1,7 @@
 /////////////////////////////////////////////////////////////////////////////////////////////////////////
 // lsu.sv
 //
-// Written: David_Harris@hmc.edu, ross1728@gmail.com
+// Written: David_Harris@hmc.edu, rose@rosethompson.net
 // Created: 9 January 2021
 // Modified: 11 January 2023 
 //

src/rvvi/csrindextoaddr.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // csrindextoaddr.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 24 January 2024
 // Modified: 24 January 2024
 //

src/rvvi/packetizer.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // packetizer.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 21 May 2024
 // Modified: 21 May 2024
 //

src/rvvi/priorityaomux.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // priorityaomux.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 24 January 2024
 // Modified: 24 January 2024
 //

src/rvvi/regchangedetect.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // regchangedetect.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 24 January 2024
 // Modified: 24 January 2024
 //

src/rvvi/rvvisynth.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // rvvisynth.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: 23 January 2024
 // Modified: 23 January 2024
 //

src/rvvi/triggergen.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // triggergen.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Created: June 26, 2024
 // Modified: June 26, 2024
 //

testbench/common/DCacheFlushFSM.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // DCacheFlushFSM.sv
 //
-// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
+// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net
 // Modified: 14 June 2023
 //
 // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

testbench/common/functionName.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // functionName.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // 
 // Purpose: decode name of function
 // 

testbench/common/loggers.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // loggers.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Modified: 14 June 2023
 // 
 // Purpose: Log branch instructions, log instruction fetches,

testbench/common/rvvitbwrapper.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // loggers.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Modified: 24 July 2024
 // 
 // Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench.

testbench/common/watchdog.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // watchdog.sv
 //
-// Written: Rose Thompson ross1728@gmail.com
+// Written: Rose Thompson rose@rosethompson.net
 // Modified: 14 June 2023
 //
 // Purpose: Detects if the processor is stuck and halts the simulation

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S

@@ -3,7 +3,7 @@
 // WALLY-cache-management-tests 
 // invalidate, clean, and flush
 //
-// Author: Rose Thompson <ross1728@gmail.com>
+// Author: Rose Thompson <rose@rosethompson.net>
 //
 // Created 18 August 2023
 //

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S

@@ -3,7 +3,7 @@
 // WALLY-cache-management-tests 
 // invalidate, clean, and flush
 //
-// Author: Rose Thompson <ross1728@gmail.com>
+// Author: Rose Thompson <rose@rosethompson.net>
 //
 // Created 22 August 2023
 //

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S

@@ -3,7 +3,7 @@
 // WALLY-cache-management-tests 
 // invalidate, clean, and flush
 //
-// Author: Rose Thompson <ross1728@gmail.com>
+// Author: Rose Thompson <rose@rosethompson.net>
 //
 // Created 18 August 2023
 //

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S

@@ -3,7 +3,7 @@
 // WALLY-cache-management-tests 
 // invalidate, clean, and flush
 //
-// Author: Rose Thompson <ross1728@gmail.com>
+// Author: Rose Thompson <rose@rosethompson.net>
 //
 // Created 22 August 2023
 //