From 30b085911ae5b027fe563405b337891a2411982b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 24 Jan 2023 05:42:34 -0800
Subject: [PATCH 01/84] bpred tab cleanup

---
 pipelined/src/ifu/bpred.sv | 54 +++++++++++++++++++-------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
index ab47d678f..94d0d692f 100644
--- a/pipelined/src/ifu/bpred.sv
+++ b/pipelined/src/ifu/bpred.sv
@@ -29,36 +29,36 @@
 `include "wally-config.vh"
 
 module bpred (
-   input logic              clk, reset,
-   input logic              StallF, StallD, StallE, StallM, StallW,
-   input logic              FlushD, FlushE, FlushM, FlushW,
-   // Fetch stage
-   // the prediction
-   input logic [31:0]       InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
-   input logic [`XLEN-1:0]  PCNextF,                   // Next Fetch Address
-   input logic [`XLEN-1:0]  PCPlus2or4F,               // PCF+2/4
-   output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
-   output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
+  input logic              clk, reset,
+  input logic              StallF, StallD, StallE, StallM, StallW,
+  input logic              FlushD, FlushE, FlushM, FlushW,
+  // Fetch stage
+  // the prediction
+  input logic [31:0]       InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
+  input logic [`XLEN-1:0]  PCNextF,                   // Next Fetch Address
+  input logic [`XLEN-1:0]  PCPlus2or4F,               // PCF+2/4
+  output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
+  output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
 
-   // Update Predictor
-   input logic [`XLEN-1:0]  PCF,                       // Fetch stage instruction address
-   input logic [`XLEN-1:0]  PCD,                       // Decode stage instruction address. Also the address the branch predictor took
-   input logic [`XLEN-1:0]  PCE,                       // Execution stage instruction address
-   input logic [`XLEN-1:0]  PCM,                       // Memory stage instruction address
+  // Update Predictor
+  input logic [`XLEN-1:0]  PCF,                       // Fetch stage instruction address
+  input logic [`XLEN-1:0]  PCD,                       // Decode stage instruction address. Also the address the branch predictor took
+  input logic [`XLEN-1:0]  PCE,                       // Execution stage instruction address
+  input logic [`XLEN-1:0]  PCM,                       // Memory stage instruction address
 
-   // Branch and jump outcome
-   input logic              PCSrcE,                    // Executation stage branch is taken
-   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
-   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
-   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  // Branch and jump outcome
+  input logic              PCSrcE,                    // Executation stage branch is taken
+  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
-   // Report branch prediction status
-   output logic             BPPredWrongE,              // Prediction is wrong
-   output logic             DirPredictionWrongM,       // Prediction direction is wrong
-   output logic             BTBPredPCWrongM,           // Prediction target wrong
-   output logic             RASPredPCWrongM,           // RAS prediction is wrong
-   output logic             PredictionInstrClassWrongM // Class prediction is wrong
-   );
+  // Report branch prediction status
+  output logic             BPPredWrongE,              // Prediction is wrong
+  output logic             DirPredictionWrongM,       // Prediction direction is wrong
+  output logic             BTBPredPCWrongM,           // Prediction target wrong
+  output logic             RASPredPCWrongM,           // RAS prediction is wrong
+  output logic             PredictionInstrClassWrongM // Class prediction is wrong
+);
 
   logic                     BTBValidF;
   logic [1:0]               DirPredictionF;

From 0e5ea5f51d4e7bee18dab0e3fb2402cff4e775f4 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 24 Jan 2023 06:14:31 -0800
Subject: [PATCH 02/84] bpred input spacing cleanup

---
 pipelined/src/ifu/bpred.sv | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
index 94d0d692f..d321169f4 100644
--- a/pipelined/src/ifu/bpred.sv
+++ b/pipelined/src/ifu/bpred.sv
@@ -29,27 +29,27 @@
 `include "wally-config.vh"
 
 module bpred (
-  input logic              clk, reset,
-  input logic              StallF, StallD, StallE, StallM, StallW,
-  input logic              FlushD, FlushE, FlushM, FlushW,
+  input  logic             clk, reset,
+  input  logic             StallF, StallD, StallE, StallM, StallW,
+  input  logic             FlushD, FlushE, FlushM, FlushW,
   // Fetch stage
   // the prediction
-  input logic [31:0]       InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
-  input logic [`XLEN-1:0]  PCNextF,                   // Next Fetch Address
-  input logic [`XLEN-1:0]  PCPlus2or4F,               // PCF+2/4
+  input  logic [31:0]      InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
+  input  logic [`XLEN-1:0] PCNextF,                   // Next Fetch Address
+  input  logic [`XLEN-1:0] PCPlus2or4F,               // PCF+2/4
   output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
   output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
 
   // Update Predictor
-  input logic [`XLEN-1:0]  PCF,                       // Fetch stage instruction address
-  input logic [`XLEN-1:0]  PCD,                       // Decode stage instruction address. Also the address the branch predictor took
-  input logic [`XLEN-1:0]  PCE,                       // Execution stage instruction address
-  input logic [`XLEN-1:0]  PCM,                       // Memory stage instruction address
+  input  logic [`XLEN-1:0] PCF,                       // Fetch stage instruction address
+  input  logic [`XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
+  input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
+  input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
 
   // Branch and jump outcome
-  input logic              PCSrcE,                    // Executation stage branch is taken
-  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
-  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic             PCSrcE,                    // Executation stage branch is taken
+  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
+  input  logic [`XLEN-1:0]  dPCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
   // Report branch prediction status

From 879cb77b9027fd856cb418266d080664c049b4c6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 24 Jan 2023 16:00:27 -0600
Subject: [PATCH 03/84] Moved branch predictor files into separate
 sub-directory.

---
 pipelined/src/ifu/{ => brpred}/BTBPredictor.sv             | 0
 pipelined/src/ifu/{ => brpred}/RAsPredictor.sv             | 0
 pipelined/src/ifu/{ => brpred}/bpred.sv                    | 0
 pipelined/src/ifu/{ => brpred}/foldedgshare.sv             | 0
 pipelined/src/ifu/{ => brpred}/globalHistoryPredictor.sv   | 0
 pipelined/src/ifu/{ => brpred}/globalhistory.sv            | 0
 pipelined/src/ifu/{ => brpred}/gshare.sv                   | 0
 pipelined/src/ifu/{ => brpred}/localHistoryPredictor.sv    | 0
 pipelined/src/ifu/{ => brpred}/oldgsharepredictor.sv       | 0
 pipelined/src/ifu/{ => brpred}/oldgsharepredictor2.sv      | 0
 pipelined/src/ifu/{ => brpred}/optgshare.sv                | 0
 pipelined/src/ifu/{ => brpred}/satCounter2.sv              | 0
 pipelined/src/ifu/{ => brpred}/speculativeglobalhistory.sv | 0
 pipelined/src/ifu/{ => brpred}/speculativegshare.sv        | 0
 pipelined/src/ifu/{ => brpred}/twoBitPredictor.sv          | 0
 15 files changed, 0 insertions(+), 0 deletions(-)
 rename pipelined/src/ifu/{ => brpred}/BTBPredictor.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/RAsPredictor.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/bpred.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/foldedgshare.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/globalHistoryPredictor.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/globalhistory.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/gshare.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/localHistoryPredictor.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/oldgsharepredictor.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/oldgsharepredictor2.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/optgshare.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/satCounter2.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/speculativeglobalhistory.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/speculativegshare.sv (100%)
 rename pipelined/src/ifu/{ => brpred}/twoBitPredictor.sv (100%)

diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/brpred/BTBPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/BTBPredictor.sv
rename to pipelined/src/ifu/brpred/BTBPredictor.sv
diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/RAsPredictor.sv
rename to pipelined/src/ifu/brpred/RAsPredictor.sv
diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
similarity index 100%
rename from pipelined/src/ifu/bpred.sv
rename to pipelined/src/ifu/brpred/bpred.sv
diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/brpred/foldedgshare.sv
similarity index 100%
rename from pipelined/src/ifu/foldedgshare.sv
rename to pipelined/src/ifu/brpred/foldedgshare.sv
diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/brpred/globalHistoryPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/globalHistoryPredictor.sv
rename to pipelined/src/ifu/brpred/globalHistoryPredictor.sv
diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv
similarity index 100%
rename from pipelined/src/ifu/globalhistory.sv
rename to pipelined/src/ifu/brpred/globalhistory.sv
diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv
similarity index 100%
rename from pipelined/src/ifu/gshare.sv
rename to pipelined/src/ifu/brpred/gshare.sv
diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/brpred/localHistoryPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/localHistoryPredictor.sv
rename to pipelined/src/ifu/brpred/localHistoryPredictor.sv
diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/brpred/oldgsharepredictor.sv
similarity index 100%
rename from pipelined/src/ifu/oldgsharepredictor.sv
rename to pipelined/src/ifu/brpred/oldgsharepredictor.sv
diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/brpred/oldgsharepredictor2.sv
similarity index 100%
rename from pipelined/src/ifu/oldgsharepredictor2.sv
rename to pipelined/src/ifu/brpred/oldgsharepredictor2.sv
diff --git a/pipelined/src/ifu/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv
similarity index 100%
rename from pipelined/src/ifu/optgshare.sv
rename to pipelined/src/ifu/brpred/optgshare.sv
diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/brpred/satCounter2.sv
similarity index 100%
rename from pipelined/src/ifu/satCounter2.sv
rename to pipelined/src/ifu/brpred/satCounter2.sv
diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
similarity index 100%
rename from pipelined/src/ifu/speculativeglobalhistory.sv
rename to pipelined/src/ifu/brpred/speculativeglobalhistory.sv
diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
similarity index 100%
rename from pipelined/src/ifu/speculativegshare.sv
rename to pipelined/src/ifu/brpred/speculativegshare.sv
diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/brpred/twoBitPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/twoBitPredictor.sv
rename to pipelined/src/ifu/brpred/twoBitPredictor.sv

From 7ae6b1868eca794bc0da9b060219a2961c251ec6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 24 Jan 2023 16:12:35 -0600
Subject: [PATCH 04/84] Partial BTB cleanup.

---
 pipelined/src/ifu/brpred/BTBPredictor.sv | 114 -----------------------
 pipelined/src/ifu/brpred/bpred.sv        |  13 ++-
 2 files changed, 6 insertions(+), 121 deletions(-)
 delete mode 100644 pipelined/src/ifu/brpred/BTBPredictor.sv

diff --git a/pipelined/src/ifu/brpred/BTBPredictor.sv b/pipelined/src/ifu/brpred/BTBPredictor.sv
deleted file mode 100644
index ba5fe374a..000000000
--- a/pipelined/src/ifu/brpred/BTBPredictor.sv
+++ /dev/null
@@ -1,114 +0,0 @@
-///////////////////////////////////////////
-// ram2p1r1wb
-//
-// Written: Ross Thomposn
-// Email: ross1728@gmail.com
-// Created: February 15, 2021
-// Modified: 
-//
-// Purpose: BTB model.  Outputs type of instruction (currently 1 hot encoded. Probably want 
-// to encode to reduce storage), valid, target PC.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module BTBPredictor
-  #(parameter int Depth = 10
-    )
-  (input  logic             clk,
-   input logic              reset,
-   input logic              StallF, StallE,
-   input logic [`XLEN-1:0]  LookUpPC,
-   output logic [`XLEN-1:0] TargetPC,
-   output logic [3:0]       InstrClass,
-   output logic             Valid,
-   // update
-   input logic              UpdateEN,
-   input logic [`XLEN-1:0]  UpdatePC,
-   input logic [`XLEN-1:0]  UpdateTarget,
-   input logic [3:0]        UpdateInstrClass,
-   input logic              UpdateInvalid
-   );
-
-  localparam TotalDepth = 2 ** Depth;
-  logic [TotalDepth-1:0]    ValidBits;
-  logic [Depth-1:0]         LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
-  logic                     UpdateENQ;
-  
-
-  // hashing function for indexing the PC
-  // We have Depth bits to index, but XLEN bits as the input.
-  // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
-  // using compressed instructions.  XOR bit 1 with the MSB of index.
-  assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
-  assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};  
-  
-
-  flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
-        .reset(reset),
-        .en(~StallE),
-        .d(UpdatePCIndex),
-        .q(UpdatePCIndexQ));
-  
-  // The valid bit must be resetable.
-  always_ff @ (posedge clk) begin
-    if (reset) begin
-      ValidBits <= #1 {TotalDepth{1'b0}};
-    end else 
-    if (UpdateENQ) begin
-      ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid;
-    end
-  end
-  assign Valid = ValidBits[LookUpPCIndexQ];
-
-
-  flopenr #(1) UpdateENReg(.clk(clk),
-     .reset(reset),
-     .en(~StallF),
-     .d(UpdateEN),
-     .q(UpdateENQ));
-
-
-  flopenr #(Depth) LookupPCIndexReg(.clk(clk),
-        .reset(reset),
-        .en(~StallF),
-        .d(LookUpPCIndex),
-        .q(LookUpPCIndexQ));
-
-
-
-  // the BTB contains the target address.
-  // Another optimization may be using a PC relative address.
-  // *** need to add forwarding.
-
-  // *** optimize for byte write enables
-  // *** switch to ram2p1r1wbefix
-  ram2p1r1wb #(Depth, `XLEN+4) memory(.clk(clk),
-          .reset(reset),
-          .ra1(LookUpPCIndex),
-          .rd1({{InstrClass, TargetPC}}),
-          .ren1(~StallF),
-          .wa2(UpdatePCIndex),
-          .wd2({UpdateInstrClass, UpdateTarget}),
-          .wen2(UpdateEN),
-          .bwe2({4'hF, {`XLEN{1'b1}}})); // *** definitely not right.
-
-
-endmodule
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index ab47d678f..9c5efe306 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -135,20 +135,19 @@ module bpred (
   // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
 
-  // *** getting to many false positivies from the BTB, we need a partial TAG to reduce this.
-  BTBPredictor TargetPredictor(.clk(clk),
+  btb TargetPredictor(.clk(clk),
           .reset(reset),
           .*, // Stalls and flushes
-          .LookUpPC(PCNextF),
-          .TargetPC(BTBPredPCF),
+          .PCNextF,
+          .BTBPredPCF,
           .InstrClass(PredInstrClassF),
           .Valid(BTBValidF),
           // update
           .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
-          .UpdatePC(PCE),
-          .UpdateTarget(IEUAdrE),
+          .PCE,
+          .IEUAdrE,
           .UpdateInvalid(PredictionInstrClassWrongE),
-          .UpdateInstrClass(InstrClassE));
+          .InstrClassE);
 
   // Part 3 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.

From 3d07f7a3a2f83a56ca1f76bfd09b53641942ebe0 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 24 Jan 2023 17:19:51 -0600
Subject: [PATCH 05/84] Moved and ranamed btb to btb.sv Fixed btb to use the
 fixed port 2 sram.

---
 pipelined/src/generic/mem/ram2p1r1wb.sv    |   8 +-
 pipelined/src/generic/mem/ram2p1rwbefix.sv |   4 +-
 pipelined/src/ifu/brpred/btb.sv            | 110 +++++++++++++++++++++
 3 files changed, 117 insertions(+), 5 deletions(-)
 create mode 100644 pipelined/src/ifu/brpred/btb.sv

diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv
index 5e79d5e24..7ac29e1df 100644
--- a/pipelined/src/generic/mem/ram2p1r1wb.sv
+++ b/pipelined/src/generic/mem/ram2p1r1wb.sv
@@ -74,12 +74,14 @@ module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
   flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q);
 
   // read port
-  assign rd1 = mem[ra1q];
+  //assign rd1 = mem[ra1q];
+  always_ff @(posedge clk)
+	if(ren1) rd1 <= mem[ra1];
   
   // write port
-  assign bwe = {WIDTH{wen2q}} & bwe2;
+  assign bwe = {WIDTH{wen2}} & bwe2;
   always_ff @(posedge clk)
-    mem[wa2q] <= wd2q & bwe | mem[wa2q] & ~bwe;
+    mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe;
  
 endmodule  
 
diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv
index 9b9beaf9b..ac30343b8 100644
--- a/pipelined/src/generic/mem/ram2p1rwbefix.sv
+++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv
@@ -59,13 +59,13 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
   
   // Write divided into part for bytes and part for extra msbs
   if(WIDTH >= 8) 
-    always_ff @(posedge clk) 
+    always @(posedge clk) 
       if (ce2 & we2) 
         for(i = 0; i < WIDTH/8; i++) 
           if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
   
   if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
-    always_ff @(posedge clk) 
+    always @(posedge clk) 
       if (ce2 & we2 & bwe2[WIDTH/8])
         mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
 
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
new file mode 100644
index 000000000..6666c35f9
--- /dev/null
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -0,0 +1,110 @@
+///////////////////////////////////////////
+// btb.sv
+//
+// Written: Ross Thomposn ross1728@gmail.com
+// Created: February 15, 2021
+// Modified: 24 January 2023 
+//
+// Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions.
+//          It also guesses the type of instrution; jalr(r), return, jump (jr), or branch.
+//
+// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module btb
+  #(parameter int Depth = 10
+    )
+  (input  logic             clk,
+   input  logic             reset,
+   input  logic             StallF, StallE,
+   input  logic [`XLEN-1:0] PCNextF,
+   output logic [`XLEN-1:0] BTBPredPCF,
+   output logic [3:0]       InstrClass,
+   output logic             Valid,
+   // update
+   input  logic             UpdateEN,
+   input  logic [`XLEN-1:0] PCE,
+   input  logic [`XLEN-1:0] IEUAdrE,
+   input  logic [3:0]       InstrClassE,
+   input  logic             UpdateInvalid
+   );
+
+  localparam TotalDepth = 2 ** Depth;
+  logic [TotalDepth-1:0]    ValidBits;
+  logic [Depth-1:0]         PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ;
+  logic                     UpdateENQ;
+  logic [`XLEN-1:0] 		ResetPC;
+
+
+  // hashing function for indexing the PC
+  // We have Depth bits to index, but XLEN bits as the input.
+  // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
+  // using compressed instructions.  XOR bit 1 with the MSB of index.
+  assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
+  assign ResetPC = `RESET_VECTOR;
+  assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
+  //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
+
+  flopenr #(Depth) PCEIndexReg(.clk(clk),
+        .reset(reset),
+        .en(~StallE),
+        .d(PCEIndex),
+        .q(PCEIndexQ));
+  
+  // The valid bit must be resetable.
+  always_ff @ (posedge clk) begin
+    if (reset) begin
+      ValidBits <= #1 {TotalDepth{1'b0}};
+    end else 
+    if (UpdateENQ) begin
+      ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid;
+    end
+  end
+  assign Valid = ValidBits[PCNextFIndexQ];
+
+
+  flopenr #(1) UpdateENReg(.clk(clk),
+     .reset(reset),
+     .en(~StallF),
+     .d(UpdateEN),
+     .q(UpdateENQ));
+
+
+  flopenr #(Depth) LookupPCIndexReg(.clk(clk),
+        .reset(reset),
+        .en(~StallF),
+        .d(PCNextFIndex),
+        .q(PCNextFIndexQ));
+
+
+
+  // the BTB contains the target address.
+  // Another optimization may be using a PC relative address.
+  // *** need to add forwarding.
+
+  // *** optimize for byte write enables
+
+  ram2p1r1wbefix #(2**Depth, `XLEN+4) memory(
+    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
+     .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
+
+endmodule

From 0d7653f1c7f17e7bf6f1fc250270366b4994c364 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 24 Jan 2023 17:22:00 -0600
Subject: [PATCH 06/84] Removed the old two port ram and replaced it with the
 fixed version. The fixed version is renamed to ram2p1r1wb.sv

---
 pipelined/src/generic/mem/ram2p1r1wb.sv       | 88 -------------------
 pipelined/src/generic/mem/ram2p1rwbefix.sv    |  6 +-
 pipelined/src/ifu/brpred/btb.sv               |  2 +-
 pipelined/src/ifu/brpred/foldedgshare.sv      |  2 +-
 pipelined/src/ifu/brpred/globalhistory.sv     |  2 +-
 pipelined/src/ifu/brpred/gshare.sv            |  2 +-
 pipelined/src/ifu/brpred/optgshare.sv         |  2 +-
 .../ifu/brpred/speculativeglobalhistory.sv    |  2 +-
 pipelined/src/ifu/brpred/speculativegshare.sv |  2 +-
 pipelined/src/ifu/brpred/twoBitPredictor.sv   |  2 +-
 10 files changed, 11 insertions(+), 99 deletions(-)
 delete mode 100644 pipelined/src/generic/mem/ram2p1r1wb.sv

diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv
deleted file mode 100644
index 7ac29e1df..000000000
--- a/pipelined/src/generic/mem/ram2p1r1wb.sv
+++ /dev/null
@@ -1,88 +0,0 @@
-///////////////////////////////////////////
-// ram2p1r1wb
-//
-// Written: Ross Thomposn
-// Email: ross1728@gmail.com
-// Created: February 14, 2021
-// Modified: 
-//
-// Purpose: Behavioral model of two port SRAM.  While this is synthesizable it will produce a flip flop based memory which
-//          behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm.
-//          
-// 
-// to preload this memory we can use the following command
-// in modelsim's do file.
-// mem load -infile <relative path to the text file > -format <bin|hex> <hierarchy to the memory.>
-// example
-// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
-  input  logic              clk,
-  input  logic              reset,
-
-  // port 1 is read only
-  input  logic [DEPTH-1:0]  ra1,
-  output logic [WIDTH-1:0]  rd1,
-  input  logic              ren1,
-
-  // port 2 is write only
-  input  logic [DEPTH-1:0]  wa2,
-  input  logic [WIDTH-1:0]  wd2,
-  input  logic              wen2,
-  input  logic [WIDTH-1:0]  bwe2
-);
-  
-
-  logic [DEPTH-1:0]         ra1q, wa2q;
-  logic                     wen2q;
-  logic [WIDTH-1:0]         wd2q;
-
-  logic [WIDTH-1:0]         mem[2**DEPTH-1:0];
-  logic [WIDTH-1:0]         bwe;
-
-  
-  // SRAMs address busses are always registered first
-  // *** likely issued DH and RT 12/20/22
-  //   wrong enable for write port registers
-  //  prefer to code read like ram1p1rw
-  //  prefer not to have two-cycle write latency
-  //  will require branch predictor changes
-  
-  flopenr #(DEPTH) ra1Reg(clk, reset, ren1, ra1, ra1q);
-  flopenr #(DEPTH) wa2Reg(clk, reset, ren1, wa2, wa2q);
-  flopr   #(1)     wen2Reg(clk, reset, wen2, wen2q);
-  flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q);
-
-  // read port
-  //assign rd1 = mem[ra1q];
-  always_ff @(posedge clk)
-	if(ren1) rd1 <= mem[ra1];
-  
-  // write port
-  assign bwe = {WIDTH{wen2}} & bwe2;
-  always_ff @(posedge clk)
-    mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe;
- 
-endmodule  
-
-
diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv
index ac30343b8..49354075b 100644
--- a/pipelined/src/generic/mem/ram2p1rwbefix.sv
+++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
-// 1 port sram.
+// 2 port sram.
 //
 // Written: ross1728@gmail.com May 3, 2021
-//          Basic sram with 1 read write port.
+//          Two port SRAM 1 read port and 1 write port.
 //          When clk rises Addr and LineWriteData are sampled.
 //          Following the clk edge read data is output from the sampled Addr.
 //          Write 
@@ -31,7 +31,7 @@
 
 `include "wally-config.vh"
 
-module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
+module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
   input  logic                     clk,
   input  logic                     ce1, ce2,
   input  logic [$clog2(DEPTH)-1:0] ra1,
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 6666c35f9..5f725b83a 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -103,7 +103,7 @@ module btb
 
   // *** optimize for byte write enables
 
-  ram2p1r1wbefix #(2**Depth, `XLEN+4) memory(
+  ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
      .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
 
diff --git a/pipelined/src/ifu/brpred/foldedgshare.sv b/pipelined/src/ifu/brpred/foldedgshare.sv
index 38e0fe610..2dfa48244 100644
--- a/pipelined/src/ifu/brpred/foldedgshare.sv
+++ b/pipelined/src/ifu/brpred/foldedgshare.sv
@@ -77,7 +77,7 @@ module foldedgshare
   assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
   assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
         
-  ram2p1r1wbefix #(2**depth, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
     .ra1(FinalIndexNextF),
     .rd1(TableDirPredictionF),
diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv
index 86c48f6b5..7aa86dbb9 100644
--- a/pipelined/src/ifu/brpred/globalhistory.sv
+++ b/pipelined/src/ifu/brpred/globalhistory.sv
@@ -51,7 +51,7 @@ module globalhistory
   logic                    PCSrcM;
   
       
-  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(GHR),
     .rd1(DirPredictionF),
diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv
index ca801a27c..ce189d268 100644
--- a/pipelined/src/ifu/brpred/gshare.sv
+++ b/pipelined/src/ifu/brpred/gshare.sv
@@ -54,7 +54,7 @@ module gshare
   assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
   assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]};
   
-  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),
diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv
index d911ec03e..fae59c675 100644
--- a/pipelined/src/ifu/brpred/optgshare.sv
+++ b/pipelined/src/ifu/brpred/optgshare.sv
@@ -153,7 +153,7 @@ module optgshare
   assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
   assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
       
-  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
index 6a4e3da04..094adca99 100644
--- a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
+++ b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
@@ -60,7 +60,7 @@ module speculativeglobalhistory
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
       
-  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
     .ra1(GHRNextF),
     .rd1(TableDirPredictionF),
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 3dd66366e..05753c76d 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -70,7 +70,7 @@ module speculativegshare
   assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
   assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
       
-  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
diff --git a/pipelined/src/ifu/brpred/twoBitPredictor.sv b/pipelined/src/ifu/brpred/twoBitPredictor.sv
index 3e41dfc4e..5a04a5fcf 100644
--- a/pipelined/src/ifu/brpred/twoBitPredictor.sv
+++ b/pipelined/src/ifu/brpred/twoBitPredictor.sv
@@ -56,7 +56,7 @@ module twoBitPredictor
   assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};  
 
 
-  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),

From 42553d1d94b0e887e8751faa22cf1880855ea6c4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 24 Jan 2023 17:26:54 -0600
Subject: [PATCH 07/84] Removed old versions of gshare.

---
 .../src/ifu/brpred/globalHistoryPredictor.sv  | 123 -----------------
 .../src/ifu/brpred/oldgsharepredictor.sv      | 130 ------------------
 .../src/ifu/brpred/oldgsharepredictor2.sv     | 130 ------------------
 3 files changed, 383 deletions(-)
 delete mode 100644 pipelined/src/ifu/brpred/globalHistoryPredictor.sv
 delete mode 100644 pipelined/src/ifu/brpred/oldgsharepredictor.sv
 delete mode 100644 pipelined/src/ifu/brpred/oldgsharepredictor2.sv

diff --git a/pipelined/src/ifu/brpred/globalHistoryPredictor.sv b/pipelined/src/ifu/brpred/globalHistoryPredictor.sv
deleted file mode 100644
index 92a3f9a1a..000000000
--- a/pipelined/src/ifu/brpred/globalHistoryPredictor.sv
+++ /dev/null
@@ -1,123 +0,0 @@
-///////////////////////////////////////////
-// globalHistoryPredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module globalHistoryPredictor
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallE,
-   input logic [`XLEN-1:0] PCNextF,
-   output logic [1:0]      BPPredF,
-   // update
-   input logic [4:0]       InstrClassE,
-   input logic [4:0]       BPInstrClassE,
-   input logic [4:0]       BPInstrClassD,
-   input logic [4:0]       BPInstrClassF, 
-   input logic             BPPredDirWrongE,
-
-   input logic [`XLEN-1:0] PCE,
-   input logic             PCSrcE,
-   input logic [1:0]       UpdateBPPredE
-  
-   );
-  logic [k+1:0]            GHR, GHRNext;
-  logic [k-1:0]            PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
-  logic                    PHTUpdateEN;
-  logic                    BPClassWrongNonCFI;
-  logic                    BPClassWrongCFI;
-  logic                    BPClassRightNonCFI;
-  logic                    BPClassRightBPWrong;
-  logic                    BPClassRightBPRight;
-
-  logic [6:0]              GHRMuxSel;
-  logic                    GHRUpdateEN;
-  logic [k-1:0]            GHRLookup;
-
-  assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
-  assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
-  assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
-  assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & BPPredDirWrongE;
-  assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~BPPredDirWrongE;
-  
-  
-  // GHR update selection, 1 hot encoded.
-  assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
-  assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
-  assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
-  assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
-  assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
-  assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
-  assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
-  assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
-
-  // hoping this created a AND-OR mux.
-  always_comb begin
-    case (GHRMuxSel) 
-      7'b000_0001: GHRNext = GHR[k-1+2:0];  // no change
-      7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
-      7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
-      7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
-      7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
-      7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
-      7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
-      default: GHRNext = GHR[k-1+2:0];
-    endcase
-  end
-
-  flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
-           .reset(reset),
-           .en((GHRUpdateEN)),
-           .d(GHRNext),
-           .q(GHR));
-
-  // if actively updating the GHR at the time of prediction we want to us
-  // GHRNext as the lookup rather than GHR.
-
-  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
-  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];  
-  assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
-  assign PHTUpdateEN = InstrClassE[0] & ~StallE;
-
-  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
-  
-  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  ram2p1r1wb #(k, 2) PHT(.clk(clk),
-    .reset(reset),
-    //.RA1(GHR[k-1:0]),
-    .ra1(GHRLookup),
-    .rd1(BPPredF),
-    .ren1(~StallF),
-    .wa2(PHTUpdateAdr),
-    .wd2(UpdateBPPredE),
-    .wen2(PHTUpdateEN),
-    .bwe2(2'b11));
-
-endmodule
diff --git a/pipelined/src/ifu/brpred/oldgsharepredictor.sv b/pipelined/src/ifu/brpred/oldgsharepredictor.sv
deleted file mode 100644
index 29a622517..000000000
--- a/pipelined/src/ifu/brpred/oldgsharepredictor.sv
+++ /dev/null
@@ -1,130 +0,0 @@
-///////////////////////////////////////////
-// globalHistoryPredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Gshare predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-module oldgsharepredictor
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, StallW, 
-   input logic             FlushD, FlushE, FlushM, FlushW,
-   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   output logic [1:0]      DirPredictionF,
-   // update
-   input logic [4:0]       InstrClassE,
-   input logic [4:0]       BPInstrClassE,
-   input logic [4:0]       BPInstrClassD,
-   input logic [4:0]       BPInstrClassF, 
-   output logic            DirPredictionWrongE,
-
-   input logic             PCSrcE
-  
-   );
-  logic [`BPRED_SIZE+1:0]  GHR, GHRNext;
-  logic [`BPRED_SIZE-1:0]  PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
-  logic                    PHTUpdateEN;
-  logic                    BPClassWrongNonCFI;
-  logic                    BPClassWrongCFI;
-  logic                    BPClassRightNonCFI;
-  logic                    BPClassRightBPWrong;
-  logic                    BPClassRightBPRight;
-  logic [1:0]              DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionE;
-
-  logic [6:0]              GHRMuxSel;
-  logic                    GHRUpdateEN;
-  logic [`BPRED_SIZE-1:0]            GHRLookup;
-
-  assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
-  assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
-  assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
-  assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
-  assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
-  
-  
-  // GHR update selection, 1 hot encoded.
-  assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
-  assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
-  assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
-  assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
-  assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
-  assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
-  assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
-  assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
-
-  // hoping this created a AND-OR mux.
-  always_comb begin
-    case (GHRMuxSel) 
-      7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0];  // no change
-      7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
-      7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
-      7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
-      7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
-      7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
-      7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
-      default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
-    endcase
-  end
-
-  flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
-           .reset(reset),
-           .en((GHRUpdateEN)),
-           .d(GHRNext),
-           .q(GHR));
-
-  // if actively updating the GHR at the time of prediction we want to us
-  // GHRNext as the lookup rather than GHR.
-
-  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
-  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];  
-  assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
-  assign PHTUpdateEN = InstrClassE[0] & ~StallE;
-
-  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
-  
-  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
-    .reset(reset),
-    //.RA1(GHR[`BPRED_SIZE-1:0]),
-    .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
-    .rd1(DirPredictionF),
-    .ren1(~StallF),
-    .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
-    .wd2(NewDirPredictionE),
-    .wen2(PHTUpdateEN),
-    .bwe2(2'b11));
-
-  // DirPrediction pipeline
-  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
-  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
-
-  // New prediction pipeline
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
-
-endmodule // gsharePredictor
diff --git a/pipelined/src/ifu/brpred/oldgsharepredictor2.sv b/pipelined/src/ifu/brpred/oldgsharepredictor2.sv
deleted file mode 100644
index 679358e37..000000000
--- a/pipelined/src/ifu/brpred/oldgsharepredictor2.sv
+++ /dev/null
@@ -1,130 +0,0 @@
-///////////////////////////////////////////
-// globalHistoryPredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Gshare predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-module oldgsharepredictor2
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, StallW, 
-   input logic             FlushD, FlushE, FlushM, FlushW,
-   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   output logic [1:0]      DirPredictionF,
-   // update
-   input logic [4:0]       InstrClassE,
-   input logic [4:0]       BPInstrClassE,
-   input logic [4:0]       BPInstrClassD,
-   input logic [4:0]       BPInstrClassF, 
-   output logic            DirPredictionWrongE,
-
-   input logic             PCSrcE
-  
-   );
-  logic [`BPRED_SIZE+1:0]  GHR, GHRNext;
-  logic [`BPRED_SIZE-1:0]  PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
-  logic                    PHTUpdateEN;
-  logic                    BPClassWrongNonCFI;
-  logic                    BPClassWrongCFI;
-  logic                    BPClassRightNonCFI;
-  logic                    BPClassRightBPWrong;
-  logic                    BPClassRightBPRight;
-  logic [1:0]              DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionE;
-
-  logic [6:0]              GHRMuxSel;
-  logic                    GHRUpdateEN;
-  logic [`BPRED_SIZE-1:0]            GHRLookup;
-
-  assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
-  assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
-  assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
-  assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
-  assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
-  
-  
-  // GHR update selection, 1 hot encoded.
-  assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
-  assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
-  assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
-  assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
-  assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
-  assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
-  assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
-  assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
-
-  // hoping this created a AND-OR mux.
-  always_comb begin
-    case (GHRMuxSel) 
-      7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0];  // no change
-      7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
-      7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
-      7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
-      7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
-      7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
-      7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
-      default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
-    endcase
-  end
-
-  flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
-           .reset(reset),
-           .en((GHRUpdateEN)),
-           .d(GHRNext),
-           .q(GHR));
-
-  // if actively updating the GHR at the time of prediction we want to us
-  // GHRNext as the lookup rather than GHR.
-
-  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
-  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];  
-  assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
-  assign PHTUpdateEN = InstrClassE[0] & ~StallE;
-
-  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
-  
-  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
-    .reset(reset),
-    //.RA1(GHR[`BPRED_SIZE-1:0]),
-    .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
-    .rd1(DirPredictionF),
-    .ren1(~StallF),
-    .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
-    .wd2(NewDirPredictionE),
-    .wen2(PHTUpdateEN),
-    .bwe2(2'b11));
-
-  // DirPrediction pipeline
-  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
-  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
-
-  // New prediction pipeline
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
-
-endmodule // gsharePredictor

From 1e7fda64103707269ba0a56bbb9ff589ea0311f2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 10:14:30 -0600
Subject: [PATCH 08/84] Fixed wrong header on optgshare.sv. Somehow it still
 had the old MIT license. Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv

---
 pipelined/src/generic/mem/ram2p1rwbefix.sv | 72 ----------------------
 pipelined/src/ifu/brpred/optgshare.sv      | 24 +++-----
 2 files changed, 10 insertions(+), 86 deletions(-)
 delete mode 100644 pipelined/src/generic/mem/ram2p1rwbefix.sv

diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv
deleted file mode 100644
index 49354075b..000000000
--- a/pipelined/src/generic/mem/ram2p1rwbefix.sv
+++ /dev/null
@@ -1,72 +0,0 @@
-///////////////////////////////////////////
-// 2 port sram.
-//
-// Written: ross1728@gmail.com May 3, 2021
-//          Two port SRAM 1 read port and 1 write port.
-//          When clk rises Addr and LineWriteData are sampled.
-//          Following the clk edge read data is output from the sampled Addr.
-//          Write 
-//
-// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
-
-`include "wally-config.vh"
-
-module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
-  input  logic                     clk,
-  input  logic                     ce1, ce2,
-  input  logic [$clog2(DEPTH)-1:0] ra1,
-  input  logic [WIDTH-1:0]         wd2,
-  input  logic [$clog2(DEPTH)-1:0] wa2,
-  input  logic                     we2,
-  input  logic [(WIDTH-1)/8:0]     bwe2,
-  output logic [WIDTH-1:0]         rd1
-);
-
-  logic [WIDTH-1:0]               mem[DEPTH-1:0];
-
-  // ***************************************************************************
-  // TRUE Smem macro
-  // ***************************************************************************
-
-  // ***************************************************************************
-  // READ first SRAM model
-  // ***************************************************************************
-    integer i;
-
-  // Read
-  always_ff @(posedge clk) 
-    if(ce1) rd1 <= #1 mem[ra1];
-  
-  // Write divided into part for bytes and part for extra msbs
-  if(WIDTH >= 8) 
-    always @(posedge clk) 
-      if (ce2 & we2) 
-        for(i = 0; i < WIDTH/8; i++) 
-          if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
-  
-  if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
-    always @(posedge clk) 
-      if (ce2 & we2 & bwe2[WIDTH/8])
-        mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
-
-endmodule
diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv
index fae59c675..1f99cfd26 100644
--- a/pipelined/src/ifu/brpred/optgshare.sv
+++ b/pipelined/src/ifu/brpred/optgshare.sv
@@ -12,22 +12,18 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
-//   substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

From a5bd78a62226115d91c1ad95bfeca10c4fe64ca0 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 10:17:43 -0600
Subject: [PATCH 09/84] Renamed file missed from last commit.

---
 pipelined/src/generic/mem/ram2p1rwbe.sv | 72 +++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 pipelined/src/generic/mem/ram2p1rwbe.sv

diff --git a/pipelined/src/generic/mem/ram2p1rwbe.sv b/pipelined/src/generic/mem/ram2p1rwbe.sv
new file mode 100644
index 000000000..49354075b
--- /dev/null
+++ b/pipelined/src/generic/mem/ram2p1rwbe.sv
@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// 2 port sram.
+//
+// Written: ross1728@gmail.com May 3, 2021
+//          Two port SRAM 1 read port and 1 write port.
+//          When clk rises Addr and LineWriteData are sampled.
+//          Following the clk edge read data is output from the sampled Addr.
+//          Write 
+//
+// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
+
+`include "wally-config.vh"
+
+module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
+  input  logic                     clk,
+  input  logic                     ce1, ce2,
+  input  logic [$clog2(DEPTH)-1:0] ra1,
+  input  logic [WIDTH-1:0]         wd2,
+  input  logic [$clog2(DEPTH)-1:0] wa2,
+  input  logic                     we2,
+  input  logic [(WIDTH-1)/8:0]     bwe2,
+  output logic [WIDTH-1:0]         rd1
+);
+
+  logic [WIDTH-1:0]               mem[DEPTH-1:0];
+
+  // ***************************************************************************
+  // TRUE Smem macro
+  // ***************************************************************************
+
+  // ***************************************************************************
+  // READ first SRAM model
+  // ***************************************************************************
+    integer i;
+
+  // Read
+  always_ff @(posedge clk) 
+    if(ce1) rd1 <= #1 mem[ra1];
+  
+  // Write divided into part for bytes and part for extra msbs
+  if(WIDTH >= 8) 
+    always @(posedge clk) 
+      if (ce2 & we2) 
+        for(i = 0; i < WIDTH/8; i++) 
+          if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
+  
+  if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
+    always @(posedge clk) 
+      if (ce2 & we2 & bwe2[WIDTH/8])
+        mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
+
+endmodule

From 5030a56f57a8473f396b690aad21c93b0829da82 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 11:41:16 -0600
Subject: [PATCH 10/84] Optomized gshare.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 05753c76d..eee2abc95 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -45,7 +45,7 @@ module speculativegshare
    input logic             PCSrcE
    );
 
-  logic                    MatchF, MatchD, MatchE, MatchM;
+  logic                    MatchF, MatchD, MatchE;
   logic                    MatchNextX, MatchXF;
 
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
@@ -57,7 +57,7 @@ module speculativegshare
   logic [k:-1] 			   GHRNextD, OldGHRD;
   logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
-  logic [k-1:0]            IndexD, IndexE, IndexM;
+  logic [k-1:0]            IndexD, IndexE;
   
   logic                    PCSrcM, PCSrcW;
   logic [`XLEN-1:0]        PCW;
@@ -68,15 +68,14 @@ module speculativegshare
   assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
   assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
   assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
-    .wa2(IndexM),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallW & ~FlushW),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
@@ -84,15 +83,13 @@ module speculativegshare
   assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
   assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
   assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
-  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
+  assign MatchNextX = MatchF | MatchD | MatchE;
 
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
                                    MatchD ? NewDirPredictionD :
-                                   MatchE ? NewDirPredictionE :
-                                   NewDirPredictionM;
+                                   NewDirPredictionE ;
   
   flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
 

From a0bca35b5043c8f8e7cd6a11aca25187f1823714 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 12:05:13 -0600
Subject: [PATCH 11/84] BTB cleanup.

---
 pipelined/src/ifu/brpred/bpred.sv |  2 +-
 pipelined/src/ifu/brpred/btb.sv   | 46 +++++++------------------------
 2 files changed, 11 insertions(+), 37 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 9c5efe306..6817dfd59 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -143,7 +143,7 @@ module bpred (
           .InstrClass(PredInstrClassF),
           .Valid(BTBValidF),
           // update
-          .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
+          .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
           .PCE,
           .IEUAdrE,
           .UpdateInvalid(PredictionInstrClassWrongE),
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 5f725b83a..8eba026ec 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -35,7 +35,7 @@ module btb
     )
   (input  logic             clk,
    input  logic             reset,
-   input  logic             StallF, StallE,
+   input  logic             StallF, StallE, StallM, FlushM,
    input  logic [`XLEN-1:0] PCNextF,
    output logic [`XLEN-1:0] BTBPredPCF,
    output logic [3:0]       InstrClass,
@@ -50,7 +50,7 @@ module btb
 
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
-  logic [Depth-1:0]         PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ;
+  logic [Depth-1:0]         PCNextFIndex, PCEIndex;
   logic                     UpdateENQ;
   logic [`XLEN-1:0] 		ResetPC;
 
@@ -60,51 +60,25 @@ module btb
   // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
   // using compressed instructions.  XOR bit 1 with the MSB of index.
   assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
+
+  // must output a valid PC and valid bit during reset.  Because the PCNextF logic of the IFU and trap units
+  // does not mux in RESET_VECTOR we have to do it here.  This is a performance optimization.
   assign ResetPC = `RESET_VECTOR;
   assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
-  //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
-
-  flopenr #(Depth) PCEIndexReg(.clk(clk),
-        .reset(reset),
-        .en(~StallE),
-        .d(PCEIndex),
-        .q(PCEIndexQ));
   
-  // The valid bit must be resetable.
   always_ff @ (posedge clk) begin
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
-    end else 
-    if (UpdateENQ) begin
-      ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid;
+    end else if (UpdateEN & ~StallM & ~FlushM) begin
+      ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
     end
+	Valid = ValidBits[PCNextFIndex];
   end
-  assign Valid = ValidBits[PCNextFIndexQ];
 
-
-  flopenr #(1) UpdateENReg(.clk(clk),
-     .reset(reset),
-     .en(~StallF),
-     .d(UpdateEN),
-     .q(UpdateENQ));
-
-
-  flopenr #(Depth) LookupPCIndexReg(.clk(clk),
-        .reset(reset),
-        .en(~StallF),
-        .d(PCNextFIndex),
-        .q(PCNextFIndexQ));
-
-
-
-  // the BTB contains the target address.
-  // Another optimization may be using a PC relative address.
+  // An optimization may be using a PC relative address.
   // *** need to add forwarding.
-
-  // *** optimize for byte write enables
-
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
-     .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
+     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
 
 endmodule

From 85e015d61ec5717190176fbe8521881476258350 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 12:08:54 -0600
Subject: [PATCH 12/84] Found minor bug in gshare.

---
 pipelined/config/rv32ic/wally-config.vh       | 2 +-
 pipelined/src/ifu/brpred/speculativegshare.sv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index 311ce8ab2..dbe29a2ee 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -132,7 +132,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_ENABLED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index eee2abc95..489024491 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -70,7 +70,7 @@ module speculativegshare
   assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
+    .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
     .wa2(IndexE),

From 62d812b150af3a37d84381f335b337c2ea2b0eda Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 12:09:02 -0600
Subject: [PATCH 13/84] Updated gitflow.

---
 gitflow.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gitflow.txt b/gitflow.txt
index 57d79333b..57300830a 100644
--- a/gitflow.txt
+++ b/gitflow.txt
@@ -48,3 +48,6 @@ Create pull request
    1. git pull upstream main          # fetch and merge the upstream openhwgroup/cvw into your local clone
    3. git push                        # sync your fork with the upstream and clone
         
+
+If the pull request need changes, modify accordingly, commit, and push changes back to the fork.
+The pull request will automatically update.

From 541524a7549bb2e28af69927e6c881b97007c8cf Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 12:14:18 -0600
Subject: [PATCH 14/84] More btb cleanup.

---
 pipelined/src/ifu/brpred/bpred.sv | 10 +++++-----
 pipelined/src/ifu/brpred/btb.sv   |  8 ++++----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 6817dfd59..dd7b9e850 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -60,7 +60,7 @@ module bpred (
    output logic             PredictionInstrClassWrongM // Class prediction is wrong
    );
 
-  logic                     BTBValidF;
+  logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
   logic [3:0]               PredInstrClassF, PredInstrClassD, PredInstrClassE;
@@ -128,9 +128,9 @@ module bpred (
   // 1) A direction (1 = Taken, 0 = Not Taken)
   // 2) Any information which is necessary for the predictor to build its next state.
   // For a 2 bit table this is the prediction count.
-  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | 
+  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
          PredInstrClassF[2] |
-         (PredInstrClassF[1] & BTBValidF) ;
+         (PredInstrClassF[1] & PredValidF) ;
 
   // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
@@ -140,8 +140,8 @@ module bpred (
           .*, // Stalls and flushes
           .PCNextF,
           .BTBPredPCF,
-          .InstrClass(PredInstrClassF),
-          .Valid(BTBValidF),
+          .PredInstrClassF,
+          .PredValidF,
           // update
           .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
           .PCE,
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 8eba026ec..839b1b7d5 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -38,8 +38,8 @@ module btb
    input  logic             StallF, StallE, StallM, FlushM,
    input  logic [`XLEN-1:0] PCNextF,
    output logic [`XLEN-1:0] BTBPredPCF,
-   output logic [3:0]       InstrClass,
-   output logic             Valid,
+   output logic [3:0]       PredInstrClassF,
+   output logic             PredValidF,
    // update
    input  logic             UpdateEN,
    input  logic [`XLEN-1:0] PCE,
@@ -72,13 +72,13 @@ module btb
     end else if (UpdateEN & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
     end
-	Valid = ValidBits[PCNextFIndex];
+	PredValidF = ValidBits[PCNextFIndex];
   end
 
   // An optimization may be using a PC relative address.
   // *** need to add forwarding.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
-    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
+    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
 
 endmodule

From d4004c2c22d3674509020db29d48a0ef4c433f1b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 13:02:20 -0600
Subject: [PATCH 15/84] Added logic to forward btb prediction results.

---
 pipelined/src/ifu/brpred/btb.sv | 42 ++++++++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 839b1b7d5..bcf5dcfd9 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -35,8 +35,8 @@ module btb
     )
   (input  logic             clk,
    input  logic             reset,
-   input  logic             StallF, StallE, StallM, FlushM,
-   input  logic [`XLEN-1:0] PCNextF,
+   input  logic             StallF, StallD, StallE, StallM, FlushD, FlushM,
+   input  logic [`XLEN-1:0] PCNextF, PCF, PCD,
    output logic [`XLEN-1:0] BTBPredPCF,
    output logic [3:0]       PredInstrClassF,
    output logic             PredValidF,
@@ -50,22 +50,44 @@ module btb
 
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
-  logic [Depth-1:0]         PCNextFIndex, PCEIndex;
+  logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
   logic                     UpdateENQ;
   logic [`XLEN-1:0] 		ResetPC;
-
-
+  logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
+  logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [`XLEN+3:0] 		TableBTBPredictionF;
+  logic [`XLEN-1:0] 		BTBPredPCD;  
+  logic [3:0] 				PredInstrClassD;  // copy of reg outside module
+  
+  
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
   // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
   // using compressed instructions.  XOR bit 1 with the MSB of index.
+  assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
+  assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
   assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
 
   // must output a valid PC and valid bit during reset.  Because the PCNextF logic of the IFU and trap units
   // does not mux in RESET_VECTOR we have to do it here.  This is a performance optimization.
   assign ResetPC = `RESET_VECTOR;
-  assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
+  assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; 
+
+  assign MatchF = PCNextFIndex == PCFIndex;
+  assign MatchD = PCNextFIndex == PCDIndex;
+  assign MatchE = PCNextFIndex == PCEIndex;
+  assign MatchNextX = MatchF | MatchD | MatchE;
   
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, BTBPredPCF} :
+                                MatchD ? {PredInstrClassD, BTBPredPCD} :
+                                {InstrClassE, IEUAdrE} ;
+
+  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
+
+  assign {PredInstrClassF, BTBPredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
+
   always_ff @ (posedge clk) begin
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
@@ -76,9 +98,13 @@ module btb
   end
 
   // An optimization may be using a PC relative address.
-  // *** need to add forwarding.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
-    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}),
+    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
 
+  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD});
+
+
+  
+
 endmodule

From bb89bf82bfd08a6ed87457db7915ce9087a51bf4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 15:16:53 -0600
Subject: [PATCH 16/84] Fixed subtle bug in btb.

---
 pipelined/src/ifu/brpred/bpred.sv | 1 -
 pipelined/src/ifu/brpred/btb.sv   | 5 ++---
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index dd7b9e850..485875b66 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -146,7 +146,6 @@ module bpred (
           .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
           .PCE,
           .IEUAdrE,
-          .UpdateInvalid(PredictionInstrClassWrongE),
           .InstrClassE);
 
   // Part 3 RAS
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index bcf5dcfd9..aba3826b3 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -44,8 +44,7 @@ module btb
    input  logic             UpdateEN,
    input  logic [`XLEN-1:0] PCE,
    input  logic [`XLEN-1:0] IEUAdrE,
-   input  logic [3:0]       InstrClassE,
-   input  logic             UpdateInvalid
+   input  logic [3:0]       InstrClassE
    );
 
   localparam TotalDepth = 2 ** Depth;
@@ -92,7 +91,7 @@ module btb
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
     end else if (UpdateEN & ~StallM & ~FlushM) begin
-      ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
+      ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
 	PredValidF = ValidBits[PCNextFIndex];
   end

From 3d285312f03ccb4fcc7e13ac15ffcee5a401967c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 15:29:55 -0600
Subject: [PATCH 17/84] Cleaned up branch predictor.

---
 pipelined/src/ifu/brpred/bpred.sv |  3 +--
 pipelined/src/ifu/brpred/btb.sv   | 14 ++++++--------
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 485875b66..d259b3b3d 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -142,8 +142,7 @@ module bpred (
           .BTBPredPCF,
           .PredInstrClassF,
           .PredValidF,
-          // update
-          .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
+          .PredictionInstrClassWrongE,
           .PCE,
           .IEUAdrE,
           .InstrClassE);
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index aba3826b3..fdac1c54d 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -41,7 +41,7 @@ module btb
    output logic [3:0]       PredInstrClassF,
    output logic             PredValidF,
    // update
-   input  logic             UpdateEN,
+   input  logic             PredictionInstrClassWrongE,
    input  logic [`XLEN-1:0] PCE,
    input  logic [`XLEN-1:0] IEUAdrE,
    input  logic [3:0]       InstrClassE
@@ -50,7 +50,6 @@ module btb
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
-  logic                     UpdateENQ;
   logic [`XLEN-1:0] 		ResetPC;
   logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
   logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
@@ -67,8 +66,10 @@ module btb
   assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
   assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
 
-  // must output a valid PC and valid bit during reset.  Because the PCNextF logic of the IFU and trap units
-  // does not mux in RESET_VECTOR we have to do it here.  This is a performance optimization.
+  // must output a valid PC and valid bit during reset.  Because only PCF, not PCNextF is reset, PCNextF is invalid
+  // during reset.  The BTB must produce a non X PC1NextF to allow the simulation to run.
+  // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus.
+  // For now it is optimal to leave it here.
   assign ResetPC = `RESET_VECTOR;
   assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; 
 
@@ -90,7 +91,7 @@ module btb
   always_ff @ (posedge clk) begin
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
-    end else if (UpdateEN & ~StallM & ~FlushM) begin
+    end else if ((|InstrClassE | PredictionInstrClassWrongE) & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
 	PredValidF = ValidBits[PCNextFIndex];
@@ -103,7 +104,4 @@ module btb
 
   flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD});
 
-
-  
-
 endmodule

From 56aa798d5c2a131c24afcf19b9d6ecd2099500a8 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 16:03:02 -0600
Subject: [PATCH 18/84] More branch predictor improvements.

---
 pipelined/src/ifu/brpred/bpred.sv             | 17 +++--
 pipelined/src/ifu/brpred/btb.sv               | 39 ++++++------
 .../ifu/brpred/speculativeglobalhistory.sv    | 62 ++++++++++---------
 pipelined/src/ifu/brpred/speculativegshare.sv |  8 +--
 4 files changed, 60 insertions(+), 66 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index d259b3b3d..35dffa964 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -64,7 +64,7 @@ module bpred (
   logic [1:0]               DirPredictionF;
 
   logic [3:0]               PredInstrClassF, PredInstrClassD, PredInstrClassE;
-  logic [`XLEN-1:0]         BTBPredPCF, RASPCF;
+  logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     TargetWrongE;
   logic                     FallThroughWrongE;
   logic                     PredictionPCWrongE;
@@ -95,8 +95,8 @@ module bpred (
     speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
-      .BranchInstrW(InstrClassW[0]), .PCSrcE);
-    
+      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
+	    
   end else if (`BPTYPE == "BPGSHARE") begin:Predictor
     gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
@@ -135,15 +135,12 @@ module bpred (
   // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
 
-  btb TargetPredictor(.clk(clk),
-          .reset(reset),
-          .*, // Stalls and flushes
-          .PCNextF,
-          .BTBPredPCF,
+  btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
+          .PCNextF, .PCF, .PCD, .PCE,
+          .PredPCF,
           .PredInstrClassF,
           .PredValidF,
           .PredictionInstrClassWrongE,
-          .PCE,
           .IEUAdrE,
           .InstrClassE);
 
@@ -160,7 +157,7 @@ module bpred (
        .incr(1'b0),
        .PCLinkE);
 
-  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF;
+  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
   // the branch predictor needs a compact decoding of the instruction class.
   assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index fdac1c54d..a81af5bb4 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -35,16 +35,15 @@ module btb
     )
   (input  logic             clk,
    input  logic             reset,
-   input  logic             StallF, StallD, StallE, StallM, FlushD, FlushM,
-   input  logic [`XLEN-1:0] PCNextF, PCF, PCD,
-   output logic [`XLEN-1:0] BTBPredPCF,
-   output logic [3:0]       PredInstrClassF,
-   output logic             PredValidF,
+   input  logic             StallF, StallD, StallM, FlushD, FlushM,
+   input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
+   output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
+   output logic [3:0]       PredInstrClassF,                        // BTB's guess at instruction class
+   output logic             PredValidF,                             // BTB's guess is valid
    // update
-   input  logic             PredictionInstrClassWrongE,
-   input  logic [`XLEN-1:0] PCE,
-   input  logic [`XLEN-1:0] IEUAdrE,
-   input  logic [3:0]       InstrClassE
+   input  logic             PredictionInstrClassWrongE,             // BTB's instruction class guess was wrong
+   input  logic [`XLEN-1:0] IEUAdrE,                                // Branch/jump target address to insert into btb
+   input  logic [3:0]       InstrClassE                             // Instruction class to insert into btb
    );
 
   localparam TotalDepth = 2 ** Depth;
@@ -54,10 +53,10 @@ module btb
   logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
   logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
   logic [`XLEN+3:0] 		TableBTBPredictionF;
-  logic [`XLEN-1:0] 		BTBPredPCD;  
-  logic [3:0] 				PredInstrClassD;  // copy of reg outside module
-  
-  
+  logic [`XLEN-1:0] 		PredPCD;  
+  logic [3:0] 				PredInstrClassD;  // *** copy of reg outside module
+  logic 					UpdateEn;
+    
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
   // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
@@ -80,28 +79,30 @@ module btb
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
-  assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, BTBPredPCF} :
-                                MatchD ? {PredInstrClassD, BTBPredPCD} :
+  assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} :
+                                MatchD ? {PredInstrClassD, PredPCD} :
                                 {InstrClassE, IEUAdrE} ;
 
   flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
-  assign {PredInstrClassF, BTBPredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
+  assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
 
   always_ff @ (posedge clk) begin
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
-    end else if ((|InstrClassE | PredictionInstrClassWrongE) & ~StallM & ~FlushM) begin
+    end else if ((UpdateEn) & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
 	PredValidF = ValidBits[PCNextFIndex];
   end
 
+  assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
+
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
-     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
+     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
-  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD});
+  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
 
 endmodule
diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
index 094adca99..ecc7a3b0f 100644
--- a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
+++ b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv
@@ -40,52 +40,56 @@ module speculativeglobalhistory
    output logic            DirPredictionWrongE,
    // update
    input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
+   input logic [3:0]       WrongPredInstrClassD, 
    input logic             PCSrcE
    );
 
-  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
+  logic                    MatchF, MatchD, MatchE;
   logic                    MatchNextX, MatchXF;
 
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
   logic [k-1:0]            GHRF;
   logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
   logic [k-1:0]            GHRNextF;
-  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
-  logic                    PCSrcM, PCSrcW;
+  logic [k:-1] 			   GHRNextD, OldGHRD;
+  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
+  logic [k-1:0]            IndexNextF, IndexF;
+  logic [k-1:0]            IndexD, IndexE;
+  
   logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
+  assign IndexNextF = GHRNextF;
+  assign IndexF = GHRF;
+  assign IndexD = GHRD[k-1:0];
+  assign IndexE = GHRE[k-1:0];
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
-    .ra1(GHRNextF),
+    .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
+    .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
-    .wa2(GHRW[k-1:0]),
-    .wd2(NewDirPredictionW),
-    .we2(BranchInstrW & ~StallW & ~FlushW),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
-  //  and then register for use in the Fetch stage.
-  assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF);
-  assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]);
-  assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]);
-  assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]);
-  assign MatchW = BranchInstrW & (GHRNextF == GHRW[k-1:0]);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
+  // and then register for use in the Fetch stage.
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchNextX = MatchF | MatchD | MatchE;
 
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
                                    MatchD ? NewDirPredictionD :
-                                   MatchE ? NewDirPredictionE :
-                                   MatchM ? NewDirPredictionM :
-                                   NewDirPredictionW;
-
+                                   NewDirPredictionE ;
+  
   flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
 
   assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
@@ -95,16 +99,11 @@ module speculativeglobalhistory
   flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
 
   // New prediction pipeline
-  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
+  assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]};
+  
   flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
-  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
 
-  // PCSrc pipeline
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
-  
   // GHR pipeline
   assign GHRNextF = FlushD ?  GHRNextD[k:1] :
                     BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
@@ -112,8 +111,11 @@ module speculativeglobalhistory
 
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
   
-  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
-  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
+  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
+  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
+				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
+				OldGHRD[k:0];
 
   assign GHRNextE = FlushE ? GHRNextM : GHRD;
   flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 489024491..b72aacb44 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -49,7 +49,7 @@ module speculativegshare
   logic                    MatchNextX, MatchXF;
 
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
   logic [k-1:0]            GHRF;
   logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
@@ -59,7 +59,6 @@ module speculativegshare
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE;
   
-  logic                    PCSrcM, PCSrcW;
   logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
@@ -104,12 +103,7 @@ module speculativegshare
   
   flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
 
-  // PCSrc pipeline
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
-  
   // GHR pipeline
   assign GHRNextF = FlushD ?  GHRNextD[k:1] :
                     BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :

From 172c40d44b9ffb2e890a8548884c911b803e6a16 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 17:06:25 -0600
Subject: [PATCH 19/84] Improved RAS.

---
 pipelined/config/rv64gc/wally-config.vh   |  7 ++++---
 pipelined/src/ifu/brpred/RAsPredictor.sv  | 16 ++++++++++------
 pipelined/src/ifu/brpred/bpred.sv         | 21 +++++++++++----------
 pipelined/src/ifu/brpred/globalhistory.sv |  9 ++++-----
 pipelined/src/ifu/brpred/gshare.sv        | 15 +++++++--------
 5 files changed, 36 insertions(+), 32 deletions(-)

diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index 29148944f..6ecab2845 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -135,9 +135,10 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_ENABLED 1
-//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+//`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+//`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
index c71ff2966..422a785cc 100644
--- a/pipelined/src/ifu/brpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/brpred/RAsPredictor.sv
@@ -32,13 +32,10 @@ module RASPredictor
   #(parameter int StackSize = 16
     )
   (input logic              clk,
-   input logic 				reset,
-   input logic 				PopF,
+   input logic 				reset, StallF, StallD, StallE,
    output logic [`XLEN-1:0] RASPCF,
    input logic [3:0] 		WrongPredInstrClassD,
-   input logic [3:0] 		InstrClassD,
-   input logic 				PushE,
-   input logic 				incr,
+   input logic [3:0] 		InstrClassD, InstrClassE, PredInstrClassF,
    input logic [`XLEN-1:0] 	PCLinkE
    );
 
@@ -51,8 +48,15 @@ module RASPredictor
   logic [Depth-1:0]         PtrD, PtrQ, PtrP1, PtrM1;
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
+  logic 		 PopF;
+  logic 		 PushE;
   
-  assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2];
+  
+
+  assign PopF = PredInstrClassF[2] & ~StallF;
+  assign PushE = InstrClassE[3] & ~StallE;
+    
+  assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
 
   assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
 
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 35dffa964..1669ee4f3 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -99,7 +99,7 @@ module bpred (
 	    
   end else if (`BPTYPE == "BPGSHARE") begin:Predictor
     gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
@@ -147,15 +147,9 @@ module bpred (
   // Part 3 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
   // *** needs to include flushX
-  RASPredictor RASPredictor(.clk(clk),
-       .reset(reset),
-       .PopF(PredInstrClassF[2] & ~StallF),
-							.WrongPredInstrClassD,
-							.InstrClassD,
-       .RASPCF,
-       .PushE(InstrClassE[3] & ~StallE),
-       .incr(1'b0),
-       .PCLinkE);
+  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, 
+							.PredInstrClassF, .InstrClassD, .InstrClassE,
+							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
 
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
@@ -227,5 +221,12 @@ module bpred (
   //  end else begin
   //	assign NextValidPCE = PCE;
   //  end
+
+  // performance counters
+  // 1. class         (class wrong / minstret)
+  // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
+  // 3. target ras    (ras target wrong / class[2])
+  // 4. direction     (br dir wrong / class[0])
+
   
 endmodule
diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv
index 7aa86dbb9..55b6827cd 100644
--- a/pipelined/src/ifu/brpred/globalhistory.sv
+++ b/pipelined/src/ifu/brpred/globalhistory.sv
@@ -46,7 +46,7 @@ module globalhistory
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
   
@@ -55,9 +55,9 @@ module globalhistory
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(GHR),
     .rd1(DirPredictionF),
-    .wa2(GHRM),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallM & ~FlushM),
+    .wa2(GHRE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -76,7 +76,6 @@ module globalhistory
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
 
 
 endmodule
diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv
index ce189d268..ff24c84d3 100644
--- a/pipelined/src/ifu/brpred/gshare.sv
+++ b/pipelined/src/ifu/brpred/gshare.sv
@@ -39,28 +39,28 @@ module gshare
    output logic [1:0]      DirPredictionF, 
    output logic            DirPredictionWrongE,
    // update
-   input logic [`XLEN-1:0] PCNextF, PCM,
+   input logic [`XLEN-1:0] PCNextF, PCE,
    input logic             BranchInstrE, BranchInstrM, PCSrcE
    );
 
-  logic [k-1:0]            IndexNextF, IndexM;
+  logic [k-1:0]            IndexNextF, IndexE;
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
   assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),
-    .wa2(IndexM),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallM & ~FlushM),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -78,7 +78,6 @@ module gshare
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
 
 
 endmodule

From 0b9f78763530119556672c8f2ab2d4f730d5b57c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 17:10:52 -0600
Subject: [PATCH 20/84] Improved RAS again.

---
 pipelined/regression/wave.do             | 83 ++++++++++--------------
 pipelined/src/ifu/brpred/RAsPredictor.sv | 15 ++---
 pipelined/src/ifu/brpred/bpred.sv        |  2 +-
 3 files changed, 44 insertions(+), 56 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index be29ed870..393f6ee11 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -41,12 +41,12 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
-add wave -noupdate -expand -group PCS /testbench/PCW
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/core/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
+add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
@@ -55,15 +55,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
-add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
+add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
+add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
+add wave -noupdate -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
@@ -85,25 +85,18 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
@@ -148,20 +141,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
-add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq
-add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
-add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
-add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
-add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
 add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
@@ -463,10 +451,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
 add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
 add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
 add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
 add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
@@ -484,7 +468,6 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
 add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
 add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
-add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
@@ -571,7 +554,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
@@ -603,8 +585,15 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -620,4 +609,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {118528 ns} {128752 ns}
+WaveRestoreZoom {79760 ns} {171462 ns}
diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
index 422a785cc..28d15ebbe 100644
--- a/pipelined/src/ifu/brpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/brpred/RAsPredictor.sv
@@ -32,15 +32,13 @@ module RASPredictor
   #(parameter int StackSize = 16
     )
   (input logic              clk,
-   input logic 				reset, StallF, StallD, StallE,
+   input logic 				reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
    output logic [`XLEN-1:0] RASPCF,
    input logic [3:0] 		WrongPredInstrClassD,
    input logic [3:0] 		InstrClassD, InstrClassE, PredInstrClassF,
    input logic [`XLEN-1:0] 	PCLinkE
    );
 
-  // *** need to update so it either doesn't push until the memory stage
-  // or need to repair flushed push.
   // *** need to repair popped and then flushed returns.
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
@@ -50,19 +48,20 @@ module RASPredictor
   integer        index;
   logic 		 PopF;
   logic 		 PushE;
+  logic 		 RepairD;
   
   
 
-  assign PopF = PredInstrClassF[2] & ~StallF;
-  assign PushE = InstrClassE[3] & ~StallE;
+  assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
+  assign RepairD = InstrClassD[2] & ~StallE & ~FlushE;
+  assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
     
   assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
 
-  assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
+  assign PtrD = PopF | RepairD ? PtrM1 : PtrP1;
 
   assign PtrM1 = PtrQ - 1'b1;
   assign PtrP1 = PtrQ + 1'b1;
-  // may have to handle a PushE and an incr at the same time.
   // *** what happens if jal is executing and there is a return being flushed in Decode?
 
   flopenr #(Depth) PTR(.clk(clk),
@@ -75,7 +74,7 @@ module RASPredictor
   always_ff @ (posedge clk) begin
     if(reset) begin
       for(index=0; index<StackSize; index++)
- memory[index] <= {`XLEN{1'b0}};
+		memory[index] <= {`XLEN{1'b0}};
     end else if(PushE) begin
       memory[PtrP1] <= #1 PCLinkE;
     end
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 1669ee4f3..d9f342db1 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -147,7 +147,7 @@ module bpred (
   // Part 3 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
   // *** needs to include flushX
-  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, 
+  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
 							.PredInstrClassF, .InstrClassD, .InstrClassE,
 							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
 

From e1d0be5c61472e2abf27c3232f6efc3b0f47b9ad Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 17:18:07 -0600
Subject: [PATCH 21/84] RAS is now compliant with our header and documentation
 guide.

---
 pipelined/src/ifu/brpred/RAsPredictor.sv | 40 +++++++++++++-----------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
index 28d15ebbe..42c484393 100644
--- a/pipelined/src/ifu/brpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/brpred/RAsPredictor.sv
@@ -1,13 +1,14 @@
 ///////////////////////////////////////////
 // RASPredictor.sv
 //
-// Written: Ross Thomposn
-// Email: ross1728@gmail.com
-// Created: February 15, 2021
-// Modified: 
+// Written: Ross Thomposn ross1728@gmail.com
+// Created: 15 February 2021
+// Modified: 25 January 2023
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -28,41 +29,42 @@
 
 `include "wally-config.vh"
 
-module RASPredictor
-  #(parameter int StackSize = 16
-    )
-  (input logic              clk,
-   input logic 				reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
-   output logic [`XLEN-1:0] RASPCF,
-   input logic [3:0] 		WrongPredInstrClassD,
-   input logic [3:0] 		InstrClassD, InstrClassE, PredInstrClassF,
-   input logic [`XLEN-1:0] 	PCLinkE
+module RASPredictor #(parameter int StackSize = 16
+)(input  logic             clk,
+  input  logic 			   reset, 
+  input  logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input  logic [3:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
+  input  logic [3:0] 	   InstrClassD, InstrClassE, PredInstrClassF, // Instr class
+  input  logic [`XLEN-1:0] PCLinkE,                                   // PC of instruction after a jal
+  output logic [`XLEN-1:0] RASPCF                                     // Top of the stack
    );
 
-  // *** need to repair popped and then flushed returns.
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
   logic [Depth-1:0]         PtrD, PtrQ, PtrP1, PtrM1;
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
+
   logic 		 PopF;
   logic 		 PushE;
   logic 		 RepairD;
+  logic 		 PossibleRepairD;
   
+  logic 		 DecrementPtr;
   
-
   assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
-  assign RepairD = InstrClassD[2] & ~StallE & ~FlushE;
+  assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE;
+  assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE;
   assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
     
-  assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
+  assign CounterEn = PopF | PushE | RepairD;
 
-  assign PtrD = PopF | RepairD ? PtrM1 : PtrP1;
+  assign DecrementPtr = PopF | PossibleRepairD;
+  mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD);
 
   assign PtrM1 = PtrQ - 1'b1;
   assign PtrP1 = PtrQ + 1'b1;
-  // *** what happens if jal is executing and there is a return being flushed in Decode?
 
   flopenr #(Depth) PTR(.clk(clk),
       .reset(reset),

From 4e858199e5aa5d50706dafcdb3f8352c83352a0c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 18:51:09 -0600
Subject: [PATCH 22/84] Fixed typos.

---
 pipelined/src/ifu/brpred/bpred.sv | 6 +++---
 pipelined/src/ifu/ifu.sv          | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index d9f342db1..6803f65d4 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -197,8 +197,8 @@ module bpred (
   assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
 
   // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
-  assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1]) & PredictionPCWrongE;
-  // similar with RAS
+  assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
+  // similar with RAS. Over counts ras if the class prediction was wrong.
   assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE;
   // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
   assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
@@ -223,7 +223,7 @@ module bpred (
   //  end
 
   // performance counters
-  // 1. class         (class wrong / minstret)
+  // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)
   // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
   // 3. target ras    (ras target wrong / class[2])
   // 4. direction     (br dir wrong / class[0])
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 476f666ff..f48727500 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -115,7 +115,7 @@ module ifu (
   logic [31:0] NextInstrD, NextInstrE;                                // Instruction into the next stage after possible stage flush
 
 
-  logic 					   CacheableF;                            // PMA indicates isntruction address is cacheable
+  logic 					   CacheableF;                            // PMA indicates instruction address is cacheable
   logic 					   SelNextSpillF;                         // In a spill, stall pipeline and gate local stallF
   logic 					   BusStall;                              // Bus interface busy with multicycle operation
   logic 					   ICacheStallF;                          // I$ busy with multicycle operation

From 43d4ac1c7b67da024a71bda064e9838d8f22cc05 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 19:39:18 -0600
Subject: [PATCH 23/84] Intermediate commit. Passes regression tests, but RAS
 is not correct.

---
 pipelined/regression/wave.do             | 47 ++++++------------------
 pipelined/src/ifu/brpred/RAsPredictor.sv |  3 +-
 pipelined/src/ifu/brpred/bpred.sv        | 40 ++++++++++++++++++--
 pipelined/src/ifu/brpred/btb.sv          |  8 ++--
 pipelined/src/ifu/ifu.sv                 |  2 +-
 5 files changed, 55 insertions(+), 45 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index 393f6ee11..ccc5928a5 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -55,11 +55,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
-add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
 add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
 add wave -noupdate -group {Memory Stage} /testbench/InstrMName
@@ -85,11 +85,8 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
 add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
 add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
@@ -566,34 +563,12 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -609,4 +584,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {79760 ns} {171462 ns}
+WaveRestoreZoom {117047 ns} {117181 ns}
diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
index 42c484393..6f2cbd059 100644
--- a/pipelined/src/ifu/brpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/brpred/RAsPredictor.sv
@@ -54,7 +54,8 @@ module RASPredictor #(parameter int StackSize = 16
   logic 		 DecrementPtr;
   
   assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
-  assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE;
+  // **********this part is wrong.
+  assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD);
   assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE;
   assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
     
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 6803f65d4..82bdf1f00 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,6 +28,8 @@
 
 `include "wally-config.vh"
 
+`define INSTR_CLASS_PRED 0
+
 module bpred (
    input logic              clk, reset,
    input logic              StallF, StallD, StallE, StallM, StallW,
@@ -46,6 +48,8 @@ module bpred (
    input logic [`XLEN-1:0]  PCE,                       // Execution stage instruction address
    input logic [`XLEN-1:0]  PCM,                       // Memory stage instruction address
 
+   input logic [31:0]       PostSpillInstrRawF,        // Instruction
+
    // Branch and jump outcome
    input logic              PCSrcE,                    // Executation stage branch is taken
    input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
@@ -63,13 +67,13 @@ module bpred (
   logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
-  logic [3:0]               PredInstrClassF, PredInstrClassD, PredInstrClassE;
+  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
   logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     TargetWrongE;
   logic                     FallThroughWrongE;
   logic                     PredictionPCWrongE;
   logic                     PredictionInstrClassWrongE;
-  logic [3:0]               InstrClassD, InstrClassE, InstrClassW;
+  logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
   logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   
   logic                     SelBPPredF;
@@ -138,7 +142,7 @@ module bpred (
   btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
           .PCNextF, .PCF, .PCD, .PCE,
           .PredPCF,
-          .PredInstrClassF,
+          .BTBPredInstrClassF,
           .PredValidF,
           .PredictionInstrClassWrongE,
           .IEUAdrE,
@@ -154,6 +158,36 @@ module bpred (
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
   // the branch predictor needs a compact decoding of the instruction class.
+  if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
+	logic [4:0] CompressedOpcF;
+	logic [3:0] InstrClassF;
+	logic 		cjal, cj, cjr, cjalr;
+	
+	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
+
+	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
+	assign cj = CompressedOpcF == 5'h0d;
+	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	
+	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
+							(`C_SUPPORTED & CompressedOpcF == 5'h0e);
+	
+	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
+							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
+	
+	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
+							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+	
+	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
+							(`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01));
+	assign PredInstrClassF = InstrClassF;
+  end else begin
+	assign PredInstrClassF = BTBPredInstrClassF;
+  end
+  
+
   assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
   assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
   assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index a81af5bb4..9b6c66b85 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -38,7 +38,7 @@ module btb
    input  logic             StallF, StallD, StallM, FlushD, FlushM,
    input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
    output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
-   output logic [3:0]       PredInstrClassF,                        // BTB's guess at instruction class
+   output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
    output logic             PredValidF,                             // BTB's guess is valid
    // update
    input  logic             PredictionInstrClassWrongE,             // BTB's instruction class guess was wrong
@@ -79,13 +79,13 @@ module btb
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
-  assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} :
+  assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
                                 MatchD ? {PredInstrClassD, PredPCD} :
                                 {InstrClassE, IEUAdrE} ;
 
   flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
-  assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
+  assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
 
   always_ff @ (posedge clk) begin
     if (reset) begin
@@ -103,6 +103,6 @@ module btb
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
-  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
+  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
 
 endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index f48727500..26227bb9b 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -327,7 +327,7 @@ module ifu (
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
+                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
 
   end else begin : bpred

From 6ece31183c4c6bedb2bda7e8e6ef02aafd2df92c Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Thu, 26 Jan 2023 06:58:15 +0200
Subject: [PATCH 24/84] Fixed config file writing for synthesis (#29)

* Fixed writing config files for synth sweeps

* cleaned up comments
---
 .gitignore                |  2 +-
 synthDC/Makefile          | 72 ++++++++++++++++++++-------------------
 synthDC/extractSummary.py | 54 ++++++++++++++---------------
 synthDC/wallySynth.py     | 31 ++++++-----------
 4 files changed, 76 insertions(+), 83 deletions(-)

diff --git a/.gitignore b/.gitignore
index c4c71a623..609ef1487 100644
--- a/.gitignore
+++ b/.gitignore
@@ -76,7 +76,7 @@ synthDC/runs/
 synthDC/newRuns
 synthDC/ppa/PPAruns
 synthDC/ppa/plots
-synthDC/plots/
+synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
 /pipelined/regression/power.saif
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 98b719428..81d982251 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -8,6 +8,7 @@ NAME := synth
 export DESIGN ?= wallypipelinedcore
 export FREQ ?= 3000
 export CONFIG ?= rv32e
+export MOD ?= orig
 # title to add a note in the synth's directory name
 TITLE = 
 # tsmc28, sky130, and sky90 presently supported
@@ -22,13 +23,15 @@ export DRIVE ?= FLOP
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
+export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
-CONFIGDIR ?= ${WALLY}/pipelined/config
+configAsList := $(subst _, ,$(CONFIG))
+BASECONFIG := $(word 1, $(configAsList))
+OLDCONFIGDIR ?= ${WALLY}/pipelined/config
+CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
 CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
 CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
-# FREQS = 25 50 100 150 200 250 300 350 400
 # k = 3 6 
 
 print:
@@ -42,8 +45,8 @@ default:
 	@echo "Use wallySynth.py to run a concurrent sweep "
 
 
-DIRS32 = rv32e rv32gc rv32ic 
-DIRS64 = rv64ic rv64gc
+DIRS32 = rv32e rv32gc rv32ic rv32i
+DIRS64 = rv64i rv64gc
 DIRS = $(DIRS32) $(DIRS64)
 
 # bpred:
@@ -51,73 +54,72 @@ DIRS = $(DIRS32) $(DIRS64)
 # 	@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
 # 	@$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
 # 	@$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
-copy: 
-	# remove old config files
-	rm -rf $(CONFIGDIR)/*_*
 
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
-	@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
-	@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
-	@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
-	@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
+configs: $(BASECONFIG)
+$(BASECONFIG):
+	@echo $(BASECONFIG)
+	cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig
+	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
+	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
+	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
 
-	@$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
-	@$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
-
-configs: $(DIRS)
-$(DIRS):
+ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),)
+	sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
+else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),)
+	sed -i "s/RAM_RANGE.*/RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
+else 
+	$(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64))
+	@echo "Config not in list, RAM_RANGE will be unmodified"
+endif
 	
 	# turn off FPU 
-	rm -rf $(CONFIGDIR)/$@_FPUoff
 	cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff
 	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
 	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
 
 	# PMP 16 
-	rm -rf $(CONFIGDIR)/$@_PMP16
 	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16
 	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh
 	
 	# PMP 0
-	rm -rf $(CONFIGDIR)/$@_PMP0
 	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
 	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
 	
 	# no muldiv
-	rm -rf $(CONFIGDIR)/$@_noMulDiv
 	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
 	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
 
 	# no priv
-	rm -rf $(CONFIGDIR)/$@_noPriv
 	cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
+ifeq ($(SAIFPOWER), 1)
+	cp -f ../pipelined/regression/power.saif .
+endif
+
 freqs: 
 	@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
 
-synth:
+mkdirecs:
 	@echo "DC Synthesis"
 	@mkdir -p $(OUTPUTDIR)
-	@mkdir -p $(OUTPUTDIR)/hdl
+	@mkdir -p $(OUTPUTDIR)/hdl/config
 	@mkdir -p $(OUTPUTDIR)/reports
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
-ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
-endif
+
+synth: mkdirecs configs rundc clean
+
+rundc:
 	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
-#	rm -rf $(OUTPUTDIR)/hdl
+	
+clean:
+	rm -rf $(OUTPUTDIR)/hdl
 	rm -rf $(OUTPUTDIR)/WORK
 	rm -rf $(OUTPUTDIR)/alib-52
-
-clean:
 	rm -f default.svf
 	rm -f command.log
 	rm -f filenames*.log
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
-	rm -f crte_*.txt
-
-fresh: clean copy configs
-	@echo "synth directory cleaned and fresh config files written"
+	rm -f crte_*.txt
\ No newline at end of file
diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index 978365b16..430f86178 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -28,16 +28,16 @@ def synthsintocsv():
 
     file = open("Summary.csv", "w")
     writer = csv.writer(file)
-    writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area'])
+    writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
 
     for oneSynth in allSynths:
         descrip = specReg.findall(oneSynth)
         width = descrip[2][:4]
         config = descrip[2][4:]
         if descrip[3][-2:] == 'nm':
-            special = ''
+            mod = ''
         else:
-            special = descrip[3]
+            mod = descrip[3]
             descrip = descrip[1:]
         tech = descrip[3][:-2]
         freq = descrip[4]
@@ -57,12 +57,12 @@ def synthsintocsv():
         else:
             delay = 1000/int(freq) - metrics[0]
             area = metrics[1]
-            writer.writerow([width, config, special, tech, freq, delay, area])
+            writer.writerow([width, config, mod, tech, freq, delay, area])
     file.close()
 
 	
 def synthsfromcsv(filename):
-    Synth = namedtuple("Synth", "width config special tech freq delay area")
+    Synth = namedtuple("Synth", "width config mod tech freq delay area")
     with open(filename, newline='') as csvfile:
         csvreader = csv.reader(csvfile)
         global allSynths
@@ -81,14 +81,9 @@ def freqPlot(tech, width, config):
     ''' plots delay, area for syntheses with specified tech, module, width
     '''
 
-    current_directory = os.getcwd()
-    final_directory = os.path.join(current_directory, 'plots/wally')
-    if not os.path.exists(final_directory):
-        os.makedirs(final_directory)
-
     freqsL, delaysL, areasL = ([[], []] for i in range(3))
     for oneSynth in allSynths:
-        if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special):
+        if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod):
             ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
             freqsL[ind] += [oneSynth.freq]
             delaysL[ind] += [oneSynth.delay]
@@ -130,7 +125,7 @@ def freqPlot(tech, width, config):
     ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
     addFO4axis(fig, ax1, tech)
 
-    plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png')
+    plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png')
 
 
 def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
@@ -168,7 +163,7 @@ def plotFeatures(tech, width, config):
             if (oneSynth.config == config) & (width == oneSynth.width):
                 delays += [oneSynth.delay]
                 areas += [oneSynth.area]
-                labels += [oneSynth.special]
+                labels += [oneSynth.mod]
 
     fig, (ax) = plt.subplots(1, 1)
 
@@ -176,28 +171,28 @@ def plotFeatures(tech, width, config):
 
     titlestr = tech+'_'+width+config
     plt.title(titlestr)
-    plt.savefig('./plots/wally/features_'+titlestr+'.png')
+    plt.savefig(final_directory + '/features_'+titlestr+'.png')
 
 	
-def plotConfigs(tech, special=''):
+def plotConfigs(tech, mod=''):
     delays, areas, labels = ([] for i in range(3))
     freq = techdict[tech].targfreq
     for oneSynth in allSynths:
-        if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special):
-                delays += [oneSynth.delay]
-                areas += [oneSynth.area]
-                labels += [oneSynth.width + oneSynth.config]
+        if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
+            delays += [oneSynth.delay]
+            areas += [oneSynth.area]
+            labels += [oneSynth.width + oneSynth.config]
 
     fig, (ax) = plt.subplots(1, 1)
 
     fig = areaDelay(tech, delays, areas, labels, fig, ax)
 
-    titleStr = tech+'_'+special
+    titleStr = tech+'_'+mod
     plt.title(titleStr)
-    plt.savefig('./plots/wally/configs_' + titleStr + '.png')
+    plt.savefig(final_directory + '/configs_' + titleStr + '.png')
 
 
-def normAreaDelay(special=''):
+def normAreaDelay(mod=''):
     fig, (ax) = plt.subplots(1, 1)
     fullLeg = []
     for tech in list(techdict.keys()):
@@ -205,7 +200,7 @@ def normAreaDelay(special=''):
         spec = techdict[tech]
         freq = spec.targfreq
         for oneSynth in allSynths:
-            if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special):
+            if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
                     delays += [oneSynth.delay]
                     areas += [oneSynth.area]
                     labels += [oneSynth.width + oneSynth.config]
@@ -216,7 +211,7 @@ def normAreaDelay(special=''):
     ax.set_xlabel('Cycle Time (FO4)')
     ax.set_ylabel('Area (add32)')        
     ax.legend(handles = fullLeg, loc='upper left')
-    plt.savefig('./plots/wally/normAreaDelay.png')
+    plt.savefig(final_directory + '/normAreaDelay.png')
 
 	
 def addFO4axis(fig, ax, tech):
@@ -254,12 +249,17 @@ if __name__ == '__main__':
     techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023)
     techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
 
+    current_directory = os.getcwd()
+    final_directory = os.path.join(current_directory, 'wallyplots')
+    if not os.path.exists(final_directory):
+        os.makedirs(final_directory)
+
     synthsintocsv()
     synthsfromcsv('Summary.csv')
     freqPlot('tsmc28', 'rv32', 'e')
     freqPlot('sky90', 'rv32', 'e')
     plotFeatures('sky90', 'rv64', 'gc')
     plotFeatures('tsmc28', 'rv64', 'gc')
-    plotConfigs('sky90', special='orig')
-    plotConfigs('tsmc28', special='orig')
-    normAreaDelay(special='orig')
+    plotConfigs('sky90', mod='orig')
+    plotConfigs('tsmc28', mod='orig')
+    normAreaDelay(mod='orig')
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 0c1579813..6b10f2e8b 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -5,20 +5,14 @@ import subprocess
 from multiprocessing import Pool
 import argparse
 
-def runSynth(config, tech, freq, maxopt):
+def runSynth(config, mod, tech, freq, maxopt):
     global pool
-    command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt)
+    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt)
     pool.map(mask, [command])
 
 def mask(command):
     subprocess.Popen(command, shell=True)
 
-def freshStart():
-    out = subprocess.check_output(['bash','-c', 'make fresh'])
-    for x in out.decode("utf-8").split('\n')[:-1]:
-        print(x)
-    return
-
 
 if __name__ == '__main__':
     
@@ -41,24 +35,21 @@ if __name__ == '__main__':
 
     args = parser.parse_args()
 
-    freq = args.targetfreq if args.targetfreq else 3000
     tech = args.tech if args.tech else 'sky90'
+    defaultfreq = 3000 if tech == 'sky90' else 10000
+    freq = args.targetfreq if args.targetfreq else defaultfreq
     maxopt = int(args.maxopt)
+    mod = 'orig' # until memory integrated
 
     if args.freqsweep:
         sc = args.freqsweep
         config = args.version if args.version else 'rv32e'
-        freshStart()
         for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
-            runSynth(config, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt)
     if args.configsweep:
-        freshStart()
-        for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs
-            config = config + '_orig' # until memory integrated
-            runSynth(config, tech, freq, maxopt)
+        for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs
+            runSynth(config, mod, tech, freq, maxopt)
     if args.featuresweep:
-        freshStart()
-        v = args.version if args.version else 'rv64gc'
-        for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations
-            config = v + '_' + mod
-            runSynth(config, tech, freq, maxopt)
+        config = args.version if args.version else 'rv64gc'
+        for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', 
+            runSynth(config, mod, tech, freq, maxopt)

From 29d4cd7ffa3705f31285bf4e763291481f5aae37 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Jan 2023 23:33:03 -0600
Subject: [PATCH 25/84] Modified the RAS to correctly repair itself.

---
 pipelined/src/ifu/brpred/RAsPredictor.sv | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
index 6f2cbd059..17ebbd1c4 100644
--- a/pipelined/src/ifu/brpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/brpred/RAsPredictor.sv
@@ -49,29 +49,33 @@ module RASPredictor #(parameter int StackSize = 16
   logic 		 PopF;
   logic 		 PushE;
   logic 		 RepairD;
-  logic 		 PossibleRepairD;
+  logic 		 IncrRepairD, DecRepairD;
   
   logic 		 DecrementPtr;
   
   assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
-  // **********this part is wrong.
-  assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD);
-  assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE;
+
+  assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) |  // Wrong class undo increment or decrement.
+				   (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
+				   (~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed
+  
+  assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
+					   (~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed
+					   (WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not
+
+  assign DecRepairD =  (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret.
+  
   assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
     
   assign CounterEn = PopF | PushE | RepairD;
 
-  assign DecrementPtr = PopF | PossibleRepairD;
+  assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
   mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD);
 
   assign PtrM1 = PtrQ - 1'b1;
   assign PtrP1 = PtrQ + 1'b1;
 
-  flopenr #(Depth) PTR(.clk(clk),
-      .reset(reset),
-      .en(CounterEn),
-      .d(PtrD),
-      .q(PtrQ));
+  flopenr #(Depth) PTR(clk, reset, CounterEn, PtrD, PtrQ);
 
   // RAS must be reset. 
   always_ff @ (posedge clk) begin

From 2ee6ffe74b75c7c132003ae5c51dcc528b1c43b1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 26 Jan 2023 10:54:43 -0600
Subject: [PATCH 26/84] Improved no class prediction mode.

---
 pipelined/src/ifu/brpred/bpred.sv | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 82bdf1f00..ff26904ce 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -132,9 +132,6 @@ module bpred (
   // 1) A direction (1 = Taken, 0 = Not Taken)
   // 2) Any information which is necessary for the predictor to build its next state.
   // For a 2 bit table this is the prediction count.
-  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
-         PredInstrClassF[2] |
-         (PredInstrClassF[1] & PredValidF) ;
 
   // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
@@ -183,8 +180,14 @@ module bpred (
 	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
 							(`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01));
 	assign PredInstrClassF = InstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
+						PredInstrClassF[2] |
+						(PredInstrClassF[1]) ;
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
+						PredInstrClassF[2] |
+						(PredInstrClassF[1] & PredValidF) ;
   end
   
 

From 36526734870bd5eaef40a81b1e2d3443bfe8e120 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 26 Jan 2023 11:07:47 -0600
Subject: [PATCH 27/84] Fixed compressed branch class decode.

---
 pipelined/src/ifu/brpred/bpred.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index ff26904ce..b55738ae8 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 0
+`define INSTR_CLASS_PRED 1
 
 module bpred (
    input logic              clk, reset,
@@ -178,7 +178,7 @@ module bpred (
 							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
 	
 	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
-							(`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01));
+							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
 	assign PredInstrClassF = InstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
 						PredInstrClassF[2] |

From e0ca23cdd67788bf44a373660cdd8390fb967db1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 26 Jan 2023 12:19:33 -0600
Subject: [PATCH 28/84] Fixed another bug with the compressed instruction class
 decode.

---
 pipelined/src/ifu/brpred/bpred.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index b55738ae8..38fd39bc3 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 1
+`define INSTR_CLASS_PRED 0
 
 module bpred (
    input logic              clk, reset,
@@ -168,7 +168,7 @@ module bpred (
 	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
 	
 	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
-							(`C_SUPPORTED & CompressedOpcF == 5'h0e);
+							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
 	
 	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
 							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5

From bbb47fc94344a9b9d387045d6669860e9e2513cb Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 26 Jan 2023 13:21:16 -0600
Subject: [PATCH 29/84] Changed the performance counters to track different
 data. Now rather than tracking jump(r) we track jump(r) and taken branches.

---
 pipelined/regression/wave.do              | 35 +++++++++++++++++-----
 pipelined/src/ifu/brpred/bpred.sv         | 36 +++++++++++++++++++++--
 pipelined/src/ifu/ifu.sv                  |  3 +-
 pipelined/src/privileged/csr.sv           |  3 +-
 pipelined/src/privileged/csrc.sv          |  3 +-
 pipelined/src/privileged/privileged.sv    |  3 +-
 pipelined/src/wally/wallypipelinedcore.sv |  5 ++--
 7 files changed, 72 insertions(+), 16 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index ccc5928a5..1e34435a5 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -1,4 +1,5 @@
 onerror {resume}
+quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
@@ -36,11 +37,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
-add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
 add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group PCS /testbench/dut/core/PCF
 add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
@@ -567,8 +568,28 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
+add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -584,4 +605,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {117047 ns} {117181 ns}
+WaveRestoreZoom {48955732 ns} {48955990 ns}
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 38fd39bc3..6af314646 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -55,6 +55,7 @@ module bpred (
    input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
    input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
    output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+   output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
    // Report branch prediction status
    output logic             BPPredWrongE,              // Prediction is wrong
@@ -82,7 +83,18 @@ module bpred (
   logic [`XLEN-1:0]         PCNext0F;
   logic [`XLEN-1:0] 		PCCorrectE;
   logic [3:0] 				WrongPredInstrClassD;
+
+
+//************ new resolve issues  
+  logic BTBTargetWrongE;
+  logic RASTargetWrongE;
+  logic JumpOrTakenBranchE;
   
+  
+
+  logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
+
+
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
   if (`BPTYPE == "BPTWOBIT") begin:Predictor
@@ -200,6 +212,7 @@ module bpred (
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
   flopenrc #(4) InstrClassRegW(clk, reset,  FlushW, ~StallW, InstrClassM, InstrClassW);
   flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
+  flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
 
   // branch predictor
   flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
@@ -234,9 +247,13 @@ module bpred (
   assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
 
   // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
-  assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
+  //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
+  //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE;
+  assign BTBPredPCWrongE = BTBTargetWrongE;
+  
   // similar with RAS. Over counts ras if the class prediction was wrong.
-  assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE;
+  //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE;
+  assign RASPredPCWrongE = RASTargetWrongE;
   // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
   assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
 
@@ -260,10 +277,23 @@ module bpred (
   //  end
 
   // performance counters
-  // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)
+  // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
   // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
   // 3. target ras    (ras target wrong / class[2])
   // 4. direction     (br dir wrong / class[0])
 
+  assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
+  assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
+
+  assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
+  
+  flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
+  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
+
+  flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
+  flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
+
+  
+  
   
 endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 26227bb9b..9be88d568 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -60,6 +60,7 @@ module ifu (
   output logic [`XLEN-1:0] 	PCM,                                      // Memory stage instruction address
   // branch predictor
   output logic [3:0] 		InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic              JumpOrTakenBranchM,
   output logic 				DirPredictionWrongM,                      // Prediction direction is wrong
   output logic 				BTBPredPCWrongM,                          // Prediction target wrong
   output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
@@ -327,7 +328,7 @@ module ifu (
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF,
+                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
 
   end else begin : bpred
diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index d6118e203..9a91d371e 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -62,6 +62,7 @@ module csr #(parameter
   input  logic             RASPredPCWrongM,
   input  logic             PredictionInstrClassWrongM,
   input  logic [3:0]       InstrClassM,
+  input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,
   input  logic             DCacheAccess,
   input  logic             ICacheMiss,
@@ -255,7 +256,7 @@ module csr #(parameter
   if (`ZICOUNTERS_SUPPORTED) begin:counters
     csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
-      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
+      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index de5743858..83e3ccdfe 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -49,6 +49,7 @@ module csrc #(parameter
   input  logic 	            RASPredPCWrongM,
   input  logic 	            PredictionInstrClassWrongM,
   input  logic [3:0]        InstrClassM,
+  input  logic              JumpOrTakenBranchM,                               // actual instruction class
   input  logic 	            DCacheMiss,
   input  logic 	            DCacheAccess,
   input  logic 	            ICacheMiss,
@@ -87,7 +88,7 @@ module csrc #(parameter
     assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;               // Branch predictor wrong direction
     assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
     assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
-    assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions
+    assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM;                // jump or taken branch instructions
     assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
     assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 32ef2eb56..c3f321753 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -51,6 +51,7 @@ module privileged (
   input  logic 		         RASPredPCWrongM,                           // return adddress stack guessed wrong target
   input  logic 		         PredictionInstrClassWrongM,                // branch predictor guessed wrong instruction class
   input  logic [3:0]       InstrClassM,                               // actual instruction class
+  input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,                                // data cache miss
   input  logic             DCacheAccess,                              // data cache accessed (hit or miss)
   input  logic             ICacheMiss,                                // instruction cache miss
@@ -124,7 +125,7 @@ module privileged (
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
     .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
-    .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
+    .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 2b71851f5..c6f5240a3 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -161,6 +161,7 @@ module wallypipelinedcore (
   logic                          BigEndianM;
   logic                          FCvtIntE;
   logic                          CommittedF;
+  logic 						 JumpOrTakenBranchM;
   
   // Bit manipulation unit
   logic [`XLEN-1:0]              BMUResultE;    // Bit manipuation result BMU -> IEU
@@ -177,7 +178,7 @@ module wallypipelinedcore (
     .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, 
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
+    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
     .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
     // Faults out
     .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
@@ -291,7 +292,7 @@ module wallypipelinedcore (
       .FRegWriteM, .LoadStallD,
       .DirPredictionWrongM, .BTBPredPCWrongM,
       .RASPredPCWrongM, .PredictionInstrClassWrongM,
-      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
+      .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
       .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, 
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,

From 7004f262c9db2f84b00d5b09731f844d07dc32ad Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 26 Jan 2023 14:51:39 -0800
Subject: [PATCH 30/84] Added DWARF symbols for QEMU simulation

---
 examples/C/sum/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/C/sum/Makefile b/examples/C/sum/Makefile
index 7c21cce23..a302309ff 100644
--- a/examples/C/sum/Makefile
+++ b/examples/C/sum/Makefile
@@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
 	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
+	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \

From 5df4679bcb8ecfa0a683f574eaf2d55d578d9fb6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 26 Jan 2023 14:53:25 -0800
Subject: [PATCH 31/84] Removed old link to imperas-riscv-tests

---
 addins/imperas-riscv-tests | 1 -
 1 file changed, 1 deletion(-)
 delete mode 120000 addins/imperas-riscv-tests

diff --git a/addins/imperas-riscv-tests b/addins/imperas-riscv-tests
deleted file mode 120000
index c3f365a40..000000000
--- a/addins/imperas-riscv-tests
+++ /dev/null
@@ -1 +0,0 @@
-/opt/riscv/imperas-riscv-tests/
\ No newline at end of file

From e682b8d0d40590d6c4047a28eea030201c41b21c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 05:55:31 -0800
Subject: [PATCH 32/84] renamed brpred to bpred

---
 pipelined/src/ifu/{brpred => bpred}/RAsPredictor.sv             | 0
 pipelined/src/ifu/{brpred => bpred}/bpred.sv                    | 0
 pipelined/src/ifu/{brpred => bpred}/btb.sv                      | 0
 pipelined/src/ifu/{brpred => bpred}/foldedgshare.sv             | 0
 pipelined/src/ifu/{brpred => bpred}/globalhistory.sv            | 0
 pipelined/src/ifu/{brpred => bpred}/gshare.sv                   | 0
 pipelined/src/ifu/{brpred => bpred}/localHistoryPredictor.sv    | 0
 pipelined/src/ifu/{brpred => bpred}/optgshare.sv                | 0
 pipelined/src/ifu/{brpred => bpred}/satCounter2.sv              | 0
 pipelined/src/ifu/{brpred => bpred}/speculativeglobalhistory.sv | 0
 pipelined/src/ifu/{brpred => bpred}/speculativegshare.sv        | 0
 pipelined/src/ifu/{brpred => bpred}/twoBitPredictor.sv          | 0
 12 files changed, 0 insertions(+), 0 deletions(-)
 rename pipelined/src/ifu/{brpred => bpred}/RAsPredictor.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/bpred.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/btb.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/foldedgshare.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/globalhistory.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/gshare.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/localHistoryPredictor.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/optgshare.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/satCounter2.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/speculativeglobalhistory.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/speculativegshare.sv (100%)
 rename pipelined/src/ifu/{brpred => bpred}/twoBitPredictor.sv (100%)

diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/RAsPredictor.sv
rename to pipelined/src/ifu/bpred/RAsPredictor.sv
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/bpred.sv
rename to pipelined/src/ifu/bpred/bpred.sv
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/btb.sv
rename to pipelined/src/ifu/bpred/btb.sv
diff --git a/pipelined/src/ifu/brpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/foldedgshare.sv
rename to pipelined/src/ifu/bpred/foldedgshare.sv
diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/bpred/globalhistory.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/globalhistory.sv
rename to pipelined/src/ifu/bpred/globalhistory.sv
diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/bpred/gshare.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/gshare.sv
rename to pipelined/src/ifu/bpred/gshare.sv
diff --git a/pipelined/src/ifu/brpred/localHistoryPredictor.sv b/pipelined/src/ifu/bpred/localHistoryPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/localHistoryPredictor.sv
rename to pipelined/src/ifu/bpred/localHistoryPredictor.sv
diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/bpred/optgshare.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/optgshare.sv
rename to pipelined/src/ifu/bpred/optgshare.sv
diff --git a/pipelined/src/ifu/brpred/satCounter2.sv b/pipelined/src/ifu/bpred/satCounter2.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/satCounter2.sv
rename to pipelined/src/ifu/bpred/satCounter2.sv
diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/speculativeglobalhistory.sv
rename to pipelined/src/ifu/bpred/speculativeglobalhistory.sv
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/speculativegshare.sv
rename to pipelined/src/ifu/bpred/speculativegshare.sv
diff --git a/pipelined/src/ifu/brpred/twoBitPredictor.sv b/pipelined/src/ifu/bpred/twoBitPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/brpred/twoBitPredictor.sv
rename to pipelined/src/ifu/bpred/twoBitPredictor.sv

From 4f7e1b942348fa4bdb2afe2c207af9382eb3d6fe Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 05:55:53 -0800
Subject: [PATCH 33/84] Fixed typo in bpred preventing compiling

---
 pipelined/src/ifu/bpred/bpred.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
index 4e1ada3c1..0319d3a08 100644
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@@ -49,7 +49,7 @@ module bpred (
   // Branch and jump outcome
   input  logic             PCSrcE,                    // Executation stage branch is taken
   input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input  logic [`XLEN-1:0]  dPCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic [`XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
   // Report branch prediction status

From b81b5781e18237f684853644d707a67bbf5a1a2b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 05:56:49 -0800
Subject: [PATCH 34/84] Renamed spike_rv32imc_isa.yaml to rv32gc to reflect
 cases tested

---
 .../spike/{spike_rv32imc_isa.yaml => spike_rv32gc_isa.yaml}       | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename tests/riscof/spike/{spike_rv32imc_isa.yaml => spike_rv32gc_isa.yaml} (100%)

diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml
similarity index 100%
rename from tests/riscof/spike/spike_rv32imc_isa.yaml
rename to tests/riscof/spike/spike_rv32gc_isa.yaml

From 4744996282f2e9272f28b2a69430df56384dec6e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 05:57:05 -0800
Subject: [PATCH 35/84] Removed suggestion about make allclean

---
 pipelined/regression/regression-wally | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index 6bbaa04b9..7398d7cec 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -204,9 +204,6 @@ def main():
     # Count the number of failures
     if num_fail:
         print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
-        # Remind the user to try `make allclean`, since it may be needed if test
-        # cases have changed
-        print("Reminder: have you run `make allclean`?")
     else:
         print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
     return num_fail

From 7fbbed7927de65ff3135e7bfce63e19210f91ccf Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 05:57:58 -0800
Subject: [PATCH 36/84] Update riscof makefile to use rv32gc config

---
 tests/riscof/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile
index 2918494dd..d963e4f0d 100644
--- a/tests/riscof/Makefile
+++ b/tests/riscof/Makefile
@@ -16,7 +16,7 @@ root:
 	mkdir -p $(work)
 	mkdir -p $(arch_workdir)
 	mkdir -p $(wally_workdir)
-	sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini
+	sed 's,{0},$(current_dir),g;s,{1},32gc,g' config.ini > config32.ini
 	sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
 	sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
 

From 37ba3d0fcde99f79072496173b9a31b172ce175b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 06:15:20 -0800
Subject: [PATCH 37/84] Removed f tests from rv32e

---
 tests/riscof/spike/spike_rv32e_isa.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml
index 7ae54347a..9e9775a9b 100644
--- a/tests/riscof/spike/spike_rv32e_isa.yaml
+++ b/tests/riscof/spike/spike_rv32e_isa.yaml
@@ -1,11 +1,11 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32EMFCZicsr_Zifencei
+  ISA: RV32EMCZicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-   reset-val: 0x40001034
+   reset-val: 0x40001014
    rv32:
      accessible: true
      mxl:

From 2af94bf283cc3eb4bc4ed5dc2b5b8c43e97d0527 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 07:21:55 -0800
Subject: [PATCH 38/84] Removed unused reference files

---
 .../C/references/cadd-01.reference_output     | 580 --------------
 .../C/references/caddi-01.reference_output    | 375 ---------
 .../references/caddi16sp-01.reference_output  |  72 --
 .../references/caddi4spn-01.reference_output  |  19 -
 .../C/references/cand-01.reference_output     | 586 --------------
 .../C/references/candi-01.reference_output    | 374 ---------
 .../C/references/cbeqz-01.reference_output    |  84 --
 .../C/references/cbnez-01.reference_output    |  84 --
 .../C/references/cj-01.reference_output       |  17 -
 .../C/references/cjal-01.reference_output     |  18 -
 .../C/references/cjalr-01.reference_output    |  15 -
 .../C/references/cjr-01.reference_output      |  15 -
 .../C/references/cli-01.reference_output      |  17 -
 .../C/references/clui-01.reference_output     |  15 -
 .../C/references/clw-01.reference_output      |  13 -
 .../C/references/clwsp-01.reference_output    |  15 -
 .../C/references/cmv-01.reference_output      |  85 --
 .../C/references/cnop-01.reference_output     |  14 -
 .../C/references/cor-01.reference_output      | 582 --------------
 .../C/references/cslli-01.reference_output    |  86 ---
 .../C/references/csrai-01.reference_output    |  85 --
 .../C/references/csrli-01.reference_output    |  87 ---
 .../C/references/csub-01.reference_output     | 581 --------------
 .../C/references/csw-01.reference_output      |  68 --
 .../C/references/cswsp-01.reference_output    |  70 --
 .../C/references/cxor-01.reference_output     | 580 --------------
 .../M/references/div-01.reference_output      | 581 --------------
 .../M/references/divu-01.reference_output     | 729 ------------------
 .../M/references/mul-01.reference_output      | 585 --------------
 .../M/references/mulh-01.reference_output     | 591 --------------
 .../M/references/mulhsu-01.reference_output   | 654 ----------------
 .../M/references/mulhu-01.reference_output    | 724 -----------------
 .../M/references/rem-01.reference_output      | 586 --------------
 .../M/references/remu-01.reference_output     | 725 -----------------
 .../references/WALLY-fld-01.reference_output  |   3 -
 .../I/references/E-add-01.reference_output    | 584 --------------
 .../I/references/E-addi-01.reference_output   | 564 --------------
 .../I/references/E-and-01.reference_output    | 588 --------------
 .../I/references/E-andi-01.reference_output   | 556 -------------
 .../I/references/E-auipc-01.reference_output  |  64 --
 .../I/references/E-beq-01.reference_output    | 592 --------------
 .../I/references/E-bge-01.reference_output    | 588 --------------
 .../I/references/E-bgeu-01.reference_output   | 728 -----------------
 .../I/references/E-blt-01.reference_output    | 588 --------------
 .../I/references/E-bltu-01.reference_output   | 728 -----------------
 .../I/references/E-bne-01.reference_output    | 588 --------------
 .../I/references/E-jal-01.reference_output    |  16 -
 .../I/references/E-jalr-01.reference_output   |  28 -
 .../references/E-lb-align-01.reference_output |  20 -
 .../E-lbu-align-01.reference_output           |  20 -
 .../references/E-lh-align-01.reference_output |  16 -
 .../E-lhu-align-01.reference_output           |  16 -
 .../I/references/E-lui-01.reference_output    |  64 --
 .../references/E-lw-align-01.reference_output |  16 -
 .../I/references/E-or-01.reference_output     | 592 --------------
 .../I/references/E-ori-01.reference_output    | 560 --------------
 .../references/E-sb-align-01.reference_output |  80 --
 .../references/E-sh-align-01.reference_output |  72 --
 .../I/references/E-sll-01.reference_output    |  88 ---
 .../I/references/E-slli-01.reference_output   |  92 ---
 .../I/references/E-slt-01.reference_output    | 584 --------------
 .../I/references/E-slti-01.reference_output   | 564 --------------
 .../I/references/E-sltiu-01.reference_output  | 700 -----------------
 .../I/references/E-sltu-01.reference_output   | 724 -----------------
 .../I/references/E-sra-01.reference_output    |  92 ---
 .../I/references/E-srai-01.reference_output   |  88 ---
 .../I/references/E-srl-01.reference_output    |  92 ---
 .../I/references/E-srli-01.reference_output   |  88 ---
 .../I/references/E-sub-01.reference_output    | 584 --------------
 .../references/E-sw-align-01.reference_output |  68 --
 .../I/references/E-xor-01.reference_output    | 584 --------------
 .../I/references/E-xori-01.reference_output   | 560 --------------
 .../I/references/WALLY-ADD.reference_output   |  12 -
 .../I/references/WALLY-SLT.reference_output   |  12 -
 .../I/references/WALLY-SLTU.reference_output  |  12 -
 .../I/references/WALLY-SUB.reference_output   |  12 -
 .../I/references/WALLY-XOR.reference_output   |  12 -
 77 files changed, 22351 deletions(-)
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi16sp-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi4spn-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cand-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/candi-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbeqz-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbnez-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cj-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjal-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjalr-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjr-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cli-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clui-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clw-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clwsp-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cmv-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cnop-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cor-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cslli-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrai-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrli-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csub-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csw-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cswsp-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cxor-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output
deleted file mode 100644
index fbdfa17f9..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output
+++ /dev/null
@@ -1,580 +0,0 @@
-bfffffff
-00004000
-bfffdffe
-e000003f
-56666665
-f7fffffa
-fbff4afc
-ffffffff
-00000000
-ef7ffffe
-ffc0ffff
-1fdfffff
-fff00002
-fff74afc
-003bffff
-fffe001f
-ffff0005
-3332b333
-3fffbfff
-fbffdffe
-fffeeffe
-0001f7ff
-66666265
-dffffdfe
-ffffff07
-ffffff3e
-7fffffbe
-66666646
-55555545
-fffffff9
-ffff7ffa
-0ffffffd
-66666665
-dfffffff
-5e666665
-fdff4afc
-ff0fffff
-bf7fffff
-00bfffff
-55355555
-002fffff
-ffffffff
-007bffff
-bffdffff
-003fbfff
-fffff03f
-1ffff7ff
-ffff7bfe
-ffffddfe
-ffffff03
-333332b1
-0000001f
-efffffee
-01fffff7
-55555552
-1ffffffe
-80000004
-3ffffffa
-0ffffff8
-07fffffa
-03fffffb
-55755556
-00040002
-00020020
-0000fdff
-fe007fff
-00002fff
-ffff9fff
-ffff5afc
-fc0007ff
-00001400
-aaaaacaa
-00040100
-fc00007f
-0000000f
-00000110
-0000000a
-00010002
-00000005
-07fffff6
-03dfffff
-00fffffc
-00800000
-66866666
-55655556
-00080200
-aaab2aab
-00004100
-00008800
-01000400
-00040200
-0000b585
-0000b514
-ffffff80
-00016a0a
-00000002
-66671b6c
-3333e839
-0000b50b
-aaab5fb0
-55560a5b
-0000b509
-00016a08
-0000b505
-66671b6a
-3333e837
-55560a59
-0000b507
-00016a09
-00000001
-66671b6b
-3333e838
-0000b50a
-aaab5faf
-55560a5a
-0000b508
-00000002
-fffe95fa
-6665b164
-33327e31
-ffff4b03
-aaa9f5a8
-5554a053
-ffff4b01
-00000000
-ffff4afd
-6665b162
-33327e2f
-5554a051
-ffff4aff
-00000001
-fffe95f9
-6665b163
-33327e30
-ffff4b02
-aaa9f5a7
-5554a052
-ffff4b00
-66671b6c
-6665b164
-ccccccce
-9999999b
-6666666d
-11111112
-bbbbbbbd
-6666666b
-66671b6a
-66666667
-cccccccc
-99999999
-bbbbbbbb
-66666669
-66671b6b
-6665b163
-cccccccd
-9999999a
-6666666c
-11111111
-bbbbbbbc
-6666666a
-3333e839
-33327e31
-9999999b
-66666668
-3333333a
-dddddddf
-8888888a
-33333338
-3333e837
-33333334
-99999999
-66666666
-88888888
-33333336
-3333e838
-33327e30
-9999999a
-66666667
-33333339
-ddddddde
-88888889
-33333337
-0000b50b
-ffff4b03
-6666666d
-3333333a
-0000000c
-aaaaaab1
-5555555c
-0000000a
-0000b509
-00000006
-6666666b
-33333338
-5555555a
-00000008
-0000b50a
-ffff4b02
-6666666c
-33333339
-0000000b
-aaaaaab0
-5555555b
-00000009
-aaab5fb0
-aaa9f5a8
-11111112
-dddddddf
-aaaaaab1
-55555556
-00000001
-aaaaaaaf
-aaab5fae
-aaaaaaab
-11111110
-dddddddd
-ffffffff
-aaaaaaad
-aaab5faf
-aaa9f5a7
-11111111
-ddddddde
-aaaaaab0
-55555555
-00000000
-aaaaaaae
-55560a5b
-5554a053
-bbbbbbbd
-8888888a
-5555555c
-00000001
-aaaaaaac
-5555555a
-55560a59
-55555556
-bbbbbbbb
-88888888
-aaaaaaaa
-55555558
-55560a5a
-5554a052
-bbbbbbbc
-88888889
-5555555b
-00000000
-aaaaaaab
-55555559
-0000b509
-ffff4b01
-6666666b
-33333338
-0000000a
-aaaaaaaf
-5555555a
-00000008
-0000b507
-00000004
-66666669
-33333336
-55555558
-00000006
-0000b508
-ffff4b00
-6666666a
-33333337
-00000009
-aaaaaaae
-55555559
-00000007
-00016a08
-00000000
-66671b6a
-3333e837
-0000b509
-aaab5fae
-55560a59
-0000b507
-00016a06
-0000b503
-66671b68
-3333e835
-55560a57
-0000b505
-00016a07
-ffffffff
-66671b69
-3333e836
-0000b508
-aaab5fad
-55560a58
-0000b506
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000003
-66671b6a
-6665b162
-cccccccc
-99999999
-6666666b
-11111110
-bbbbbbbb
-66666669
-66671b68
-66666665
-33333333
-99999998
-66666665
-88888887
-33333335
-3333e837
-33327e2f
-99999999
-66666666
-33333338
-dddddddd
-88888888
-33333336
-0000b50a
-ffff4b02
-6666666c
-33333339
-0000000b
-aaaaaab0
-5555555b
-00000009
-0000b508
-00000005
-6666666a
-33333337
-55555559
-00000007
-0000b509
-ffff4b01
-6666666b
-33333338
-0000000a
-aaaaaaaf
-5555555a
-00000008
-aaab5faf
-aaa9f5a7
-11111111
-ddddddde
-aaaaaab0
-55555555
-00000000
-aaaaaaae
-aaab5fad
-aaaaaaaa
-1111110f
-dddddddc
-fffffffe
-aaaaaaac
-aaab5fae
-aaa9f5a6
-11111110
-dddddddd
-aaaaaaaf
-55555554
-ffffffff
-aaaaaaad
-55560a5a
-5554a052
-bbbbbbbc
-88888889
-5555555b
-00000000
-aaaaaaab
-55555559
-55560a58
-55555555
-bbbbbbba
-88888887
-aaaaaaa9
-55555557
-55560a59
-5554a051
-bbbbbbbb
-88888888
-5555555a
-ffffffff
-aaaaaaaa
-55555558
-0000b508
-ffff4b00
-6666666a
-33333337
-00000009
-aaaaaaae
-55555559
-00000007
-0000b506
-00000003
-66666668
-33333335
-55555557
-00000005
-0000b507
-ffff4aff
-66666669
-33333336
-00000008
-aaaaaaad
-55555558
-00000006
-ccccccca
-99999997
-bbbbbbb9
-66666667
-66671b69
-6665b161
-cccccccb
-99999998
-6666666a
-1111110f
-bbbbbbba
-66666668
-3333e837
-33327e2f
-99999999
-66666666
-33333338
-dddddddd
-88888888
-33333336
-3333e835
-33333332
-99999997
-66666664
-88888886
-33333334
-3333e836
-33327e2e
-99999998
-66666665
-33333337
-dddddddc
-88888887
-33333335
-55560a59
-5554a051
-bbbbbbbb
-88888888
-5555555a
-ffffffff
-aaaaaaaa
-55555558
-55560a57
-55555554
-bbbbbbb9
-88888886
-aaaaaaa8
-55555556
-55560a58
-5554a050
-bbbbbbba
-88888887
-55555559
-fffffffe
-aaaaaaa9
-55555557
-0000b507
-ffff4aff
-66666669
-33333336
-00000008
-aaaaaaad
-55555558
-00000006
-0000b505
-00000002
-66666667
-33333334
-55555556
-00000004
-0000b506
-ffff4afe
-66666668
-33333335
-00000007
-aaaaaaac
-55555557
-00000005
-00016a09
-00000001
-66671b6b
-3333e838
-0000b50a
-aaab5faf
-55560a5a
-0000b508
-00016a07
-0000b504
-66671b69
-3333e836
-55560a58
-0000b506
-00016a08
-00000000
-66671b6a
-3333e837
-0000b509
-aaab5fae
-55560a59
-0000b507
-00000001
-fffe95f9
-6665b163
-33327e30
-ffff4b02
-aaa9f5a7
-5554a052
-ffff4b00
-ffffffff
-ffff4afc
-6665b161
-33327e2e
-5554a050
-ffff4afe
-00000000
-fffe95f8
-6665b162
-33327e2f
-ffff4b01
-aaa9f5a6
-5554a051
-ffff4aff
-66671b6b
-6665b163
-cccccccd
-9999999a
-6666666c
-11111111
-bbbbbbbc
-6666666a
-66671b69
-66666666
-cccccccb
-99999998
-bbbbbbba
-66666668
-66671b6a
-6665b162
-cccccccc
-99999999
-6666666b
-11111110
-bbbbbbbb
-66666669
-3333e838
-33327e30
-9999999a
-66666667
-33333339
-ddddddde
-88888889
-33333337
-3333e836
-80001fff
-feff7ffe
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output
deleted file mode 100644
index 168266e00..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output
+++ /dev/null
@@ -1,375 +0,0 @@
-007fffe0
-80000003
-bffffffe
-e0000007
-f0000003
-f8000004
-fc000003
-fdfffffa
-ff00000f
-ff7ffffa
-ffbfffdf
-ffdffffd
-ffeffffd
-fff80004
-fffc0004
-fffe0003
-fffefffa
-ffff7ff7
-ffffc005
-ffffe002
-ffffeffd
-fffff7df
-fffffc03
-fffffdee
-fffffefe
-ffffff82
-ffffffba
-ffffffc9
-ffffffeb
-ffffffe7
-ffffffeb
-00000001
-00000005
-0000001c
-effffff6
-0007fffd
-80000009
-3fffffea
-20000010
-10000000
-08000010
-04000005
-02000006
-01000008
-0040000f
-00200009
-00100009
-0004000f
-0001ffea
-0000fff0
-00008006
-00004005
-00002007
-00000ff9
-000007f6
-000003fe
-000001ef
-00000101
-00000084
-00000046
-00000024
-00000013
-0000000c
-00000004
-00000001
-00000005
-00000001
-0000b50b
-0000b501
-0000b504
-0000b50c
-0000b509
-0000b510
-0000b505
-0000b50a
-0000b507
-0000b50e
-0000b500
-0000b503
-0000b508
-0000b50f
-ffff4b03
-ffff4af9
-ffff4afc
-ffff4b04
-ffff4b01
-ffff4b08
-ffff4afd
-ffff4b02
-ffff4aff
-ffff4b06
-ffff4af8
-ffff4afb
-ffff4b00
-ffff4b07
-6666666d
-66666663
-66666666
-6666666e
-6666666b
-66666672
-66666667
-6666666c
-66666669
-66666670
-66666662
-66666665
-6666666a
-66666671
-3333333a
-33333330
-33333333
-3333333b
-33333338
-3333333f
-33333334
-33333339
-33333336
-3333333d
-3333332f
-33333332
-33333337
-3333333e
-0000000c
-00000002
-00000005
-0000000d
-0000000a
-00000011
-00000006
-0000000b
-00000008
-0000000f
-00000001
-00000004
-00000009
-00000010
-aaaaaab1
-aaaaaaa7
-aaaaaaaa
-aaaaaab2
-aaaaaaaf
-aaaaaab6
-aaaaaaab
-aaaaaab0
-aaaaaaad
-aaaaaab4
-aaaaaaa6
-aaaaaaa9
-aaaaaaae
-aaaaaab5
-5555555c
-55555552
-55555555
-5555555d
-5555555a
-55555561
-55555556
-5555555b
-55555558
-5555555f
-55555551
-55555554
-55555559
-55555560
-0000000a
-00000000
-00000003
-0000000b
-00000008
-0000000f
-00000009
-00000006
-0000000d
-ffffffff
-00000002
-00000007
-0000000e
-0000b509
-0000b4ff
-0000b502
-0000b50a
-0000b507
-0000b50e
-0000b503
-0000b508
-0000b505
-0000b50c
-0000b4fe
-0000b501
-0000b506
-0000b50d
-00000006
-fffffffc
-ffffffff
-00000007
-00000004
-0000000b
-00000000
-00000005
-00000002
-00000009
-fffffffb
-fffffffe
-00000003
-0000000a
-6666666b
-66666661
-66666664
-6666666c
-66666669
-66666670
-66666665
-6666666a
-66666667
-6666666e
-66666660
-66666663
-66666668
-6666666f
-33333338
-3333332e
-33333331
-33333339
-33333336
-3333333d
-33333332
-33333337
-33333334
-3333333b
-3333332d
-33333330
-33333335
-3333333c
-5555555a
-55555550
-55555553
-5555555b
-55555558
-5555555f
-55555554
-55555559
-55555556
-5555555d
-5555554f
-55555552
-55555557
-5555555e
-00000008
-fffffffe
-00000009
-00000006
-0000000d
-00000002
-00000007
-00000004
-0000000b
-fffffffd
-00000000
-00000005
-0000000c
-0000b50a
-0000b500
-0000b503
-0000b50b
-0000b508
-0000b50f
-0000b504
-0000b509
-0000b506
-0000b50d
-0000b4ff
-0000b502
-0000b507
-0000b50e
-ffff4b02
-ffff4af8
-ffff4afb
-ffff4b03
-ffff4b00
-ffff4b07
-ffff4afc
-ffff4b01
-ffff4afe
-ffff4b05
-ffff4af7
-ffff4afa
-ffff4aff
-ffff4b06
-6666666c
-66666662
-66666665
-6666666d
-6666666a
-66666671
-66666666
-6666666b
-66666668
-6666666f
-66666661
-66666664
-66666669
-66666670
-33333339
-3333332f
-33333332
-3333333a
-33333337
-3333333e
-33333333
-33333338
-33333335
-3333333c
-0000000d
-aaaaaaa3
-5555555e
-0000001b
-3333332e
-33333331
-33333336
-3333333d
-0000000b
-00000001
-00000004
-0000000c
-00000009
-00000010
-00000005
-0000000a
-00000007
-0000000e
-00000000
-00000003
-00000008
-0000000f
-aaaaaab0
-aaaaaaa6
-aaaaaaa9
-aaaaaab1
-aaaaaaae
-aaaaaab5
-aaaaaaaa
-aaaaaaaf
-aaaaaaac
-aaaaaab3
-aaaaaaa5
-aaaaaaa8
-aaaaaaad
-aaaaaab4
-5555555b
-55555551
-55555554
-5555555c
-55555559
-55555560
-55555555
-5555555a
-55555557
-55555550
-55555553
-55555558
-5555555f
-00000009
-ffffffff
-00000002
-0000000a
-00000007
-0000000e
-00000003
-00000008
-00000005
-0000000c
-fffffffe
-00000001
-00000006
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi16sp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi16sp-01.reference_output
deleted file mode 100644
index d77f4904d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi16sp-01.reference_output
+++ /dev/null
@@ -1,72 +0,0 @@
-003ffe00
-8000007f
-c000005f
-dfffff9f
-effffe9f
-f7ffffaf
-fbffff6f
-fe0000ef
-feffff7f
-ff7fff8f
-ffc0003f
-ffdffe9f
-fff0000f
-fff8000f
-fffbfeff
-fffe014f
-fffeffaf
-ffff803f
-ffffc04f
-ffffdfbf
-fffff07f
-fffff87f
-fffffbef
-ffffff4f
-fffffedf
-ffffff5f
-0000004f
-ffffffef
-fffffe8f
-ffffff97
-fffffefb
-ffffff6d
-0000006e
-004001f0
-fffffeeb
-ffbfffcf
-7fffff60
-40000100
-1ffffff0
-10000030
-07ffff60
-000000c0
-00000210
-00000200
-00000078
-fffffef4
-ffffffb2
-00000051
-00000029
-aaaaaada
-555555b5
-ffffff00
-00000080
-03fffe00
-01fffe00
-00ffffc0
-00800010
-00200020
-00100090
-00080050
-0003fea0
-0001ff60
-00010150
-000081f0
-00004040
-00002080
-000011f0
-00000900
-000005f0
-00000350
-000002f0
-000000b0
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi4spn-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi4spn-01.reference_output
deleted file mode 100644
index 976ad903c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi4spn-01.reference_output
+++ /dev/null
@@ -1,19 +0,0 @@
-000003fc
-000001fc
-000002fc
-0000037c
-000003bc
-000003dc
-000003ec
-000003f4
-000003f8
-00000200
-00000100
-00000080
-00000004
-000002a8
-00000154
-00000040
-00000020
-00000010
-00000008
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cand-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cand-01.reference_output
deleted file mode 100644
index 6481f5fbf..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cand-01.reference_output
+++ /dev/null
@@ -1,586 +0,0 @@
-80000000
-0000b503
-bfff4afc
-00000003
-00000200
-55555555
-00001000
-fdff7fff
-fefffff9
-ff7ffffa
-40000000
-00000006
-00000020
-20000000
-00000020
-fffdffdf
-66666665
-00000000
-ffffbff8
-00000003
-fffff7fd
-00000003
-00200000
-55555456
-ffffff7c
-ffff4abd
-20000000
-55555545
-aaaaaaa3
-80000000
-dffffffd
-33333334
-00000800
-15555555
-2fffffff
-f7feffff
-00000009
-ddffffff
-fefffffa
-c0000000
-00008000
-ffdf7fff
-00200000
-00000100
-00000000
-fffdfffc
-00000006
-00020000
-40000000
-55554554
-ffff42fd
-55555156
-fffffd7f
-fffffefd
-00000004
-00000200
-00000006
-00100000
-aaaaaaaa
-00000002
-80000000
-00000000
-00000000
-08000000
-00000000
-00000000
-00000000
-00000000
-00400000
-00080000
-00040000
-00000000
-00000000
-00002000
-00001000
-00000400
-00000080
-00000040
-00000020
-00000010
-00000008
-00000000
-00000001
-10000000
-00000000
-04000000
-01000000
-00000000
-00100000
-00000000
-00040000
-00020000
-00010000
-00000000
-00000000
-00002000
-00000000
-00000400
-00000100
-00000080
-00000000
-00000004
-00000000
-00000000
-0000b505
-00000005
-00002405
-00003104
-00000004
-0000a001
-00001504
-00000004
-0000b501
-00000000
-00002405
-00003100
-00001504
-00000000
-0000b504
-00000004
-00002404
-00003101
-00000005
-0000a000
-00001505
-00000001
-00000005
-ffff4afd
-66664265
-33330234
-00000004
-aaaa0aa9
-55554054
-00000004
-00000001
-00000000
-66664265
-33330230
-55554054
-00000000
-00000004
-ffff4afc
-66664264
-33330231
-00000005
-aaaa0aa8
-55554055
-00000001
-00002405
-66664265
-66666667
-22222224
-00000006
-22222223
-44444446
-00000004
-00002403
-00000000
-66666665
-22222222
-44444444
-00000002
-00002404
-66664264
-66666666
-22222223
-00000005
-22222222
-44444445
-00000003
-00003104
-33330234
-22222224
-33333334
-00000004
-22222220
-11111114
-00000004
-00003100
-00000000
-22222224
-33333330
-11111114
-00000000
-00003104
-33330234
-22222224
-33333330
-00000004
-22222220
-11111114
-00000000
-00000004
-00000004
-00000006
-00000004
-00000006
-00000002
-00000006
-00000004
-00000002
-00000000
-00000004
-00000002
-00000004
-00000002
-00000004
-00000004
-00000006
-00000002
-00000004
-00000002
-00000004
-00000002
-0000a001
-aaaa0aa9
-22222223
-22222220
-00000002
-aaaaaaab
-00000002
-00000000
-0000a003
-00000000
-22222221
-22222222
-00000000
-00000002
-0000a000
-aaaa0aa8
-22222222
-22222223
-00000001
-aaaaaaaa
-00000001
-00000003
-00001504
-55554054
-44444446
-11111114
-00000006
-00000002
-55555556
-00000004
-00001502
-00000000
-44444444
-11111112
-55555554
-00000002
-00001504
-55554054
-44444446
-11111112
-00000004
-00000002
-55555554
-00000002
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000000
-00000000
-00000004
-00000000
-00000004
-00000000
-00000004
-00000004
-00000004
-00000000
-00000004
-00000000
-00000004
-00000000
-0000b501
-00000001
-00002403
-00003100
-00000002
-0000a003
-00001502
-00000000
-0000b503
-00000000
-00002401
-00003102
-00001500
-00000002
-0000b500
-00000000
-00002402
-00003103
-00000001
-0000a002
-00001501
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00002405
-66664265
-66666665
-22222224
-00000004
-22222221
-44444444
-00000004
-00002401
-00000000
-22222221
-33333332
-11111110
-00000002
-00003100
-33330230
-22222222
-33333333
-00000001
-22222222
-11111111
-00000003
-00000005
-00000005
-00000005
-00000004
-00000004
-00000001
-00000004
-00000004
-00000001
-00000000
-00000005
-00000000
-00000004
-00000000
-00000004
-00000004
-00000004
-00000001
-00000005
-00000000
-00000005
-00000001
-0000a000
-aaaa0aa8
-22222222
-22222220
-00000002
-aaaaaaaa
-00000002
-00000000
-0000a002
-00000000
-22222220
-22222222
-00000000
-00000002
-0000a000
-aaaa0aa8
-22222222
-22222222
-00000000
-aaaaaaaa
-00000000
-00000002
-00001505
-55554055
-44444445
-11111114
-00000004
-00000001
-55555554
-00000004
-00001501
-00000000
-44444445
-11111110
-55555554
-00000000
-00001504
-55554054
-44444444
-11111111
-00000005
-00000000
-55555555
-00000001
-00000001
-00000001
-00000003
-00000000
-00000002
-00000003
-00000002
-00000000
-00000003
-00000000
-00000001
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000003
-00000001
-00000002
-00000001
-00000003
-00000000
-66666665
-22222220
-44444444
-00002404
-66664264
-66666664
-22222221
-00000005
-22222220
-44444445
-00000001
-00003100
-33330230
-22222222
-33333330
-00000002
-22222222
-11111112
-00000000
-00003102
-00000000
-22222220
-33333332
-11111110
-00000002
-00003100
-33330230
-22222222
-33333332
-00000000
-22222222
-11111110
-00000002
-00001504
-55554054
-44444444
-11111114
-00000004
-00000000
-55555554
-00000004
-00001500
-00000000
-44444444
-11111110
-55555554
-00000000
-00001504
-55554054
-44444444
-11111110
-00000004
-00000000
-55555554
-00000000
-00000000
-00000000
-00000002
-00000000
-00000002
-00000002
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000002
-00000000
-00000002
-00000000
-00000002
-0000b504
-00000004
-00002404
-00003104
-00000004
-0000a000
-00001504
-00000004
-0000b500
-00000000
-00002404
-00003100
-00001504
-00000000
-0000b504
-00000004
-00002404
-00003100
-00000004
-0000a000
-00001504
-00000000
-00000004
-ffff4afc
-66664264
-33330234
-00000004
-aaaa0aa8
-55554054
-00000004
-00000000
-00000000
-66664264
-33330230
-55554054
-00000000
-00000004
-ffff4afc
-66664264
-33330230
-00000004
-aaaa0aa8
-55554054
-00000000
-00002404
-66664264
-66666666
-22222224
-00000006
-22222222
-44444446
-00000004
-00002402
-00000000
-66666664
-22222222
-44444444
-00000002
-00002404
-66664264
-66666666
-22222222
-00000004
-22222222
-44444444
-00000002
-00003101
-33330231
-22222223
-33333330
-00000002
-22222223
-11111112
-00000000
-00003103
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/candi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/candi-01.reference_output
deleted file mode 100644
index a7f6c9c03..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/candi-01.reference_output
+++ /dev/null
@@ -1,374 +0,0 @@
-00000200
-00000004
-00000000
-00000007
-00000003
-00000006
-00000009
-00000004
-00000000
-00000005
-ffbffff8
-ffdffffd
-00000004
-00000002
-fffbfff8
-00000007
-00000006
-00000005
-00000004
-00000003
-ffffeffa
-00000006
-fffffbfb
-fffffdea
-00000006
-ffffff6a
-ffffffbe
-ffffffd0
-00000004
-00000000
-00000002
-00000000
-00000006
-0000001f
-00000800
-00000005
-00000000
-00000000
-00000000
-10000000
-00000000
-00000000
-02000000
-01000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00008000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000080
-00000000
-00000000
-00000000
-00000008
-00000000
-00000000
-00000000
-00000004
-0000b504
-0000b505
-00000005
-00000004
-00000001
-00000000
-00000005
-00000000
-00000001
-0000b501
-0000b504
-00000001
-00000000
-00000004
-ffff4afc
-ffff4afd
-00000005
-00000004
-00000009
-00000000
-00000005
-00000000
-00000009
-ffff4af9
-ffff4afc
-00000001
-00000008
-00000006
-66666664
-66666667
-00000007
-00000004
-00000003
-00000000
-00000005
-00000002
-00000001
-66666663
-66666666
-00000003
-00000002
-00000004
-33333334
-33333334
-00000004
-00000004
-00000000
-00000000
-00000004
-00000000
-00000000
-33333330
-33333334
-00000000
-00000000
-00000006
-00000004
-00000006
-00000006
-00000004
-00000002
-00000000
-00000004
-00000002
-00000000
-00000002
-00000006
-00000002
-00000002
-00000002
-aaaaaaa8
-aaaaaaab
-00000003
-00000000
-0000000b
-00000000
-00000001
-00000002
-00000009
-aaaaaaab
-aaaaaaaa
-00000003
-0000000a
-00000006
-55555554
-55555556
-00000006
-00000004
-00000002
-00000000
-00000004
-00000002
-00000000
-55555552
-55555556
-00000002
-00000002
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000000
-00000000
-00000000
-00000004
-00000000
-00000000
-00000002
-0000b500
-0000b503
-00000003
-00000000
-00000003
-00000000
-00000001
-00000002
-00000001
-0000b503
-0000b502
-00000003
-00000002
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000004
-66666664
-66666665
-00000005
-00000004
-00000001
-00000000
-00000005
-00000000
-00000001
-66666661
-66666664
-00000001
-00000000
-00000002
-33333330
-33333332
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000000
-33333332
-33333332
-00000002
-00000002
-00000004
-55555554
-55555554
-00000004
-00000004
-00000000
-00000000
-00000004
-00000000
-00000000
-55555550
-55555554
-00000000
-00000000
-00000002
-00000000
-00000002
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000000
-00000002
-00000002
-00000002
-00000002
-00000004
-0000b504
-0000b504
-00000004
-00000004
-00000000
-00000000
-00000004
-00000000
-00000000
-0000b500
-0000b504
-00000000
-00000000
-00000004
-ffff4afc
-ffff4afc
-00000004
-00000004
-00000008
-00000000
-00000004
-00000000
-00000008
-ffff4af8
-ffff4afc
-00000000
-00000008
-00000006
-66666664
-66666666
-00000006
-00000004
-00000002
-00000000
-00000004
-00000002
-00000000
-66666662
-66666666
-00000002
-00000002
-00000002
-33333330
-33333333
-00000003
-00000000
-00000003
-00000000
-00000001
-00000002
-00000001
-00000002
-00000000
-00000004
-00000000
-33333333
-33333332
-00000003
-00000002
-00000004
-00000004
-00000005
-00000005
-00000004
-00000001
-00000000
-00000005
-00000000
-00000001
-00000001
-00000004
-00000001
-00000000
-00000002
-aaaaaaa8
-aaaaaaaa
-00000002
-00000000
-0000000a
-00000000
-00000002
-00000008
-aaaaaaaa
-aaaaaaaa
-00000002
-0000000a
-00000004
-55555554
-55555555
-00000005
-00000001
-00000000
-00000005
-00000000
-00000001
-55555551
-55555554
-00000001
-00000000
-00000002
-00000000
-00000003
-00000003
-00000000
-00000003
-00000000
-00000001
-00000002
-00000001
-00000003
-00000002
-00000003
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbeqz-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbeqz-01.reference_output
deleted file mode 100644
index b57270221..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbeqz-01.reference_output
+++ /dev/null
@@ -1,84 +0,0 @@
-ff76df58
-ff76df5a
-ff76df5c
-ff76df5e
-ff76df60
-ff76df62
-ff76df64
-ff76df66
-ff76df68
-ff76df6a
-ff76df6c
-ff76df6e
-ff76df70
-ff76df72
-ff76df74
-ff76df76
-ff76df78
-ff76df7a
-ff76df7c
-ff76df7e
-ff76df80
-ff76df82
-ff76df84
-ff76df86
-ff76df88
-ff76df8a
-ff76df8c
-ff76df8e
-ff76df90
-ff76df92
-ff76df94
-ff76df96
-ff76df98
-ff76df9a
-ff76df9c
-ff76df9e
-ff76dfa0
-ff76dfa2
-ff76dfa4
-ff76dfa6
-ff76dfa8
-ff76dfaa
-ff76dfac
-ff76dfae
-ff76dfb0
-ff76dfb2
-ff76dfb4
-ff76dfb6
-ff76dfb8
-ff76dfba
-ff76dfbc
-ff76dfbe
-ff76dfc0
-ff76dfc2
-ff76dfc4
-ff76dfc6
-ff76dfc8
-ff76dfca
-ff76dfcc
-ff76dfce
-ff76dfd0
-ff76dfd2
-ff76dfd4
-ff76dfd6
-ff76dfd8
-ff76dfda
-ff76dfdc
-ff76dfde
-ff76dfe0
-ff76dfe2
-ff76dfe5
-ff76dfe7
-ff76dfe9
-ff76dfeb
-ff76dfed
-ff76dfef
-ff76dff1
-ff76dff3
-ff76dff5
-ff76dff7
-ff76dff9
-ff76dffb
-ff76dffd
-ff76dfff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbnez-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbnez-01.reference_output
deleted file mode 100644
index e303deedd..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cbnez-01.reference_output
+++ /dev/null
@@ -1,84 +0,0 @@
-ff76df57
-ff76df5a
-ff76df5d
-ff76df5e
-ff76df61
-ff76df62
-ff76df63
-ff76df66
-ff76df69
-ff76df6c
-ff76df6d
-ff76df70
-ff76df73
-ff76df76
-ff76df79
-ff76df7c
-ff76df7d
-ff76df80
-ff76df81
-ff76df82
-ff76df85
-ff76df88
-ff76df89
-ff76df8a
-ff76df8d
-ff76df90
-ff76df93
-ff76df96
-ff76df97
-ff76df98
-ff76df9b
-ff76df9c
-ff76df9d
-ff76dfa0
-ff76dfa1
-ff76dfa4
-ff76dfa5
-ff76dfa8
-ff76dfa9
-ff76dfac
-ff76dfaf
-ff76dfb2
-ff76dfb3
-ff76dfb4
-ff76dfb5
-ff76dfb6
-ff76dfb7
-ff76dfba
-ff76dfbd
-ff76dfbe
-ff76dfc1
-ff76dfc2
-ff76dfc5
-ff76dfc6
-ff76dfc9
-ff76dfcc
-ff76dfcd
-ff76dfce
-ff76dfcf
-ff76dfd2
-ff76dfd5
-ff76dfd6
-ff76dfd7
-ff76dfda
-ff76dfdb
-ff76dfdc
-ff76dfdf
-ff76dfe2
-ff76dfe3
-ff76dfe6
-ff76dfe8
-ff76dfeb
-ff76dfec
-ff76dfef
-ff76dff0
-ff76dff3
-ff76dff4
-ff76dff7
-ff76dff8
-ff76dff9
-ff76dffa
-ff76dffb
-ff76dffe
-ff76e001
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cj-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cj-01.reference_output
deleted file mode 100644
index beca9cf62..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cj-01.reference_output
+++ /dev/null
@@ -1,17 +0,0 @@
-ff76df57
-ff76df58
-ff76df59
-ff76df5a
-ff76df5b
-ff76df5c
-ff76df5d
-ff76df5e
-ff76df61
-ff76df64
-ff76df67
-ff76df68
-ff76df6b
-ff76df6e
-ff76df71
-ff76df74
-ff76df77
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjal-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjal-01.reference_output
deleted file mode 100644
index 52a519fdc..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjal-01.reference_output
+++ /dev/null
@@ -1,18 +0,0 @@
-00000015
-00000409
-00000209
-00000109
-00000089
-00000049
-00000029
-00000019
-00000011
-0000000d
-0000000d
-0000000d
-0000055d
-0000000d
-0000000d
-0000000d
-0000000d
-0000000d
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjalr-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjalr-01.reference_output
deleted file mode 100644
index b566ee4ba..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjalr-01.reference_output
+++ /dev/null
@@ -1,15 +0,0 @@
-00000009
-0000000f
-00000009
-0000000f
-00000009
-0000000f
-00000009
-0000000f
-00000009
-0000000f
-00000009
-0000000f
-0000000f
-00000009
-0000000f
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjr-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjr-01.reference_output
deleted file mode 100644
index c65570806..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cjr-01.reference_output
+++ /dev/null
@@ -1,15 +0,0 @@
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000013
-00000011
-00000013
-00000011
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cli-01.reference_output
deleted file mode 100644
index bf520871c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cli-01.reference_output
+++ /dev/null
@@ -1,17 +0,0 @@
-ffffffe0
-0000001f
-ffffffef
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-00000010
-00000000
-00000008
-00000004
-00000000
-00000001
-ffffffea
-00000015
-00000000
-00000002
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clui-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clui-01.reference_output
deleted file mode 100644
index 69598767d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clui-01.reference_output
+++ /dev/null
@@ -1,15 +0,0 @@
-00004000
-0001f000
-fffef000
-ffff7000
-ffffb000
-ffffd000
-00000000
-fffe0000
-0000c000
-00010000
-00008000
-00002000
-00001000
-fffea000
-00015000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clw-01.reference_output
deleted file mode 100644
index b1c4788a3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clw-01.reference_output
+++ /dev/null
@@ -1,13 +0,0 @@
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clwsp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clwsp-01.reference_output
deleted file mode 100644
index fbe8ffc2c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/clwsp-01.reference_output
+++ /dev/null
@@ -1,15 +0,0 @@
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cmv-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cmv-01.reference_output
deleted file mode 100644
index b9982de7d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cmv-01.reference_output
+++ /dev/null
@@ -1,85 +0,0 @@
-80000000
-7fffffff
-bfffffff
-dfffffff
-efffffff
-f7ffffff
-fbffffff
-fdffffff
-feffffff
-ff7fffff
-ffbfffff
-ffdfffff
-ffefffff
-fff7ffff
-00000000
-fffdffff
-fffeffff
-ffff7fff
-ffffbfff
-ffffdfff
-ffffefff
-fffff7ff
-fffffbff
-fffffdff
-fffffeff
-ffffff7f
-ffffffbf
-ffffffdf
-ffffffef
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-40000000
-20000000
-10000000
-08000000
-04000000
-02000000
-01000000
-00800000
-00400000
-00200000
-00100000
-00080000
-00040000
-00020000
-00010000
-00008000
-00004000
-00002000
-00001000
-00000800
-00000400
-00000200
-00000100
-00000080
-00000040
-00000001
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000020
-00000010
-00000008
-00000003
-fffbffff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cnop-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cnop-01.reference_output
deleted file mode 100644
index 1b55829c0..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cnop-01.reference_output
+++ /dev/null
@@ -1,14 +0,0 @@
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cor-01.reference_output
deleted file mode 100644
index 690b29794..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cor-01.reference_output
+++ /dev/null
@@ -1,582 +0,0 @@
-80000000
-33333334
-bfffffff
-dfffffff
-ffffffff
-f7ffffff
-ffffffff
-fdffffff
-ffffffff
-ffffffff
-ffbfffff
-ffffffff
-ffffffff
-fff7ffff
-fffbffff
-fffdffff
-ffffffff
-ffff7fff
-ffffbfff
-ffffdfff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-fffffeff
-ffffff7f
-ffffffbf
-ffffffff
-ffffffff
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-7fffffff
-dfffffff
-ffffffff
-f7ffffff
-fbffffff
-fdffffff
-feffffff
-ffffffff
-ffefffff
-fffdffff
-fffeffff
-ffff7fff
-ffffbfff
-ffffdfff
-ffffefff
-fffff7ff
-ffffffff
-fffffdff
-ffffffff
-ffffffff
-ffffffbf
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-8000b503
-40000003
-20000000
-55555554
-feffffff
-fffff7ff
-c1000000
-10800000
-fdffffff
-55755554
-bfffffff
-fffffff9
-00042000
-33333332
-00012000
-0000c000
-00002200
-04001000
-fffffffb
-00000200
-fbffffff
-04000010
-ffffffbf
-40000000
-ffff4afc
-02000010
-01000004
-ffffffff
-ffffdfff
-00300000
-00080003
-00040006
-fffeffff
-aaabaaab
-00001001
-00100800
-00020400
-ffffbfff
-00000085
-0000b505
-0000b505
-fffffffd
-6666f767
-3333b735
-0000b507
-aaaabfaf
-5555f557
-0000b505
-0000b507
-0000b505
-6666f765
-3333b737
-5555f555
-0000b507
-0000b505
-fffffffd
-6666f767
-3333b737
-0000b505
-aaaabfaf
-5555f555
-0000b507
-fffffffd
-ffff4afd
-ffff6eff
-ffff7bfd
-ffff4aff
-ffffeaff
-ffff5fff
-ffff4afd
-ffffffff
-ffff4afd
-ffff6efd
-ffff7bff
-ffff5ffd
-ffff4aff
-fffffffd
-ffff4afd
-ffff6eff
-ffff7bff
-ffff4afd
-ffffeaff
-ffff5ffd
-ffff4aff
-6666f767
-ffff6eff
-66666667
-77777777
-66666667
-eeeeeeef
-77777777
-66666667
-6666f767
-66666667
-66666667
-77777777
-77777777
-66666667
-6666f767
-ffff6eff
-66666667
-77777777
-66666667
-eeeeeeef
-77777777
-66666667
-3333b735
-ffff7bfd
-77777777
-33333334
-33333336
-bbbbbbbf
-77777776
-33333334
-3333b737
-33333334
-77777775
-33333336
-77777774
-33333336
-3333b734
-ffff7bfc
-77777776
-33333337
-33333335
-bbbbbbbe
-77777775
-33333337
-0000b507
-ffff4aff
-66666667
-33333336
-00000006
-aaaaaaaf
-55555556
-00000006
-0000b507
-00000006
-66666667
-33333336
-55555556
-00000006
-0000b506
-ffff4afe
-66666666
-33333337
-00000007
-aaaaaaae
-55555557
-00000007
-aaaabfaf
-ffffeaff
-eeeeeeef
-bbbbbbbf
-aaaaaaaf
-aaaaaaab
-ffffffff
-aaaaaaaf
-aaaabfab
-aaaaaaab
-eeeeeeef
-bbbbbbbb
-ffffffff
-aaaaaaab
-aaaabfaf
-ffffeaff
-eeeeeeef
-bbbbbbbb
-aaaaaaaf
-aaaaaaab
-ffffffff
-aaaaaaab
-5555f557
-ffff5fff
-77777777
-77777776
-55555556
-ffffffff
-55555556
-55555556
-5555f557
-55555556
-77777777
-77777776
-55555556
-55555556
-5555f556
-ffff5ffe
-77777776
-77777777
-55555557
-fffffffe
-55555557
-55555557
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaaf
-55555556
-00000004
-0000b507
-00000004
-66666665
-33333336
-55555554
-00000006
-0000b504
-ffff4afc
-66666666
-33333337
-00000005
-aaaaaaae
-55555555
-00000007
-0000b507
-ffffffff
-6666f767
-3333b737
-0000b507
-aaaabfab
-5555f557
-0000b507
-0000b503
-0000b503
-6666f767
-3333b733
-5555f557
-0000b503
-0000b507
-ffffffff
-6666f767
-3333b733
-0000b507
-aaaabfab
-5555f557
-0000b503
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000003
-6666f765
-ffff6efd
-66666667
-77777775
-66666667
-eeeeeeef
-77777777
-66666665
-6666f767
-66666665
-33333333
-77777777
-33333333
-77777777
-33333333
-3333b737
-ffff7bff
-77777777
-33333333
-33333337
-bbbbbbbb
-77777777
-33333333
-0000b505
-ffff4afd
-66666667
-33333335
-00000007
-aaaaaaaf
-55555557
-00000005
-0000b507
-00000005
-66666665
-33333337
-55555555
-00000007
-0000b505
-ffff4afd
-66666667
-33333337
-00000005
-aaaaaaaf
-55555555
-00000007
-aaaabfaf
-ffffeaff
-eeeeeeef
-bbbbbbbe
-aaaaaaae
-aaaaaaab
-fffffffe
-aaaaaaae
-aaaabfab
-aaaaaaaa
-eeeeeeef
-bbbbbbba
-fffffffe
-aaaaaaaa
-aaaabfae
-ffffeafe
-eeeeeeee
-bbbbbbbb
-aaaaaaaf
-aaaaaaaa
-ffffffff
-aaaaaaab
-5555f555
-ffff5ffd
-77777777
-77777775
-55555557
-ffffffff
-55555557
-55555555
-5555f557
-55555555
-77777775
-77777777
-55555555
-55555557
-5555f555
-ffff5ffd
-77777777
-77777777
-55555555
-ffffffff
-55555555
-55555557
-0000b507
-ffff4aff
-66666667
-33333337
-00000007
-aaaaaaab
-55555557
-00000007
-0000b503
-00000003
-66666667
-33333333
-55555557
-00000003
-0000b507
-ffff4aff
-66666667
-33333333
-00000007
-aaaaaaab
-55555557
-00000003
-66666665
-77777777
-77777775
-66666667
-6666f765
-ffff6efd
-66666667
-77777777
-66666665
-eeeeeeef
-77777775
-66666667
-3333b737
-ffff7bff
-77777777
-33333336
-33333336
-bbbbbbbb
-77777776
-33333336
-3333b733
-33333332
-77777777
-33333332
-77777776
-33333332
-3333b736
-ffff7bfe
-77777776
-33333333
-33333337
-bbbbbbba
-77777777
-33333333
-5555f555
-ffff5ffd
-77777777
-77777774
-55555556
-ffffffff
-55555556
-55555554
-5555f557
-55555554
-77777775
-77777776
-55555554
-55555556
-5555f554
-ffff5ffc
-77777776
-77777777
-55555555
-fffffffe
-55555555
-55555557
-0000b507
-ffff4aff
-66666667
-33333336
-00000006
-aaaaaaab
-55555556
-00000006
-0000b503
-00000002
-66666667
-33333332
-55555556
-00000002
-0000b506
-ffff4afe
-66666666
-33333333
-00000007
-aaaaaaaa
-55555557
-00000003
-0000b505
-fffffffd
-6666f767
-3333b734
-0000b506
-aaaabfaf
-5555f556
-0000b504
-0000b507
-0000b504
-6666f765
-3333b736
-5555f554
-0000b506
-0000b504
-fffffffc
-6666f766
-3333b737
-0000b505
-aaaabfae
-5555f555
-0000b507
-fffffffd
-ffff4afd
-ffff6eff
-ffff7bfc
-ffff4afe
-ffffeaff
-ffff5ffe
-ffff4afc
-ffffffff
-ffff4afc
-ffff6efd
-ffff7bfe
-ffff5ffc
-ffff4afe
-fffffffc
-ffff4afc
-ffff6efe
-ffff7bff
-ffff4afd
-ffffeafe
-ffff5ffd
-ffff4aff
-6666f767
-ffff6eff
-66666667
-77777776
-66666666
-eeeeeeef
-77777776
-66666666
-6666f767
-66666666
-66666667
-77777776
-77777776
-66666666
-6666f766
-ffff6efe
-66666666
-77777777
-66666667
-eeeeeeee
-77777777
-66666667
-3333b737
-ffff7bff
-77777777
-33333337
-33333337
-bbbbbbbb
-77777777
-33333337
-3333b733
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cslli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cslli-01.reference_output
deleted file mode 100644
index 88c5dcee9..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cslli-01.reference_output
+++ /dev/null
@@ -1,86 +0,0 @@
-e0000000
-fffff800
-fffff000
-ffffff80
-7ffffff8
-80000000
-fff80000
-fffffc00
-dfffffe0
-80000000
-fff80000
-fffe0000
-dffffe00
-ffe00000
-f8000000
-fff7fffc
-80000000
-f7ffe000
-e0000000
-f8000000
-fbff8000
-80000000
-ffffbfe0
-80000000
-c0000000
-fffffdf8
-ef800000
-ffffffde
-e0000000
-fd800000
-e8000000
-80000000
-00000000
-00000000
-00000000
-00000000
-00000000
-10000000
-40000000
-20000000
-20000000
-00000000
-10000000
-00000000
-00000000
-08000000
-00000000
-08000000
-00010000
-00000000
-00004000
-00200000
-10000000
-00000000
-00400000
-04000000
-00002000
-00008000
-00000000
-00100000
-00400000
-00800000
-10000000
-00080000
-40000000
-fff7fff0
-5a828000
-fd2bf400
-c0000000
-33333340
-00000030
-55800000
-55555600
-18000000
-18000000
-55555550
-55555550
-00000000
-cccccca0
-33320000
-aa000000
-002d4100
-fd2bf000
-99980000
-66666666
-00000050
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrai-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrai-01.reference_output
deleted file mode 100644
index 44f590c55..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrai-01.reference_output
+++ /dev/null
@@ -1,85 +0,0 @@
-fffeaaaa
-003fffff
-fdffffff
-fdffffff
-ffffff7f
-fffffeff
-ffffbfff
-ffffffff
-fffff7ff
-ffefffff
-ffffefff
-fffffeff
-ffffff7f
-ffffbfff
-ffffbfff
-ffffffff
-ffffffff
-ffffdfff
-ffffff7f
-ffffffff
-ffffffbf
-ffffffff
-ffffff7f
-ffffffff
-fffffffd
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-00000000
-ffffe000
-00002000
-00000004
-00000080
-00000200
-00000020
-00200000
-00000000
-00000000
-00000200
-00000100
-00000002
-00000400
-00000000
-00002000
-00000100
-00000400
-00000000
-00000100
-00000000
-00000002
-00000000
-00000000
-00000000
-00000010
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-2aaaaaaa
-00000005
-fffffa57
-00000333
-00000066
-00000000
-00000000
-00000000
-feaaaaaa
-00002aaa
-00000002
-03333333
-00333333
-00555555
-00000000
-ffffff4a
-00033333
-00000066
-00000002
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrli-01.reference_output
deleted file mode 100644
index 5886c90cf..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csrli-01.reference_output
+++ /dev/null
@@ -1,87 +0,0 @@
-0003ffff
-00ffffff
-00017fff
-001bffff
-000effff
-0f7fffff
-1f7fffff
-00007eff
-03fbffff
-0001feff
-000007fd
-1ffbffff
-3ffbffff
-0000fff7
-03ffefff
-0000fffd
-007fff7f
-007fffbf
-000ffffb
-0003ffff
-07ffff7f
-000007ff
-00000007
-000fffff
-000fffff
-01fffffe
-00000007
-0001ffff
-000fffff
-01ffffff
-00000003
-001fffff
-00000000
-0000001f
-00400000
-00800000
-00800000
-00080000
-00000000
-00000200
-00000010
-00000100
-00000000
-00000400
-00000200
-00000000
-00000000
-00000000
-00000000
-00000100
-00000000
-00000800
-00000000
-00000000
-00000010
-00000000
-00000000
-00000080
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-000007ff
-00333333
-00006666
-00000000
-05555555
-0000aaaa
-00002d40
-00000000
-00000000
-2aaaaaaa
-000aaaaa
-00000000
-00000000
-00019999
-00cccccc
-0aaaaaaa
-00000000
-07fffa57
-0ccccccc
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csub-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csub-01.reference_output
deleted file mode 100644
index 2eb459464..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csub-01.reference_output
+++ /dev/null
@@ -1,581 +0,0 @@
-d5555556
-00000000
-c0000000
-1ffffff7
-0fff4afd
-6e666666
-03fffffa
-f2000000
-00fff800
-33b33333
-00380000
-001ffffd
-000fffc0
-0007ff80
-0003fff9
-02020001
-0000fffd
-40008000
-ffff8afe
-fffc2000
-00001005
-ffffc800
-ffe00400
-01000201
-00000201
-0000007f
-00000081
-0000001e
-ffff8010
-ffffffc8
-00000025
-ffffe002
-fffffc01
-bfffffbf
-e0000005
-78000000
-fc000020
-fe000007
-ff000010
-ff7ff7ff
-bfbfffff
-ffefffff
-fffeb503
-ffff0100
-7ffff000
-fbfffdff
-000fffe0
-000007f0
-fffffff2
-00000001
-5fffffff
-dffffffd
-f000b504
-f8004000
-fe000020
-fefffff7
-01800000
-00000000
-ffe00020
-66566666
-fff6ffff
-fffc0009
-fffe0000
-ffff0009
-ffff8200
-aaaa6aaa
-ffffdff7
-ffffefff
-aaaaa6aa
-00000200
-ffffdeff
-fffffb7f
-ffff7fdf
-fffffff0
-5555554d
-ffff4af8
-fefffffd
-0fffffff
-3fffffe0
-1ffffffe
-07fe0000
-04000011
-f8800000
-00200000
-000ffffc
-f0080000
-00040001
-00020201
-e0010000
-00008008
-10002001
-10001001
-000007fb
-00000088
-ffff4b0d
-00000003
-00000000
-9999999b
-00000000
-00016a08
-999a4e9e
-cccd81d1
-0000b4ff
-55560a5a
-aaab5faf
-0000b501
-00000002
-0000b505
-999a4ea0
-cccd81d3
-aaab5fb1
-0000b503
-00000001
-00016a09
-999a4e9f
-cccd81d2
-0000b500
-55560a5b
-aaab5fb0
-0000b502
-fffe95f8
-00000000
-9998e496
-cccc17c9
-ffff4af7
-5554a052
-aaa9f5a7
-ffff4af9
-fffe95fa
-ffff4afd
-9998e498
-cccc17cb
-aaa9f5a9
-ffff4afb
-fffe95f9
-00000001
-9998e497
-cccc17ca
-ffff4af8
-5554a053
-aaa9f5a8
-ffff4afa
-6665b162
-66671b6a
-00000000
-33333333
-66666661
-bbbbbbbc
-11111111
-66666663
-6665b164
-66666667
-00000002
-33333335
-11111113
-66666665
-6665b163
-66671b6b
-00000001
-33333334
-66666662
-bbbbbbbd
-11111112
-66666664
-33327e2f
-3333e837
-cccccccd
-00000000
-3333332e
-88888889
-ddddddde
-33333330
-33327e31
-33333334
-cccccccf
-00000002
-dddddde0
-33333332
-33327e30
-3333e838
-ccccccce
-00000001
-3333332f
-8888888a
-dddddddf
-33333331
-ffff4b01
-0000b509
-9999999f
-ccccccd2
-00000000
-5555555b
-aaaaaab0
-00000002
-ffff4b03
-00000006
-999999a1
-ccccccd4
-aaaaaab2
-00000004
-ffff4b02
-0000b50a
-999999a0
-ccccccd3
-00000001
-5555555c
-aaaaaab1
-00000003
-aaa9f5a6
-aaab5fae
-44444444
-77777777
-aaaaaaa5
-00000000
-55555555
-aaaaaaa7
-aaa9f5a8
-aaaaaaab
-44444446
-77777779
-55555557
-aaaaaaa9
-aaa9f5a7
-aaab5faf
-44444445
-77777778
-aaaaaaa6
-00000001
-55555556
-aaaaaaa8
-5554a051
-55560a59
-eeeeeeef
-22222222
-55555550
-aaaaaaab
-00000000
-55555552
-5554a053
-55555556
-eeeeeef1
-22222224
-00000002
-55555554
-5554a052
-55560a5a
-eeeeeef0
-22222223
-55555551
-aaaaaaac
-00000001
-55555553
-ffff4aff
-0000b507
-9999999d
-ccccccd0
-fffffffe
-55555559
-aaaaaaae
-00000000
-ffff4b01
-00000004
-9999999f
-ccccccd2
-aaaaaab0
-00000002
-ffff4b00
-0000b508
-9999999e
-ccccccd1
-ffffffff
-5555555a
-aaaaaaaf
-00000001
-fffffffe
-00016a06
-999a4e9c
-cccd81cf
-0000b4fd
-55560a58
-aaab5fad
-0000b4ff
-00000000
-0000b503
-999a4e9e
-cccd81d1
-aaab5faf
-0000b501
-ffffffff
-00016a07
-999a4e9d
-cccd81d0
-0000b4fe
-55560a59
-aaab5fae
-0000b500
-ffff4afb
-0000b503
-99999999
-cccccccc
-fffffffa
-55555555
-aaaaaaaa
-fffffffc
-ffff4afd
-00000000
-9999999b
-ccccccce
-aaaaaaac
-fffffffe
-ffff4afc
-0000b504
-9999999a
-cccccccd
-fffffffb
-55555556
-aaaaaaab
-fffffffd
-6665b160
-66671b68
-fffffffe
-33333331
-6666665f
-bbbbbbba
-1111110f
-33333333
-ccccccce
-00000001
-dddddddf
-33333331
-33327e2f
-3333e837
-cccccccd
-00000000
-3333332e
-88888889
-ddddddde
-33333330
-ffff4b00
-0000b508
-9999999e
-ccccccd1
-ffffffff
-5555555a
-aaaaaaaf
-00000001
-ffff4b02
-00000005
-999999a0
-ccccccd3
-aaaaaab1
-00000003
-ffff4b01
-0000b509
-9999999f
-ccccccd2
-00000000
-5555555b
-aaaaaab0
-00000002
-aaa9f5a5
-aaab5fad
-44444443
-77777776
-aaaaaaa4
-ffffffff
-55555554
-aaaaaaa6
-aaa9f5a7
-aaaaaaaa
-44444445
-77777778
-55555556
-aaaaaaa8
-aaa9f5a6
-aaab5fae
-44444444
-77777777
-aaaaaaa5
-00000000
-55555555
-aaaaaaa7
-5554a050
-55560a58
-eeeeeeee
-22222221
-5555554f
-aaaaaaaa
-ffffffff
-55555551
-5554a052
-55555555
-eeeeeef0
-22222223
-00000001
-55555553
-5554a051
-55560a59
-eeeeeeef
-22222222
-55555550
-aaaaaaab
-00000000
-55555552
-ffff4afe
-0000b506
-9999999c
-cccccccf
-fffffffd
-55555558
-aaaaaaad
-ffffffff
-ffff4b00
-00000003
-9999999e
-ccccccd1
-aaaaaaaf
-00000001
-ffff4aff
-0000b507
-9999999d
-ccccccd0
-fffffffe
-55555559
-aaaaaaae
-00000000
-66666661
-6665b162
-66666665
-00000000
-33333333
-11111111
-66666663
-6665b161
-66671b69
-ffffffff
-33333332
-66666660
-bbbbbbbb
-11111110
-66666662
-33327e2d
-3333e835
-cccccccb
-fffffffe
-3333332c
-88888887
-dddddddc
-3333332e
-33327e2f
-33333332
-cccccccd
-00000000
-ddddddde
-33333330
-33327e2e
-3333e836
-cccccccc
-ffffffff
-3333332d
-88888888
-dddddddd
-3333332f
-5554a04f
-55560a57
-eeeeeeed
-22222220
-5555554e
-aaaaaaa9
-fffffffe
-55555550
-5554a051
-55555554
-eeeeeeef
-22222222
-00000000
-55555552
-5554a050
-55560a58
-eeeeeeee
-22222221
-5555554f
-aaaaaaaa
-ffffffff
-55555551
-ffff4afd
-0000b505
-9999999b
-ccccccce
-fffffffc
-55555557
-aaaaaaac
-fffffffe
-ffff4aff
-00000002
-9999999d
-ccccccd0
-aaaaaaae
-ffff4afe
-0000b506
-9999999c
-cccccccf
-fffffffd
-55555558
-aaaaaaad
-ffffffff
-ffffffff
-00016a07
-999a4e9d
-cccd81d0
-0000b4fe
-55560a59
-aaab5fae
-0000b500
-00000001
-0000b504
-999a4e9f
-cccd81d2
-aaab5fb0
-0000b502
-00000000
-00016a08
-999a4e9e
-cccd81d1
-0000b4ff
-55560a5a
-aaab5faf
-0000b501
-fffe95f7
-ffffffff
-9998e495
-cccc17c8
-ffff4af6
-5554a051
-aaa9f5a6
-fffe95f9
-ffff4afc
-9998e497
-cccc17ca
-aaa9f5a8
-ffff4afa
-fffe95f8
-00000000
-9998e496
-cccc17c9
-ffff4af7
-5554a052
-aaa9f5a7
-ffff4af9
-6665b161
-66671b69
-ffffffff
-33333332
-66666660
-bbbbbbbb
-11111110
-66666662
-6665b163
-66666666
-00000001
-33333334
-11111112
-66666664
-6665b162
-66671b6a
-00000000
-33333333
-66666661
-bbbbbbbc
-11111111
-66666663
-33327e2e
-3333e836
-cccccccc
-ffffffff
-3333332d
-88888888
-dddddddd
-3333332f
-33327e30
-7fffff00
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csw-01.reference_output
deleted file mode 100644
index 92cbdd427..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csw-01.reference_output
+++ /dev/null
@@ -1,68 +0,0 @@
-ffffbfff
-7fffffff
-bfffffff
-dfffffff
-efffffff
-f7ffffff
-fbffffff
-fdffffff
-feffffff
-ff7fffff
-ffbfffff
-ffdfffff
-ffefffff
-fff7ffff
-fffbffff
-fffdffff
-fffeffff
-ffff7fff
-ffffdfff
-ffffefff
-fffff7ff
-fffffbff
-fffffdff
-fffffeff
-ffffff7f
-ffffffbf
-ffffffdf
-ffffffef
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-00008000
-80000000
-40000000
-20000000
-10000000
-08000000
-00000020
-00000010
-00000008
-00000004
-00000002
-00000001
-ffefffff
-00080000
-aaaaaaaa
-55555555
-00000000
-04000000
-02000000
-01000000
-00800000
-00400000
-00200000
-00100000
-00040000
-00020000
-00010000
-00004000
-00002000
-00001000
-00000800
-00000400
-00000200
-00000100
-00000080
-00000040
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cswsp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cswsp-01.reference_output
deleted file mode 100644
index 1997f2f7e..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cswsp-01.reference_output
+++ /dev/null
@@ -1,70 +0,0 @@
-00000003
-7fffffff
-bfffffff
-dfffffff
-8000220c
-f7ffffff
-fbffffff
-fdffffff
-feffffff
-ff7fffff
-ffbfffff
-ffdfffff
-ffefffff
-fff7ffff
-fffbffff
-fffdffff
-fffeffff
-ffff7fff
-ffffbfff
-ffffdfff
-ffffefff
-fffff7ff
-fffffbff
-fffffdff
-fffffeff
-ffffff7f
-ffffffbf
-ffffffdf
-ffffffef
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-ffff7fff
-80000000
-40000000
-20000000
-10000000
-08000000
-04000000
-00000040
-00000020
-00000010
-00000008
-00000004
-00000002
-00000001
-aaaaaaaa
-55555555
-00000000
-02000000
-01000000
-00800000
-00400000
-00200000
-00100000
-00080000
-00040000
-00020000
-00010000
-00008000
-00004000
-00002000
-00001000
-00000800
-00000400
-00000200
-00000100
-00000080
-efffffff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cxor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cxor-01.reference_output
deleted file mode 100644
index 9d9ee5f39..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cxor-01.reference_output
+++ /dev/null
@@ -1,580 +0,0 @@
-7fff7fff
-00000000
-ffffffff
-dfffffdf
-1000b503
-08002000
-0c000000
-02000800
-feefffff
-aa2aaaab
-00440000
-ffdffeff
-00100006
-fff7fff9
-f7fbffff
-00020002
-fffefff6
-00005000
-ffffdffa
-efffefff
-10000800
-fffffbff
-ffbffdff
-00000300
-00000089
-ffffffba
-fff7ffdf
-ffff4aec
-04000008
-00000000
-ffdffffd
-fffdfffe
-7fffffff
-bffdffff
-9fffffff
-fdfffff8
-81000000
-00880000
-ffbffffb
-ffd7ffff
-00100800
-40080000
-02020000
-fffefffb
-00008006
-ffff0afa
-ffbffbff
-fffff6ff
-fbffff7f
-80000040
-00000420
-80000010
-99999992
-fffffff7
-d5555556
-20200000
-10000004
-3b333334
-ffffffff
-54555555
-33b33334
-ffdbffff
-ff6fffff
-aaaeaaaa
-ff7effff
-04008000
-04004000
-55557555
-ffefefff
-00010400
-08000200
-00080100
-ffffff7d
-00000140
-aaaaaa8b
-3fffffef
-ffbffff7
-fffffff4
-fffffffc
-a0000000
-57555555
-32333332
-fe7fffff
-40040000
-6666e666
-ffff9fff
-0000a000
-ffff5afc
-fffff3ff
-00000408
-ffeffdff
-0000b584
-dfffffef
-fefffff7
-00000004
-fffdfffe
-00000000
-fffffff8
-6666d362
-33338631
-0000b503
-aaaa1fae
-5555e053
-0000b501
-00000006
-0000b505
-6666d360
-33338637
-5555e051
-0000b507
-00000001
-fffffff9
-6666d363
-33338636
-0000b500
-aaaa1faf
-5555e050
-0000b506
-fffffff8
-00000000
-99992c9a
-cccc79c9
-ffff4afb
-5555e056
-aaaa1fab
-ffff4af9
-fffffffe
-ffff4afd
-99992c98
-cccc79cf
-aaaa1fa9
-ffff4aff
-fffffff9
-00000001
-99992c9b
-cccc79ce
-ffff4af8
-5555e057
-aaaa1fa8
-ffff4afe
-6666d362
-99992c9a
-00000000
-55555553
-66666661
-cccccccc
-33333331
-66666663
-6666d364
-66666667
-00000002
-55555555
-33333333
-66666665
-6666d363
-99992c9b
-00000001
-55555554
-66666662
-cccccccd
-33333332
-66666664
-33338631
-cccc79c9
-55555553
-00000000
-33333332
-9999999f
-66666662
-33333330
-33338637
-33333334
-55555551
-00000006
-66666660
-33333336
-33338630
-cccc79c8
-55555552
-00000007
-33333331
-9999999e
-66666661
-33333337
-0000b503
-ffff4afb
-66666661
-33333332
-00000000
-aaaaaaad
-55555550
-00000002
-0000b505
-00000006
-66666663
-33333334
-55555552
-00000004
-0000b502
-ffff4afa
-66666660
-33333335
-00000003
-aaaaaaac
-55555553
-00000005
-aaaa1fae
-5555e056
-cccccccc
-9999999f
-aaaaaaad
-00000000
-fffffffd
-aaaaaaaf
-aaaa1fa8
-aaaaaaab
-ccccccce
-99999999
-ffffffff
-aaaaaaa9
-aaaa1faf
-5555e057
-cccccccd
-99999998
-aaaaaaae
-00000001
-fffffffe
-aaaaaaa8
-5555e053
-aaaa1fab
-33333331
-66666662
-55555550
-fffffffd
-00000000
-55555552
-5555e055
-55555556
-33333333
-66666664
-00000002
-55555554
-5555e052
-aaaa1faa
-33333330
-66666665
-55555553
-fffffffc
-00000003
-55555555
-0000b501
-ffff4af9
-66666663
-33333330
-00000002
-aaaaaaaf
-55555552
-00000000
-0000b507
-00000004
-66666661
-33333336
-55555550
-00000006
-0000b500
-ffff4af8
-66666662
-33333337
-00000001
-aaaaaaae
-55555551
-00000007
-00000006
-fffffffe
-6666d364
-33338637
-0000b505
-aaaa1fa8
-5555e055
-0000b507
-00000000
-0000b503
-6666d366
-33338631
-5555e057
-0000b501
-00000007
-ffffffff
-6666d365
-33338630
-0000b506
-aaaa1fa9
-5555e056
-0000b500
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000003
-6666d360
-99992c98
-00000002
-55555551
-66666663
-ccccccce
-33333333
-66666661
-33333333
-55555556
-00000001
-66666667
-33333331
-33338637
-cccc79cf
-55555555
-00000000
-33333336
-99999999
-66666666
-33333330
-0000b500
-ffff4af8
-66666662
-33333331
-00000003
-aaaaaaae
-55555553
-00000001
-0000b506
-00000005
-66666660
-33333337
-55555551
-00000007
-0000b501
-ffff4af9
-66666663
-33333336
-00000000
-aaaaaaaf
-55555550
-00000006
-aaaa1faf
-5555e057
-cccccccd
-9999999e
-aaaaaaac
-00000001
-fffffffc
-aaaaaaae
-aaaa1fa9
-aaaaaaaa
-cccccccf
-99999998
-fffffffe
-aaaaaaa8
-aaaa1fae
-5555e056
-cccccccc
-99999999
-aaaaaaaf
-00000000
-ffffffff
-aaaaaaa9
-5555e050
-aaaa1fa8
-33333332
-66666661
-55555553
-fffffffe
-00000003
-55555551
-5555e056
-55555555
-33333330
-66666667
-00000001
-55555557
-5555e051
-aaaa1fa9
-33333333
-66666666
-55555550
-ffffffff
-00000000
-55555556
-0000b506
-ffff4afe
-66666664
-33333337
-00000005
-aaaaaaa8
-55555555
-00000007
-0000b500
-00000003
-66666666
-33333331
-55555557
-00000001
-0000b507
-ffff4aff
-66666665
-33333330
-00000006
-aaaaaaa9
-55555556
-00000000
-6666d366
-66666665
-00000000
-55555557
-33333331
-66666667
-6666d361
-99992c99
-00000003
-55555556
-66666660
-cccccccf
-33333330
-66666666
-33338637
-cccc79cf
-55555555
-00000006
-33333334
-99999999
-66666664
-33333336
-33338631
-33333332
-55555557
-00000000
-66666666
-33333330
-33338636
-cccc79ce
-55555554
-00000001
-33333337
-99999998
-66666667
-33333331
-5555e051
-aaaa1fa9
-33333333
-66666660
-55555552
-ffffffff
-00000002
-55555550
-5555e057
-55555554
-33333331
-66666666
-00000000
-55555556
-5555e050
-aaaa1fa8
-33333332
-66666667
-55555551
-fffffffe
-00000001
-55555557
-0000b507
-ffff4aff
-66666665
-33333336
-aaaaaaa9
-55555554
-00000006
-0000b501
-00000002
-66666667
-33333330
-55555556
-00000000
-0000b506
-ffff4afe
-66666664
-33333331
-00000007
-aaaaaaa8
-55555557
-00000001
-00000001
-fffffff9
-6666d363
-33338630
-0000b502
-aaaa1faf
-5555e052
-0000b500
-00000007
-0000b504
-6666d361
-33338636
-5555e050
-0000b506
-00000000
-fffffff8
-6666d362
-33338637
-0000b501
-aaaa1fae
-5555e051
-0000b507
-fffffff9
-00000001
-99992c9b
-cccc79c8
-ffff4afa
-5555e057
-aaaa1faa
-ffff4af8
-ffffffff
-ffff4afc
-99992c99
-cccc79ce
-aaaa1fa8
-ffff4afe
-fffffff8
-00000000
-99992c9a
-cccc79cf
-ffff4af9
-5555e056
-aaaa1fa9
-ffff4aff
-6666d363
-99992c9b
-00000001
-55555552
-66666660
-cccccccd
-33333330
-66666662
-6666d365
-66666666
-00000003
-55555554
-33333332
-66666664
-6666d362
-99992c9a
-00000000
-55555555
-66666663
-cccccccc
-33333333
-66666665
-33338636
-cccc79ce
-55555554
-00000007
-33333335
-99999998
-66666665
-33333337
-33338630
-7fffffbf
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output
deleted file mode 100644
index 68ea59019..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output
+++ /dev/null
@@ -1,581 +0,0 @@
-00000000
-00000000
-00000001
-00000001
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-fffffd56
-00000000
-00000000
-00000000
-00000001
-00000000
-fffffe01
-00000000
-00000000
-00000000
-00000000
-00000000
-00001ff0
-ffccffcd
-0000003f
-ff03f040
-00f83e0f
-fffc3c3d
-0038e38e
-00019999
-000aaaab
-fc000000
-ffffffc1
-00007fff
-fffe0000
-02aaaaab
-00000001
-0000003f
-ffff8000
-00000000
-00000000
-00000000
-00000000
-00000007
-000000e3
-00000092
-00000000
-00000081
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000333
-00000000
-00000000
-00000000
-0000aaaa
-00000000
-00000000
-00033333
-00000000
-00000008
-00000004
-00000002
-00000000
-08000000
-00000002
-40000000
-ffffffff
-00000000
-00000100
-00000000
-fffff002
-00000000
-fffffe01
-00000000
-00000040
-00002aaa
-00000000
-fffffff1
-00000000
-00000000
-00000020
-00000000
-00000001
-ffffffff
-00000000
-00000000
-00001e2b
-00000000
-00000000
-00002d41
-00000001
-ffffffff
-00000000
-00000000
-00000000
-00005a82
-00000001
-ffffffff
-00000000
-00000000
-00002434
-00000000
-00000000
-00003c57
-00000000
-00000001
-00000000
-00000000
-ffffe1d5
-00000000
-00000000
-ffffd2c0
-ffffffff
-ffffffff
-00000000
-00000000
-00000000
-ffffa57f
-00000000
-00000000
-00000000
-00000000
-ffffdbcd
-00000000
-00000000
-ffffc3aa
-000090d0
-ffff6f2e
-00000001
-00000001
-11111111
-ffffffff
-00000001
-19999999
-000090d2
-ffffffff
-00000001
-00000002
-00000001
-33333333
-000090d1
-ffff6f2f
-00000001
-00000002
-147ae147
-ffffffff
-00000001
-22222222
-00004868
-ffffb797
-00000000
-00000001
-08888888
-00000000
-00000000
-0ccccccd
-00004869
-ffffffff
-00000000
-00000001
-00000000
-1999999a
-00004868
-ffffb798
-00000000
-00000001
-0a3d70a4
-00000000
-00000000
-11111111
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000003
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-ffff8753
-000078af
-00000000
-ffffffff
-f1c71c72
-00000001
-00000000
-eaaaaaab
-ffff8751
-ffffffff
-00000000
-ffffffff
-ffffffff
-d5555556
-ffff8752
-000078ae
-00000000
-ffffffff
-eeeeeeef
-00000000
-ffffffff
-e38e38e4
-000078ad
-ffff8751
-00000000
-00000001
-0e38e38e
-ffffffff
-00000001
-15555555
-000078af
-ffffffff
-00000000
-00000001
-00000001
-2aaaaaab
-000078ae
-ffff8752
-00000000
-00000001
-11111111
-ffffffff
-00000001
-1c71c71c
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000002
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00001e2b
-00000000
-00000000
-00002d40
-00000001
-ffffffff
-00000000
-00000000
-00000000
-00005a81
-00000000
-00000000
-00000000
-00000000
-00002433
-00000000
-00000000
-00003c56
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-000090d0
-ffff6f2e
-00000000
-00000001
-11111110
-ffffffff
-00000001
-19999999
-000090d2
-ffffffff
-00000000
-00000001
-00000000
-19999999
-00004868
-ffffb798
-00000000
-00000001
-0a3d70a3
-00000000
-00000000
-11111111
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-ffff8753
-000078af
-00000000
-ffffffff
-f1c71c72
-00000001
-ffffffff
-eaaaaaab
-ffff8751
-ffffffff
-00000000
-ffffffff
-ffffffff
-d5555555
-ffff8752
-000078ae
-00000000
-ffffffff
-eeeeeeef
-00000001
-ffffffff
-e38e38e4
-000078ad
-ffff8751
-00000000
-00000001
-0e38e38e
-ffffffff
-00000000
-15555555
-000078af
-ffffffff
-00000000
-00000001
-00000001
-2aaaaaaa
-000078ae
-ffff8752
-00000000
-00000001
-11111111
-00000000
-00000001
-1c71c71c
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-ffffffff
-00000001
-00000002
-00000001
-33333332
-000090d1
-ffff6f2f
-00000000
-00000001
-147ae147
-ffffffff
-00000001
-22222221
-00004868
-ffffb797
-00000000
-00000000
-08888888
-00000000
-00000000
-0ccccccc
-00004869
-ffffffff
-00000000
-00000001
-00000000
-19999999
-00004868
-ffffb798
-00000000
-00000000
-0a3d70a3
-00000000
-00000000
-11111110
-000078ad
-ffff8751
-00000000
-00000001
-0e38e38e
-00000000
-00000000
-15555555
-000078af
-ffffffff
-00000000
-00000001
-00000001
-2aaaaaaa
-000078ae
-ffff8752
-00000000
-00000001
-11111110
-00000000
-00000000
-1c71c71c
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00001e2b
-00000000
-00000000
-00002d41
-00000001
-ffffffff
-00000000
-00000000
-00000000
-00005a82
-00000001
-ffffffff
-00000000
-00000000
-00002434
-00000000
-00000000
-00003c56
-00000000
-00000001
-00000000
-00000000
-ffffe1d5
-00000000
-00000000
-ffffd2bf
-ffffffff
-ffffffff
-00000000
-00000000
-00000000
-ffffa57e
-ffffffff
-00000001
-00000000
-00000000
-ffffdbcc
-00000000
-00000000
-ffffc3aa
-000090d0
-ffff6f2e
-00000000
-00000001
-11111111
-ffffffff
-00000001
-19999999
-000090d2
-ffffffff
-00000001
-00000002
-00000001
-33333333
-000090d1
-ffff6f2f
-00000001
-00000002
-147ae147
-ffffffff
-00000001
-22222222
-00004868
-ffffb797
-00000000
-00000000
-08888888
-00000000
-00000000
-0ccccccc
-00004869
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output
deleted file mode 100644
index 76f0e23b0..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output
+++ /dev/null
@@ -1,729 +0,0 @@
-00000000
-00000000
-00000001
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-3fffffff
-00000000
-0001536c
-00000000
-00000007
-00000001
-00000002
-0000003f
-00000001
-2aa7ffff
-33326666
-0f0effff
-00000000
-1ffff7ff
-00000001
-00000000
-249248db
-00000002
-24924922
-00000001
-3ffffffe
-00000002
-00000001
-00000000
-00000000
-0000007f
-00000055
-00000008
-00000000
-00000000
-00000000
-00000aaa
-00000000
-00001999
-0000ffff
-0001ffff
-00002000
-00000000
-000fffff
-00000040
-00000080
-00000800
-00efffff
-0000016a
-00000000
-01000000
-0fffefff
-7fffffdf
-00080000
-0ba2e8ba
-00040000
-00001000
-00000000
-00800000
-00000000
-00000000
-00000000
-00000000
-00000666
-000000f0
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00010000
-00000001
-00000000
-00000000
-00002aaa
-00000000
-00000000
-00004000
-00000001
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000000
-00008000
-00000001
-00000001
-00000000
-00000000
-00003333
-00000000
-00000000
-00005555
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-0000b505
-00000001
-00000000
-00000000
-00001e2b
-00000000
-00000000
-00002d41
-00000000
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000000
-00005a82
-00000000
-00000001
-00000000
-00000000
-00002434
-00000000
-00000000
-00003c57
-00006666
-66666667
-000090d0
-00000001
-00000001
-11111111
-00000000
-00000001
-19999999
-00006667
-ffffffff
-000090d2
-00000001
-00000002
-00000000
-00000001
-33333333
-00006666
-000090d1
-00000001
-00000002
-147ae147
-00000000
-00000001
-22222222
-00003333
-33333334
-00004868
-00000000
-00000001
-08888888
-00000000
-00000000
-0ccccccd
-00003333
-ffffffff
-00004869
-00000000
-00000001
-00000000
-00000000
-1999999a
-00003333
-00004868
-00000000
-00000001
-0a3d70a4
-00000000
-00000000
-11111111
-00000000
-00000006
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000003
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-0000aaaa
-aaaaaaab
-0000f15b
-00000001
-00000003
-1c71c71c
-00000001
-00000001
-2aaaaaaa
-0000aaac
-ffffffff
-0000f15e
-00000001
-00000003
-00000001
-00000002
-55555555
-0000aaab
-0000f15d
-00000001
-00000003
-22222222
-00000001
-00000002
-38e38e39
-00005555
-55555556
-000078ad
-00000000
-00000001
-0e38e38e
-00000000
-00000001
-15555555
-00005556
-ffffffff
-000078af
-00000000
-00000001
-00000000
-00000001
-2aaaaaab
-00005555
-000078ae
-00000000
-00000001
-11111111
-00000000
-00000001
-1c71c71c
-00000000
-00000004
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000002
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-0000fffe
-00000001
-00000000
-00000000
-00002aaa
-00000000
-00000000
-00003fff
-00000001
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000000
-00007fff
-00000000
-00000001
-00000000
-00000000
-00003332
-00000000
-00000000
-00005554
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-0000b503
-00000000
-00000000
-00000000
-00001e2b
-00000000
-00000000
-00002d40
-00000000
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000000
-00005a81
-00000000
-00000000
-00000000
-00000000
-00002433
-00000000
-00000000
-00003c56
-00006666
-66666665
-000090d0
-00000000
-00000001
-11111110
-00000000
-00000001
-19999999
-00006667
-ffffffff
-000090d2
-00000001
-00000002
-00000000
-00000001
-33333332
-00006666
-000090d1
-00000000
-00000001
-147ae147
-00000000
-00000001
-22222221
-00003333
-33333332
-00004868
-00000000
-00000000
-08888888
-00000000
-00000000
-0ccccccc
-00003333
-ffffffff
-00004869
-00000000
-00000001
-00000000
-00000000
-19999999
-00003333
-00004868
-00000000
-00000000
-0a3d70a3
-00000000
-00000000
-11111110
-0000aaaa
-aaaaaaa9
-0000f15b
-00000001
-00000003
-1c71c71c
-00000000
-00000001
-2aaaaaaa
-0000aaac
-ffffffff
-0000f15e
-00000001
-00000003
-00000001
-00000002
-55555554
-0000aaab
-0000f15d
-00000001
-00000003
-15555555
-00005556
-ffffffff
-000078af
-00000000
-00000001
-00000000
-00000001
-2aaaaaaa
-00005555
-000078ae
-00000000
-00000001
-11111110
-00000000
-00000000
-1c71c71c
-00000000
-00000002
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-0000ffff
-00000001
-00000000
-00000000
-00002aaa
-00000000
-00000000
-00003fff
-00000001
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000000
-00007fff
-00000001
-00000001
-00000000
-00000000
-00003333
-00000000
-00000000
-00005555
-00000000
-0000b504
-00000000
-00000000
-00000000
-00001e2b
-00000000
-00000000
-00002d41
-00000000
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000000
-00005a82
-00000000
-00000001
-00000000
-00000000
-00002434
-00000000
-00000000
-00003c56
-00006666
-66666666
-000090d0
-00000000
-00000001
-11111111
-00000000
-00000001
-19999999
-00006667
-ffffffff
-000090d2
-00000001
-00000002
-00000000
-00000001
-33333333
-00006666
-000090d1
-00000001
-00000002
-147ae147
-00000000
-00000001
-22222222
-00003333
-33333333
-00004868
-00000000
-00000000
-08888888
-00000000
-00000000
-0ccccccc
-00003333
-ffffffff
-38e38e38
-00004869
-00000000
-00000001
-00000000
-00000000
-19999999
-00003333
-00004868
-00000000
-00000001
-0a3d70a3
-00000000
-00000000
-11111111
-00000000
-00000005
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000002
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-0000aaaa
-aaaaaaaa
-0000f15b
-00000001
-00000003
-1c71c71c
-00000000
-00000001
-2aaaaaaa
-0000aaac
-ffffffff
-0000f15e
-00000001
-00000003
-00000001
-00000002
-55555555
-0000aaab
-0000f15d
-00000001
-00000003
-22222222
-00000001
-00000002
-38e38e38
-00005555
-55555555
-000078ad
-00000000
-00000001
-0e38e38e
-00000000
-00000000
-15555555
-00005556
-ffffffff
-000078af
-00000000
-00000001
-00000000
-00000001
-2aaaaaaa
-00005555
-000078ae
-00000000
-00000001
-11111111
-00000000
-00000001
-1c71c71c
-00000000
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-22222221
-00000000
-00000001
-00005555
-55555554
-000078ad
-00000000
-00000001
-0e38e38e
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output
deleted file mode 100644
index 66fcf6049..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output
+++ /dev/null
@@ -1,585 +0,0 @@
-00000002
-2aaaaaab
-00000000
-00000040
-10000101
-00000000
-04080001
-edfffff7
-00000000
-00000000
-00000000
-666ccccd
-00000000
-01080001
-0001999a
-feffff80
-aaab5556
-00108001
-fffbfff0
-08002001
-02001001
-ffffc7f9
-f0000000
-cccccb99
-00000404
-ffbf8000
-04100041
-e0000000
-aaaaaaa5
-80000009
-ffffffe2
-00000033
-00000000
-fffc0000
-5ffffffb
-4aaaaaaa
-ffff0000
-c0800001
-ffcccccc
-00220001
-00044001
-000a0001
-10011001
-fffe0000
-80000000
-00202001
-00001001
-00000aac
-fffffccc
-fffffbfe
-fffdfc00
-ffd209fc
-000000a5
-ffffffb8
-fffffff1
-00000018
-fffffff0
-00000000
-00000000
-f0000000
-00000000
-00000000
-ec000000
-ff000000
-99800000
-01800000
-00000000
-00000000
-fff80000
-02000000
-00000000
-00020000
-fffff000
-fa57e000
-00000a00
-fffff600
-00020000
-00000000
-000000c0
-00000040
-04000000
-fffffffb
-80000000
-00000000
-fc000000
-06000000
-ff800000
-ffc00000
-00000000
-00140000
-6a080000
-00100000
-08000000
-00100000
-00000000
-fffff200
-55555540
-0000000c
-ffffffdf
-80001219
-800157f1
-6666d303
-3333c404
-00043e1e
-00003c57
-000078ae
-0002d414
-7ffea80f
-00000000
-666568f9
-333259fa
-ffff0ea4
-00016a0a
-7fff5d14
-8000a2ec
-66661dfe
-33330eff
-00038919
-ffff8752
-ffffc3a9
-00021f0f
-800157f1
-7ffd3e09
-6665f9cb
-3332a264
-fffbc1ee
-555518ff
-aaaa31fe
-fffd2bf4
-8002c1f7
-00000000
-666763d1
-33340c6a
-aaab9c04
-fffe95fa
-80020cf4
-7ffdf30c
-6666aece
-33335767
-fffc76f1
-5555ce02
-aaaae701
-fffde0f7
-6666d303
-6665f9cb
-d70a3d71
-1eb851ec
-6666666a
-cccccccd
-9999999a
-9999999c
-999a0635
-00000000
-0a3d70a3
-51eb851e
-cccccccc
-ccccccce
-00006c9c
-ffff9364
-70a3d70a
-b851eb85
-00000003
-66666666
-33333333
-33333335
-3333c404
-3332a264
-1eb851ec
-28f5c290
-33333338
-bbbbbbbc
-77777778
-ccccccd0
-cccd5d9c
-00000000
-b851eb84
-c28f5c28
-11111110
-66666668
-000090d0
-ffff6f30
-eb851eb8
-f5c28f5c
-00000004
-88888888
-44444444
-9999999c
-00043e1e
-fffbc1ee
-6666666a
-33333338
-00000024
-00000004
-00000018
-00043e12
-00000000
-6666665e
-3333332c
-fffffff8
-0000000c
-00043e18
-fffbc1e8
-66666664
-33333332
-0000001e
-fffffffc
-fffffffe
-00000012
-00003c57
-555518ff
-cccccccd
-bbbbbbbc
-00000002
-38e38e39
-71c71c72
-aaaaaaac
-aaaae701
-00000000
-77777777
-66666666
-1c71c71c
-55555556
-555591ac
-aaaa6e54
-22222222
-11111111
-55555557
-8e38e38e
-c71c71c7
-00000001
-000078ae
-aaaa31fe
-9999999a
-77777778
-00000004
-71c71c72
-e38e38e4
-55555558
-5555ce02
-00000000
-eeeeeeee
-cccccccc
-38e38e38
-aaaaaaac
-aaab2358
-5554dca8
-44444444
-22222222
-aaaaaaae
-1c71c71c
-8e38e38e
-00000002
-0002d414
-fffd2bf4
-9999999c
-ccccccd0
-00000018
-aaaaaaac
-55555558
-00000010
-0002d40c
-00000000
-99999994
-ccccccc8
-55555550
-00000008
-0002d410
-fffd2bf0
-99999998
-cccccccc
-00000014
-aaaaaaa8
-55555554
-0000000c
-7ffea80f
-8002c1f7
-999a0635
-cccd5d9c
-00043e12
-aaaae701
-5555ce02
-0002d40c
-7ffd3e09
-00000000
-99989c2f
-cccbf396
-555463fc
-00016a06
-7ffdf30c
-80020cf4
-99995132
-cccca899
-0003890f
-aaaa31fe
-555518ff
-00021f09
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-666568f9
-666763d1
-0a3d70a3
-b851eb84
-6666665e
-77777777
-eeeeeeee
-99999994
-00000000
-51eb851f
-8f5c28f6
-bbbbbbbc
-66666666
-ffffdbcc
-00002434
-851eb852
-c28f5c29
-ffffffff
-ddddddde
-eeeeeeef
-99999999
-00038919
-fffc76f1
-00000003
-00000004
-0000001e
-55555557
-aaaaaaae
-00000014
-0003890f
-00000000
-fffffff9
-fffffffa
-aaaaaaa4
-0000000a
-00038914
-fffc76ec
-fffffffe
-ffffffff
-00000019
-55555552
-aaaaaaa9
-0000000f
-ffff8752
-5555ce02
-66666666
-88888888
-fffffffc
-8e38e38e
-1c71c71c
-aaaaaaa8
-aaaa31fe
-00000000
-11111112
-33333334
-c71c71c8
-55555554
-5554dca8
-aaab2358
-bbbbbbbc
-ddddddde
-55555552
-e38e38e4
-71c71c72
-fffffffe
-ffffc3a9
-aaaae701
-33333333
-44444444
-fffffffe
-c71c71c7
-8e38e38e
-55555554
-555518ff
-00000000
-88888889
-9999999a
-e38e38e4
-aaaaaaaa
-aaaa6e54
-555591ac
-ddddddde
-eeeeeeef
-aaaaaaa9
-71c71c72
-38e38e39
-ffffffff
-00021f0f
-fffde0f7
-33333335
-9999999c
-00000012
-00000001
-00000002
-0000000c
-00021f09
-00000000
-3333332f
-99999996
-fffffffc
-00000006
-00021f0c
-fffde0f4
-33333332
-99999999
-0000000f
-fffffffe
-ffffffff
-00000009
-99989c2f
-00000000
-3d70a3d9
-eb851eba
-22222224
-ccccccca
-ffff0294
-0000fd6c
-a3d70a3e
-51eb851f
-fffffff9
-11111112
-88888889
-3333332f
-333259fa
-33340c6a
-51eb851e
-c28f5c28
-3333332c
-66666666
-cccccccc
-ccccccc8
-cccbf396
-00000000
-eb851eba
-5c28f5c4
-66666668
-66666664
-ffff26c8
-0000d938
-1eb851ec
-8f5c28f6
-fffffffa
-33333334
-9999999a
-99999996
-ffff0ea4
-aaab9c04
-cccccccc
-11111110
-fffffff8
-1c71c71c
-38e38e38
-55555550
-555463fc
-00000000
-22222224
-66666668
-8e38e390
-aaaaaaa8
-aaa9b950
-555646b0
-77777778
-bbbbbbbc
-aaaaaaa4
-c71c71c8
-e38e38e4
-fffffffc
-00016a0a
-fffe95fa
-ccccccce
-66666668
-55555556
-aaaaaaac
-00000008
-00016a06
-00000000
-ccccccca
-66666664
-aaaaaaa8
-00000004
-00016a08
-fffe95f8
-cccccccc
-66666666
-0000000a
-55555554
-aaaaaaaa
-00000006
-7fff5d14
-80020cf4
-00006c9c
-000090d0
-00043e18
-555591ac
-aaab2358
-0002d410
-7ffdf30c
-00000000
-ffff0294
-ffff26c8
-aaa9b950
-00016a08
-7ffea810
-800157f0
-ffffb798
-ffffdbcc
-00038914
-5554dca8
-aaaa6e54
-00021f0c
-8000a2ec
-7ffdf30c
-ffff9364
-ffff6f30
-fffbc1e8
-aaaa6e54
-5554dca8
-fffd2bf0
-80020cf4
-00000000
-0000fd6c
-0000d938
-555646b0
-fffe95f8
-800157f0
-7ffea810
-00004868
-00002434
-fffc76ec
-aaab2358
-555591ac
-fffde0f4
-66661dfe
-6666aece
-70a3d70a
-eb851eb8
-66666664
-22222222
-44444444
-99999998
-99995132
-00000000
-a3d70a3e
-1eb851ec
-77777778
-cccccccc
-ffffb798
-00004868
-0a3d70a4
-851eb852
-fffffffe
-bbbbbbbc
-ddddddde
-33333332
-33330eff
-33335767
-b851eb85
-f5c28f5c
-33333332
-11111111
-22222222
-cccccccc
-cccca899
-f8000000
-fffffff8
-fb7ffff7
-f7ffffe0
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output
deleted file mode 100644
index dba60c2eb..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output
+++ /dev/null
@@ -1,591 +0,0 @@
-ffffffff
-00005a81
-3fffffff
-00001000
-fccccccc
-fffffa57
-00000000
-00080000
-00000000
-ffdfffff
-ffefffff
-00040000
-fffccccc
-00000002
-fffffbff
-00000000
-ffffdfff
-fffff333
-fffff999
-ffffffff
-00000000
-ffffffff
-ffffffff
-ffffffff
-fffffff7
-00000000
-ffffffff
-ffffffff
-ffffffff
-00000000
-00000000
-00000000
-000016a0
-fffff4af
-000002d4
-ff555555
-00002000
-ffe66666
-00000000
-ffffffff
-00000000
-fffeaaaa
-00000020
-ffffaaaa
-00000000
-fffffd55
-ffffffff
-00000002
-00000000
-ffffffd5
-00000015
-00000000
-ffffffff
-ffffffff
-ffffffff
-00000000
-00000000
-20000000
-00000001
-00000080
-ffbfffff
-fff7ffff
-00cccccc
-00200000
-00555555
-00000000
-00000016
-00000000
-0003ffff
-00000000
-ffffffff
-00000000
-00000fff
-00000002
-ffffffff
-fffffe00
-00000040
-00000000
-00000000
-ffffffff
-0000000c
-ffffffff
-ffffffff
-ffffffff
-00000000
-00005a81
-00000000
-00000001
-ffffffff
-ffaaaaaa
-ffd55555
-00080000
-00000000
-00000000
-00000000
-00000100
-ffffefff
-ffffffbf
-fffffaaa
-0000001f
-00000019
-fffffff8
-00000000
-00000000
-ffffffff
-00004868
-00002434
-00000000
-ffffc3a9
-00003c57
-00000000
-00000000
-00000000
-00004868
-00002434
-00003c56
-00000000
-00000000
-ffffffff
-00004868
-00002434
-00000000
-ffffc3a8
-00003c56
-00000000
-ffffffff
-00000000
-ffffb798
-ffffdbcc
-ffffffff
-00003c56
-ffffc3a9
-ffffffff
-ffffffff
-00000000
-ffffb798
-ffffdbcc
-ffffc3a9
-ffffffff
-ffffffff
-00000000
-ffffb798
-ffffdbcc
-ffffffff
-00003c56
-ffffc3a9
-ffffffff
-00004868
-ffffb798
-28f5c28f
-147ae148
-00000002
-dddddddd
-22222222
-00000001
-00004867
-00000000
-28f5c28f
-147ae147
-22222221
-00000000
-00004868
-ffffb797
-28f5c28f
-147ae147
-00000002
-dddddddd
-22222222
-00000001
-00002434
-ffffdbcc
-147ae148
-0a3d70a4
-00000001
-eeeeeeee
-11111111
-00000000
-00002433
-00000000
-147ae147
-0a3d70a3
-11111111
-00000000
-00002434
-ffffdbcb
-147ae147
-0a3d70a3
-00000001
-eeeeeeee
-11111111
-00000000
-00000000
-ffffffff
-00000002
-00000001
-00000000
-fffffffe
-00000002
-00000000
-00000000
-00000000
-00000002
-00000001
-00000001
-00000000
-00000000
-ffffffff
-00000002
-00000001
-00000000
-fffffffd
-00000001
-00000000
-ffffc3a9
-00003c56
-dddddddd
-eeeeeeee
-fffffffe
-1c71c71c
-e38e38e3
-fffffffe
-ffffc3a9
-00000000
-ddddddde
-eeeeeeef
-e38e38e4
-ffffffff
-ffffc3a9
-00003c56
-ddddddde
-eeeeeeef
-fffffffe
-1c71c71c
-e38e38e3
-ffffffff
-00003c57
-ffffc3a9
-22222222
-11111111
-00000002
-e38e38e3
-1c71c71c
-00000001
-00003c56
-00000000
-22222221
-11111110
-1c71c71c
-00000000
-00003c56
-ffffc3a9
-22222222
-11111111
-00000001
-e38e38e3
-1c71c71c
-00000001
-00000000
-ffffffff
-00000001
-00000000
-00000000
-fffffffe
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-ffffffff
-00000001
-00000000
-00000000
-fffffffe
-00000001
-00000000
-00000000
-ffffffff
-00004867
-00002433
-00000000
-ffffc3a9
-00003c56
-00000000
-00000000
-00000000
-00004867
-00002433
-00003c56
-00000000
-00000000
-ffffffff
-00004867
-00002433
-00000000
-ffffc3a9
-00003c56
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00004868
-ffffb798
-28f5c28f
-147ae147
-00000002
-ddddddde
-22222221
-00000001
-00004867
-00000000
-00000000
-147ae147
-0a3d70a3
-11111110
-00000000
-00002433
-ffffdbcc
-147ae147
-0a3d70a3
-00000000
-eeeeeeee
-11111110
-00000000
-00000000
-ffffffff
-00000002
-00000001
-00000000
-fffffffe
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-ffffffff
-00000001
-00000000
-00000000
-fffffffe
-00000001
-00000000
-ffffc3a8
-00003c56
-dddddddd
-eeeeeeee
-fffffffd
-1c71c71c
-e38e38e3
-fffffffe
-ffffc3a9
-00000000
-ddddddde
-eeeeeeef
-e38e38e3
-ffffffff
-ffffc3a9
-00003c56
-dddddddd
-eeeeeeee
-fffffffe
-1c71c71c
-e38e38e3
-fffffffe
-00003c56
-ffffc3a9
-22222222
-11111111
-00000001
-e38e38e3
-1c71c71c
-00000001
-00003c56
-00000000
-22222221
-11111110
-1c71c71b
-00000000
-00003c56
-ffffc3a9
-22222221
-11111110
-00000001
-e38e38e3
-1c71c71c
-00000000
-00000000
-ffffffff
-00000001
-00000000
-00000000
-ffffffff
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000001
-00000000
-00000000
-fffffffe
-00000000
-00000000
-28f5c28e
-147ae146
-22222221
-00000000
-00004867
-ffffb798
-28f5c28e
-147ae147
-00000001
-ddddddde
-22222221
-00000001
-00002434
-ffffdbcc
-147ae147
-0a3d70a3
-00000001
-eeeeeeef
-11111110
-00000000
-00002433
-00000000
-147ae146
-0a3d70a3
-11111110
-00000000
-00002433
-ffffdbcc
-147ae147
-0a3d70a3
-00000000
-eeeeeeef
-11111110
-00000000
-00003c56
-ffffc3a9
-22222221
-11111111
-00000001
-e38e38e4
-1c71c71c
-00000001
-00003c56
-00000000
-22222221
-11111110
-1c71c71b
-00000000
-00003c56
-ffffc3a9
-22222221
-11111110
-00000001
-e38e38e3
-1c71c71b
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-ffffffff
-00000000
-00000000
-00000000
-ffffffff
-00004868
-00002434
-00000000
-ffffc3a9
-00003c56
-00000000
-00000000
-00000000
-00004867
-00002433
-00003c56
-00000000
-00000000
-ffffffff
-00004867
-00002433
-00000000
-ffffc3a9
-00003c56
-00000000
-ffffffff
-00000000
-ffffb797
-ffffdbcb
-ffffffff
-00003c56
-ffffc3a9
-ffffffff
-ffffffff
-00000000
-ffffb798
-ffffdbcc
-ffffc3a9
-ffffffff
-ffffffff
-00000000
-ffffb798
-ffffdbcc
-ffffffff
-00003c56
-ffffc3a9
-ffffffff
-00004868
-ffffb798
-28f5c28f
-147ae147
-00000002
-ddddddde
-22222222
-00000001
-00004867
-00000000
-28f5c28e
-147ae147
-22222221
-00000000
-00004867
-ffffb798
-28f5c28f
-147ae147
-00000001
-dddddddd
-22222221
-00000001
-00002434
-ffffdbcc
-147ae147
-0a3d70a3
-00000001
-eeeeeeef
-11111111
-00000000
-00002433
-00080000
-00000020
-ffffffff
-ffff9999
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output
deleted file mode 100644
index 197dc32c5..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output
+++ /dev/null
@@ -1,654 +0,0 @@
-0000aaaa
-d5555555
-00000100
-00000000
-fffffff0
-00000000
-fffffc0f
-00000001
-fffffffe
-0007fbff
-000001ff
-554aaaaa
-55500000
-fffffbff
-c000ffff
-00000000
-fffffffb
-0000b503
-00000002
-fffffff9
-0000b504
-aaaaad55
-fffffffe
-fffeffff
-03fffffb
-66666632
-00000002
-66666658
-00000005
-efffffff
-ffff4afd
-00000003
-f7ffffff
-7ff7fffe
-fffffffe
-ffffffff
-ffffffff
-ff000001
-ff800003
-ffffffc0
-ffe1ffff
-fffffffe
-fffffeff
-fffff7ff
-ffffffff
-ffffffff
-ffffffff
-ffffdfff
-ffffffff
-fffff7ff
-fffffdff
-fffffeff
-ffffffff
-ffffffbf
-ffffffdf
-fffffffd
-fffffffd
-00000040
-00000400
-08000000
-ffff7fff
-ffffffbf
-01555555
-00000000
-fffffffe
-000ccccc
-00000000
-0002aaaa
-00015555
-00000800
-fffffdff
-00000000
-00000000
-00000000
-ffffffff
-ffffffff
-00000019
-00000000
-fffffffd
-00000000
-00000000
-00000000
-ffffff80
-00000001
-00040000
-00000000
-00000001
-002aaaaa
-003ffdff
-001fffef
-00000040
-0001ffff
-00000000
-00002aaa
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000007
-00000000
-00000000
-00000000
-00000000
-00004868
-00002434
-00000000
-000078ae
-00003c57
-00000000
-00000000
-00000000
-00000000
-00004868
-00002434
-000078ad
-00003c56
-00000000
-00000000
-00000000
-00004868
-00002434
-00000000
-000078ad
-00003c56
-00000000
-ffffffff
-ffffffff
-ffffffff
-ffffb798
-ffffdbcc
-ffffffff
-ffff8753
-ffffc3a9
-ffffffff
-ffffffff
-00000000
-ffffffff
-ffffb798
-ffffdbcc
-ffff8753
-ffffc3a9
-ffffffff
-ffffffff
-ffffffff
-ffffb798
-ffffdbcc
-ffffffff
-ffff8753
-ffffc3a9
-ffffffff
-00006666
-00000000
-00004868
-28f5c28f
-147ae148
-00000002
-44444444
-22222222
-00000001
-00006665
-00000000
-00004867
-28f5c28f
-147ae147
-44444443
-22222221
-00000000
-00006666
-00004868
-28f5c28f
-147ae147
-00000002
-44444444
-22222222
-00000001
-00003333
-00000000
-00002434
-147ae148
-0a3d70a4
-00000001
-22222222
-11111111
-00000000
-00003332
-00000000
-00002433
-147ae147
-0a3d70a3
-22222222
-11111111
-00000000
-00003333
-00002434
-147ae147
-0a3d70a3
-00000001
-22222222
-11111111
-00000000
-00000000
-00000000
-00000000
-00000002
-00000001
-00000000
-00000004
-00000002
-00000000
-00000000
-00000000
-00000000
-00000002
-00000001
-00000003
-00000001
-00000000
-00000000
-00000000
-00000002
-00000001
-00000000
-00000003
-00000001
-00000000
-ffffaaaa
-ffffffff
-ffffc3a9
-dddddddd
-eeeeeeee
-fffffffe
-c71c71c7
-e38e38e3
-fffffffe
-ffffaaab
-00000000
-ffffc3a9
-ddddddde
-eeeeeeef
-c71c71c7
-e38e38e4
-ffffffff
-ffffaaab
-ffffc3a9
-ddddddde
-eeeeeeef
-fffffffe
-c71c71c7
-e38e38e3
-ffffffff
-00005555
-00000000
-00003c57
-22222222
-11111111
-00000002
-38e38e39
-1c71c71c
-00000001
-00005554
-00000000
-00003c56
-22222221
-11111110
-38e38e38
-1c71c71c
-00000000
-00005555
-00003c56
-22222222
-11111111
-00000001
-38e38e39
-1c71c71c
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000000
-00004867
-00002433
-00000000
-000078ac
-00003c56
-00000000
-00000000
-00000000
-00000000
-00004867
-00002433
-000078ac
-00003c56
-00000000
-00000000
-00000000
-00004867
-00002433
-00000000
-000078ac
-00003c56
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00006666
-00000000
-00004868
-28f5c28f
-147ae147
-00000002
-44444443
-22222221
-00000001
-00006665
-00000000
-00004867
-28f5c28e
-147ae146
-44444442
-22222221
-00000000
-00006665
-00004867
-28f5c28e
-147ae147
-00000001
-44444443
-22222221
-00000001
-00003333
-00000000
-00002434
-147ae147
-0a3d70a3
-00000001
-22222221
-11111110
-00003332
-00000000
-00002433
-147ae146
-0a3d70a3
-22222221
-11111110
-00000000
-00003332
-00002433
-147ae147
-0a3d70a3
-ffffffff
-ffffffff
-00000000
-ffffffff
-ffffb798
-ffffdbcc
-ffff8752
-ffffc3a9
-ffffffff
-ffffffff
-ffffffff
-ffffb798
-ffffdbcc
-ffffffff
-ffff8752
-ffffc3a9
-ffffffff
-00006666
-00000000
-00004868
-28f5c28f
-147ae147
-00000002
-44444444
-22222222
-00000001
-00006665
-00000000
-00004867
-28f5c28e
-147ae147
-44444443
-22222221
-00000000
-00006665
-00004867
-28f5c28f
-147ae147
-00000001
-44444443
-22222221
-00000001
-00003333
-00000000
-00002434
-147ae147
-0a3d70a3
-00000001
-22222222
-11111111
-00000000
-00003332
-00000000
-00002433
-147ae147
-0a3d70a3
-22222221
-11111110
-00000000
-00003332
-00002433
-147ae147
-0a3d70a3
-00000000
-22222221
-11111110
-00000000
-00000000
-00000000
-00000000
-00000002
-00000001
-00000000
-00000003
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000003
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000003
-00000001
-00000000
-ffffaaaa
-ffffffff
-ffffc3a8
-dddddddd
-eeeeeeee
-fffffffd
-c71c71c6
-e38e38e3
-fffffffe
-ffffaaab
-00000000
-ffffc3a9
-ddddddde
-eeeeeeef
-c71c71c7
-e38e38e3
-ffffffff
-ffffaaaa
-ffffc3a9
-dddddddd
-eeeeeeee
-fffffffe
-c71c71c6
-e38e38e3
-fffffffe
-00005555
-00000000
-00003c56
-22222222
-11111111
-00000001
-38e38e38
-1c71c71c
-00000001
-00005554
-00000000
-00000000
-00003c56
-22222221
-11111110
-38e38e38
-1c71c71b
-00000000
-00005554
-00003c56
-22222221
-11111110
-00000001
-38e38e38
-1c71c71c
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-22222221
-11111110
-00000000
-00005555
-00000000
-00003c56
-fffffffe
-22222221
-11111111
-00000001
-38e38e38
-1c71c71c
-00000001
-00005554
-00000000
-00003c56
-22222221
-11111110
-38e38e37
-1c71c71b
-00000000
-00005554
-00003c56
-22222221
-11111110
-00000001
-38e38e37
-1c71c71b
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00004868
-00002434
-00000000
-000078ad
-00003c56
-00000000
-00000000
-00000000
-00000000
-00004867
-00002433
-000078ad
-00003c56
-00000000
-00000000
-00000000
-00004867
-00002433
-00000000
-000078ad
-00003c56
-ffffffff
-ffffffff
-ffffffff
-ffffb797
-ffffdbcb
-ffffffff
-ffff8752
-ffffc3a9
-000bffff
-59999997
-00000004
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output
deleted file mode 100644
index 4143c8c36..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output
+++ /dev/null
@@ -1,724 +0,0 @@
-00000000
-00003fff
-fff0003e
-00000000
-077fffff
-0000001e
-fbffffbf
-00000000
-0000fefe
-ff7fffde
-33266665
-0000003f
-fbf03ffe
-0000b4fd
-00007ffd
-3332cccc
-00000010
-0000fffd
-003fffef
-00000012
-ff7ff006
-00000004
-ffffdbfe
-ffff7dfe
-0000007f
-fffff77e
-fffffdbe
-fffffede
-00000012
-0003ffff
-0000b504
-ffffffdc
-0000001f
-7ffdfffe
-b3fffffe
-dffff1fe
-77fffffe
-00000000
-0000fdfe
-feff00fe
-ffbffffa
-ffdf800e
-00ffefff
-00000007
-000fffdf
-1fffdfff
-00000000
-ffffedfe
-666664cc
-ff7fff7e
-7ffffff6
-ffffffb6
-0000003f
-000000ff
-effffffd
-00100000
-15555555
-00000080
-07efffff
-03bfffff
-01ffffff
-0000005a
-003fffff
-000aaaaa
-00000200
-00000200
-00000200
-00002000
-00004000
-00003f7f
-00000666
-00000555
-000007fd
-00000000
-000000aa
-0000007f
-00000000
-00000000
-00000000
-00000001
-00000000
-00000003
-00080000
-00000000
-01feffff
-00000000
-00000000
-00003ff7
-00000000
-00000000
-00000000
-000001ff
-00000000
-0000000f
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00006666
-00003333
-00000000
-0000aaaa
-00005555
-00000000
-00000000
-00000000
-00000000
-00006666
-00003333
-0000aaaa
-00005555
-00000000
-00000000
-00000000
-00006666
-00003333
-00000000
-0000aaaa
-00005555
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00004868
-00002434
-00000000
-000078ae
-00003c57
-00000000
-00000000
-00000000
-00000000
-00004868
-00002434
-000078ad
-00003c56
-00000000
-00000000
-00000000
-00004868
-00002434
-00000000
-000078ad
-00003c56
-00000000
-00006666
-00000000
-00004868
-28f5c28f
-147ae148
-00000002
-44444444
-22222222
-00000001
-00006665
-00000000
-00004867
-28f5c28f
-147ae147
-44444443
-22222221
-00000000
-00006666
-00004868
-28f5c28f
-147ae147
-00000002
-44444444
-22222222
-00000001
-00003333
-00002434
-147ae148
-0a3d70a4
-00000001
-22222222
-11111111
-00000000
-00003332
-00000000
-00002433
-147ae147
-0a3d70a3
-22222222
-11111111
-00000000
-00003333
-00002434
-147ae147
-0a3d70a3
-00000001
-22222222
-11111111
-00000000
-00000000
-00000000
-00000000
-00000002
-00000001
-00000000
-00000004
-00000002
-00000000
-00000000
-00000000
-00000000
-00000002
-00000001
-00000003
-00000001
-00000000
-00000000
-00000000
-00000002
-00000001
-00000000
-00000003
-00000001
-00000000
-0000aaaa
-00000000
-000078ae
-44444444
-22222222
-00000004
-71c71c72
-38e38e39
-00000002
-0000aaa9
-00000000
-000078ac
-44444443
-22222221
-71c71c70
-38e38e38
-00000001
-0000aaaa
-000078ad
-44444444
-22222222
-00000003
-71c71c71
-38e38e38
-00000002
-00005555
-00000000
-00003c57
-22222222
-11111111
-00000002
-38e38e39
-1c71c71c
-00000001
-00005554
-00000000
-00003c56
-22222221
-11111110
-38e38e38
-1c71c71c
-00000000
-00005555
-00003c56
-22222222
-11111111
-00000001
-38e38e39
-1c71c71c
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000000
-00006665
-00003332
-00000000
-0000aaa9
-00005554
-00000000
-00000000
-00000000
-00000000
-00006665
-00003332
-0000aaa9
-00005554
-00000000
-00000000
-00000000
-00006665
-00003332
-00000000
-0000aaa9
-00005554
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00004867
-00002433
-00000000
-000078ac
-00003c56
-00000000
-00000000
-00000000
-00000000
-00004867
-00002433
-000078ac
-00003c56
-00000000
-00000000
-00000000
-00004867
-00002433
-00000000
-000078ac
-00003c56
-00000000
-00006666
-00000000
-00004868
-28f5c28f
-147ae147
-00000002
-44444443
-22222221
-00000001
-00006665
-00000000
-00004867
-28f5c28e
-147ae146
-44444442
-22222221
-00000000
-00006665
-00004867
-28f5c28e
-147ae147
-00000001
-44444443
-22222221
-00000001
-00003333
-00000000
-00002434
-147ae147
-0a3d70a3
-00000001
-22222221
-11111110
-00000000
-00003332
-00000000
-00002433
-147ae146
-0a3d70a3
-22222221
-11111110
-00000000
-00003332
-00002433
-147ae147
-0a3d70a3
-00000000
-22222221
-11111110
-00000000
-0000aaaa
-00000000
-000078ad
-44444443
-22222222
-00000003
-71c71c70
-38e38e38
-00000002
-0000aaa9
-00000000
-000078ac
-44444442
-22222221
-71c71c6f
-38e38e37
-00000001
-0000aaa9
-000078ad
-44444443
-22222221
-00000001
-00005554
-00000000
-00003c56
-22222221
-11111110
-38e38e37
-1c71c71b
-00000000
-00005554
-00003c56
-22222221
-11111110
-00000001
-38e38e37
-1c71c71b
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00006666
-00003333
-00000000
-0000aaaa
-00005555
-00000000
-00000000
-00000000
-00000000
-00006665
-00003332
-0000aaa9
-00005554
-00000000
-00000000
-00000000
-00006665
-00003332
-00000000
-0000aaa9
-00005554
-00000000
-00000000
-00000000
-00000000
-00004868
-00002434
-00000000
-000078ad
-00003c56
-00000000
-00000000
-00000000
-00000000
-00004867
-00002433
-000078ad
-00003c56
-00000000
-00000000
-00000000
-00004867
-00002433
-00000000
-000078ad
-00003c56
-00000000
-00006666
-00000000
-00004868
-28f5c28f
-147ae147
-00000002
-44444444
-22222222
-00000001
-00006665
-00000000
-00004867
-28f5c28e
-147ae147
-44444443
-22222221
-00000000
-00006665
-00004867
-28f5c28f
-147ae147
-00000001
-44444443
-22222221
-00000001
-00003333
-00000000
-00002434
-147ae147
-0a3d70a3
-00000001
-22222222
-11111111
-00000000
-00003332
-00000000
-00002433
-00005555
-147ae147
-0a3d70a3
-22222221
-22222221
-11111110
-00000000
-00003332
-00002433
-147ae147
-0a3d70a3
-00000000
-22222221
-11111110
-00000000
-00000000
-00000000
-00000000
-00000002
-00000001
-00000000
-00000003
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000003
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000003
-00000001
-00000000
-0000aaaa
-00000000
-000078ad
-44444444
-22222222
-00000003
-71c71c71
-38e38e39
-00000002
-0000aaa9
-00000000
-000078ac
-44444443
-22222221
-71c71c70
-38e38e37
-00000001
-0000aaa9
-000078ad
-44444443
-22222221
-00000003
-71c71c70
-38e38e38
-00000001
-00005555
-00000000
-00003c56
-22222222
-11111111
-00000001
-38e38e38
-1c71c71c
-00000001
-00005554
-00000000
-00003c56
-22222221
-11111110
-38e38e38
-1c71c71b
-00000000
-00005554
-00003c56
-22222221
-11111110
-00000001
-38e38e38
-1c71c71c
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000002
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000003
-71c71c70
-00001fff
-38e38e38
-00000001
-00000000
-00003c56
-11111111
-00000001
-38e38e38
-1c71c71c
-bff9fffe
-0006ffff
-54aaaaa9
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output
deleted file mode 100644
index 37ac3dfc4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output
+++ /dev/null
@@ -1,586 +0,0 @@
-0000b503
-00000800
-00000000
-00000000
-fffffeff
-ff7fffff
-03333326
-04000000
-00000400
-ffffffef
-00000002
-fff003ff
-00000000
-00032668
-00000004
-00000000
-ffffbffe
-00000005
-00000000
-fffffb07
-00000000
-000003fe
-00000060
-fffffffd
-fffffffb
-00000020
-ffffffee
-00000008
-00000008
-fffffffc
-ffffffff
-00000000
-ffff3ffe
-ffffffff
-ffffffdf
-fdffffff
-feffffff
-ffbfffff
-ffdfffff
-ffefffff
-ffff8913
-ffff7fff
-fffffffb
-ffffffff
-ffffffff
-fffff7ff
-fffffbff
-fffffdff
-ffffffbf
-ffffffdf
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-00000100
-eaaaaaaa
-ffffffdf
-ffff4afc
-00000010
-0000b505
-ffff4afc
-00266667
-ffeaaaaa
-00000020
-00000007
-00000002
-00006667
-00000004
-00000000
-00000000
-00000000
-00000000
-ffffffff
-ffffffff
-fffffff9
-00000008
-00000000
-00000005
-00000000
-00000000
-00000000
-00000000
-000000c1
-20000000
-00000000
-00000000
-01000000
-00800000
-00000000
-00200000
-00080000
-00000000
-00000001
-00000010
-00000200
-00000000
-00000001
-00000001
-00000000
-00000002
-0000b505
-0000b505
-00000003
-0000b505
-0000b505
-00000001
-00000002
-0000b505
-0000b505
-0000b505
-0000b505
-00000001
-00000001
-00000001
-0000b505
-0000b505
-00000001
-0000b505
-0000b505
-00000000
-ffff4afd
-00000000
-ffff4afd
-ffff4afd
-ffffffff
-ffff4afd
-ffff4afd
-fffffffd
-00000000
-ffff4afd
-ffff4afd
-ffff4afd
-ffff4afd
-ffffffff
-ffff4afd
-ffff4afd
-ffff4afd
-ffff4afd
-fffffffc
-ffff4afd
-ffff4afd
-ffffffff
-00008257
-000039f1
-00000000
-33333333
-00000001
-11111112
-11111111
-00000003
-000039f1
-66666667
-00000002
-00000003
-11111113
-00000001
-00005e23
-00005e23
-00000001
-00000001
-00000004
-11111111
-11111112
-00000001
-0000412c
-00001cf9
-33333334
-00000000
-00000004
-33333334
-33333334
-00000000
-00001cf9
-33333334
-33333334
-00000002
-33333334
-00000000
-00008994
-00008994
-33333334
-00000001
-00000000
-33333334
-33333334
-00000001
-00000006
-00000006
-00000006
-00000006
-00000000
-00000006
-00000006
-00000002
-00000006
-00000006
-00000006
-00000006
-00000006
-00000000
-00000006
-00000006
-00000006
-00000006
-00000001
-00000006
-00000006
-00000000
-ffff570c
-ffffcfb8
-aaaaaaab
-dddddddf
-ffffffff
-00000000
-aaaaaaab
-ffffffff
-ffffcfb8
-aaaaaaab
-aaaaaaab
-dddddddd
-ffffffff
-ffffffff
-ffff9363
-ffff9363
-aaaaaaab
-ddddddde
-00000000
-aaaaaaab
-00000000
-ffffffff
-0000a8f5
-00003049
-55555556
-22222222
-00000002
-00000001
-00000000
-00000002
-00003049
-55555556
-55555556
-22222224
-00000002
-00000000
-00006c9e
-00006c9e
-55555556
-22222223
-00000001
-00000000
-00000001
-00000002
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000001
-0000b503
-00000000
-0000b503
-0000b503
-00000001
-0000b503
-0000b503
-00000003
-00000000
-0000b503
-0000b503
-0000b503
-0000b503
-00000001
-0000b503
-0000b503
-0000b503
-0000b503
-00000004
-0000b503
-0000b503
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00008255
-000039ef
-66666665
-33333331
-00000005
-11111110
-1111110f
-00000001
-000039ef
-33333333
-33333333
-00000001
-33333333
-00000001
-00008993
-00008993
-33333333
-00000000
-00000004
-33333333
-33333333
-00000000
-00000005
-00000005
-00000005
-00000005
-00000005
-00000005
-00000005
-00000001
-00000005
-00000005
-00000005
-00000005
-00000005
-00000001
-00000005
-00000005
-00000005
-00000005
-00000000
-00000005
-00000005
-00000002
-ffff570b
-ffffcfb7
-aaaaaaaa
-ddddddde
-fffffffe
-ffffffff
-00000000
-fffffffe
-ffffcfb7
-aaaaaaaa
-aaaaaaaa
-dddddddc
-fffffffe
-00000000
-ffff9362
-ffff9362
-aaaaaaaa
-dddddddd
-ffffffff
-00000000
-ffffffff
-fffffffe
-0000a8f4
-00003048
-55555555
-22222221
-00000001
-00000000
-55555555
-00000001
-00003048
-55555555
-55555555
-22222223
-00000001
-00000001
-00006c9d
-00006c9d
-55555555
-22222222
-00000000
-55555555
-00000000
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000000
-66666665
-00000000
-00000001
-11111111
-00000001
-00005e21
-00005e21
-66666665
-33333332
-00000002
-1111110f
-11111110
-00000002
-0000412a
-00001cf7
-33333332
-33333332
-00000002
-33333332
-33333332
-00000002
-00001cf7
-33333332
-33333332
-00000000
-33333332
-00000000
-00008992
-00008992
-33333332
-33333332
-00000003
-33333332
-33333332
-00000002
-0000a8f3
-00003047
-55555554
-22222220
-00000000
-55555554
-55555554
-00000000
-00003047
-55555554
-55555554
-22222222
-00000000
-00000000
-00006c9c
-00006c9c
-55555554
-22222221
-00000004
-55555554
-55555554
-00000000
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000000
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-0000b504
-00000001
-0000b504
-0000b504
-00000002
-0000b504
-0000b504
-00000000
-00000001
-0000b504
-0000b504
-0000b504
-0000b504
-00000000
-00000000
-00000000
-0000b504
-0000b504
-00000000
-0000b504
-0000b504
-00000002
-ffff4afc
-ffffffff
-ffff4afc
-ffff4afc
-fffffffe
-ffff4afc
-ffff4afc
-00000000
-ffffffff
-ffff4afc
-ffff4afc
-ffff4afc
-ffff4afc
-00000000
-00000000
-00000000
-ffff4afc
-ffff4afc
-00000000
-ffff4afc
-ffff4afc
-fffffffe
-00008256
-000039f0
-66666666
-33333332
-00000000
-11111111
-11111110
-00000002
-000039f0
-66666666
-00000001
-00000002
-11111112
-00000000
-00005e22
-00005e22
-00000000
-00000000
-00000003
-11111110
-11111111
-00000000
-0000412b
-00001cf8
-33333333
-33333333
-00000003
-33333333
-33333333
-00000003
-00001cf8
-fbffffff
-fffdffff
-01ffffff
-fffffff9
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output
deleted file mode 100644
index e8914d920..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output
+++ /dev/null
@@ -1,725 +0,0 @@
-00000020
-33333332
-00000000
-00000000
-0ffc0000
-00020000
-00000000
-00000000
-00000003
-007fffe0
-00000010
-fffffffb
-ff7fffff
-0000b503
-fbffffff
-ffdfffff
-00000000
-00004000
-0000000c
-00000000
-00000ff8
-20000000
-00010000
-000000c0
-00000400
-00000001
-33333332
-ffffffbf
-00000000
-ffff7fff
-00000001
-00000400
-001fffff
-000001ff
-0000a9bb
-f7ffffff
-fdffffff
-32333335
-00000005
-0000000d
-fff7ffff
-fffdffff
-001fe000
-00000009
-01fff800
-00000003
-fffffdff
-0000000f
-00000f7f
-ffffffef
-00001ffe
-55555554
-00000020
-1fff7fff
-0000000b
-00000002
-00400000
-01333332
-00000005
-00000010
-003ff7ff
-00000000
-00000080
-00000100
-0001ffff
-0000ff7f
-00007ff7
-00000000
-00001fdf
-00000004
-000003ff
-00000067
-00000000
-00000008
-00000004
-00000003
-00000000
-00000000
-80000000
-40000000
-10000000
-00002160
-00000000
-01000000
-00000000
-00200000
-00080000
-00040000
-00004000
-00002000
-00001000
-00000800
-00000002
-00000040
-00000000
-00000000
-00004afb
-00010000
-00010000
-00000004
-00010000
-00010000
-00000000
-00000002
-00010000
-00004afd
-00010000
-00010000
-00010000
-00010000
-00000000
-00000001
-00004afc
-00010000
-00010000
-00000001
-00010000
-00010000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-0000b505
-00000000
-00000000
-0000b505
-0000b505
-00000003
-0000b505
-0000b505
-00000001
-0000b505
-0000b505
-00000002
-0000b505
-0000b505
-0000b505
-0000b505
-00000001
-0000b505
-00000001
-0000b505
-0000b505
-00000001
-0000b505
-0000b505
-00000000
-00006667
-00000000
-00008257
-00000000
-33333333
-00000001
-66666667
-11111111
-00000003
-00003335
-66666667
-000039f1
-00000002
-00000003
-66666667
-11111113
-00000001
-0000cccd
-00005e23
-00000001
-00000001
-00000004
-66666667
-11111112
-00000001
-00003334
-00000000
-0000412c
-33333334
-00000000
-00000004
-33333334
-33333334
-00000000
-0000999a
-33333334
-00001cf9
-33333334
-00000002
-33333334
-33333334
-00000000
-00006667
-00008994
-33333334
-00000001
-00000000
-33333334
-33333334
-00000001
-00000006
-00000000
-00000006
-00000006
-00000006
-00000000
-00000006
-00000006
-00000002
-00000006
-00000006
-00000006
-00000006
-00000006
-00000006
-00000006
-00000000
-00000006
-00000006
-00000006
-00000006
-00000001
-00000006
-00000006
-00000000
-0000aaab
-00000000
-00009ce4
-44444444
-1111110f
-00000003
-00000000
-55555555
-00000003
-00000003
-aaaaaaab
-00006091
-44444446
-11111115
-00000002
-00000003
-00000001
-00005556
-00002437
-44444445
-11111112
-00000001
-00000001
-00000001
-00000000
-00005556
-00000000
-0000a8f5
-55555556
-22222222
-00000002
-55555556
-00000000
-00000002
-00000002
-55555556
-00003049
-55555556
-22222224
-55555556
-00000002
-00000000
-0000aaab
-00006c9e
-55555556
-22222223
-00000001
-55555556
-00000001
-00000002
-00000004
-00000000
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000004
-00000001
-0000fffe
-00000000
-00004af9
-0000fffe
-0000fffe
-00000002
-0000fffe
-0000fffe
-00000002
-00000000
-0000fffe
-00004afb
-0000fffe
-0000fffe
-0000fffe
-0000fffe
-00000000
-0000fffe
-00004afa
-0000fffe
-0000fffe
-00000004
-0000fffe
-0000fffe
-00000002
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-0000b503
-00000000
-0000b503
-0000b503
-0000b503
-00000001
-0000b503
-0000b503
-00000003
-0000b503
-0000b503
-00000000
-0000b503
-0000b503
-0000b503
-0000b503
-00000001
-0000b503
-0000b503
-0000b503
-0000b503
-00000004
-0000b503
-0000b503
-00000001
-00006665
-00000000
-00008255
-66666665
-33333331
-00000005
-66666665
-1111110f
-00000001
-00003333
-66666665
-000039ef
-00000000
-00000001
-66666665
-11111111
-00000001
-0000cccb
-00005e21
-66666665
-33333332
-00000002
-66666665
-11111110
-00000002
-00003332
-00000000
-0000412a
-33333332
-33333332
-00000002
-33333332
-33333332
-00000002
-00009998
-33333332
-00001cf7
-33333332
-00000000
-33333332
-33333332
-00000000
-00006665
-00008992
-33333332
-33333332
-00000003
-33333332
-33333332
-00000002
-0000aaa9
-00000000
-00009ce2
-44444442
-1111110d
-00000001
-aaaaaaa9
-55555553
-00000001
-00000001
-aaaaaaa9
-0000608f
-44444444
-11111113
-00000000
-00000001
-00000001
-00005554
-00002435
-44444443
-11111110
-00000004
-00000000
-00000000
-55555554
-00003047
-55555554
-22222222
-55555554
-00000000
-00000000
-0000aaa9
-00006c9c
-55555554
-22222221
-00000004
-55555554
-55555554
-00000000
-00000002
-00000000
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000000
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-0000ffff
-00000000
-00004afa
-0000ffff
-0000ffff
-00000003
-0000ffff
-0000ffff
-00000003
-00000001
-0000ffff
-00004afc
-0000ffff
-0000ffff
-0000ffff
-0000ffff
-00000001
-00000000
-00004afb
-0000ffff
-0000ffff
-00000000
-0000ffff
-0000ffff
-00000000
-0000b504
-00000000
-0000b504
-0000b504
-0000b504
-00000002
-0000b504
-0000b504
-00000000
-0000b504
-0000b504
-00000001
-0000b504
-0000b504
-0000b504
-0000b504
-00000000
-0000b504
-00000000
-0000b504
-0000b504
-00000000
-0000b504
-0000b504
-00000002
-00006666
-00000000
-00008256
-66666666
-33333332
-00000000
-66666666
-11111110
-00000002
-00003334
-66666666
-000039f0
-00000001
-00000002
-66666666
-11111112
-00000000
-0000cccc
-00005e22
-00000000
-00000000
-00000003
-66666666
-11111111
-00000000
-00003333
-00000000
-0000412b
-33333333
-33333333
-00000003
-33333333
-33333333
-00000003
-00009999
-33333333
-00000001
-00001cf8
-33333333
-00000001
-33333333
-33333333
-00000001
-00006666
-00008993
-33333333
-00000000
-00000004
-33333333
-33333333
-00000000
-00000005
-00000000
-00000005
-00000005
-00000005
-00000005
-00000005
-00000005
-00000001
-00000005
-00000005
-00000005
-00000005
-00000005
-00000005
-00000005
-00000001
-00000005
-00000005
-00000005
-00000005
-00000000
-00000005
-00000005
-00000002
-0000aaaa
-00000000
-00009ce3
-44444443
-1111110e
-00000002
-aaaaaaaa
-55555554
-00000002
-00000002
-aaaaaaaa
-00006090
-44444445
-11111114
-00000001
-00000002
-00000000
-00005555
-00002436
-44444444
-11111111
-00000000
-00000000
-00000000
-00000002
-00005555
-00000000
-0000a8f4
-55555555
-22222221
-00000001
-55555555
-55555555
-00000001
-00000001
-55555555
-00003048
-55555555
-22222223
-55555555
-00000001
-00000001
-0000aaaa
-00006c9d
-55555555
-22222222
-00000000
-55555555
-00000000
-00000001
-00000003
-00000000
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000000
-aaaaaaa9
-00000010
-55555554
-00005554
-00000000
-0000a8f3
-55555554
-22222220
-00000000
-55555554
-55555554
-00008000
-0000000c
-55555555
-dfffffff
-001ffffc
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output
deleted file mode 100644
index ab5658348..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output
+++ /dev/null
@@ -1,3 +0,0 @@
-00000000
-40000000
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output
deleted file mode 100644
index b364d3f1a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output
+++ /dev/null
@@ -1,584 +0,0 @@
-ffffb7fe
-7ffbfffe
-bfbffffe
-00000040
-00000000
-f6fffffe
-fc000006
-31333332
-ff0007ff
-ff7fffee
-ffbffffa
-fddffffe
-ffedfffe
-ffd7fffe
-fffc007f
-fdfdfffe
-aaa9aaa9
-3332b331
-ffffe002
-fffff008
-fff7f7fe
-fffffbff
-fffff5fe
-55555454
-ffffff7c
-ffdfffbe
-ffffff5e
-fffffff8
-ffffbff6
-07fffffb
-ffdffffc
-ffffbffd
-8001ffff
-26666664
-dfff7ffe
-f000001f
-f7ffff7e
-fc0fffff
-ff7ffffb
-ffefffff
-fffeeffe
-00077fff
-ffffdfff
-0003efff
-fffffcff
-ffffddfe
-ffffeefe
-ffffffae
-ffffffe6
-fdfffff6
-fffffff8
-80000006
-60000000
-e0000000
-baaaaaaa
-08000001
-59555554
-02000040
-01000003
-007ffffa
-00400010
-000fffff
-00010000
-ffff7fff
-ffff8afd
-55557555
-00011000
-00000800
-00080400
-000001fd
-fffffe7f
-00000042
-ffe0000f
-fffffff7
-fffffffb
-ffffffc1
-40000000
-80000006
-40000005
-0fff4afc
-04000006
-01fffff7
-00fffff9
-007ffffe
-003ffdff
-001ffff8
-c00fffff
-0003ff7f
-c001ffff
-01008000
-c0004000
-00042000
-aaaabaaa
-f80003ff
-00000201
-ffff00ff
-fff80007
-00016a0a
-00000002
-66671b6c
-3333e839
-0000b50b
-aaab5fb0
-55560a5b
-0000b509
-00016a08
-0000b505
-66671b6a
-3333e837
-55560a59
-0000b507
-00016a09
-00000001
-66671b6b
-3333e838
-0000b50a
-aaab5faf
-55560a5a
-0000b508
-00000002
-fffe95fa
-6665b164
-33327e31
-ffff4b03
-aaa9f5a8
-5554a053
-ffff4b01
-00000000
-ffff4afd
-6665b162
-33327e2f
-5554a051
-ffff4aff
-00000001
-fffe95f9
-6665b163
-33327e30
-ffff4b02
-aaa9f5a7
-5554a052
-ffff4b00
-66671b6c
-6665b164
-ccccccce
-9999999b
-6666666d
-11111112
-bbbbbbbd
-6666666b
-66671b6a
-66666667
-cccccccc
-99999999
-bbbbbbbb
-66666669
-66671b6b
-6665b163
-cccccccd
-9999999a
-6666666c
-11111111
-bbbbbbbc
-6666666a
-3333e839
-33327e31
-9999999b
-66666668
-3333333a
-dddddddf
-8888888a
-33333338
-3333e837
-33333334
-99999999
-66666666
-88888888
-33333336
-3333e838
-33327e30
-9999999a
-66666667
-33333339
-ddddddde
-88888889
-33333337
-0000b50b
-ffff4b03
-6666666d
-3333333a
-0000000c
-aaaaaab1
-5555555c
-0000000a
-0000b509
-00000006
-6666666b
-33333338
-5555555a
-00000008
-0000b50a
-ffff4b02
-6666666c
-33333339
-0000000b
-aaaaaab0
-5555555b
-00000009
-aaab5fb0
-aaa9f5a8
-11111112
-dddddddf
-aaaaaab1
-55555556
-00000001
-aaaaaaaf
-aaab5fae
-aaaaaaab
-11111110
-dddddddd
-ffffffff
-aaaaaaad
-aaab5faf
-aaa9f5a7
-11111111
-ddddddde
-aaaaaab0
-55555555
-00000000
-aaaaaaae
-55560a5b
-5554a053
-bbbbbbbd
-8888888a
-5555555c
-00000001
-aaaaaaac
-5555555a
-55560a59
-55555556
-bbbbbbbb
-88888888
-aaaaaaaa
-55555558
-55560a5a
-5554a052
-bbbbbbbc
-88888889
-5555555b
-00000000
-aaaaaaab
-55555559
-0000b509
-ffff4b01
-6666666b
-33333338
-0000000a
-aaaaaaaf
-5555555a
-00000008
-0000b507
-00000004
-66666669
-33333336
-55555558
-00000006
-0000b508
-ffff4b00
-6666666a
-33333337
-00000009
-aaaaaaae
-55555559
-00000007
-00016a08
-00000000
-66671b6a
-3333e837
-0000b509
-aaab5fae
-55560a59
-0000b507
-00016a06
-0000b503
-66671b68
-3333e835
-55560a57
-0000b505
-00016a07
-ffffffff
-66671b69
-3333e836
-0000b508
-aaab5fad
-55560a58
-0000b506
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000003
-66671b6a
-6665b162
-cccccccc
-99999999
-6666666b
-11111110
-bbbbbbbb
-66666669
-66671b68
-33333333
-99999998
-66666665
-88888887
-33333335
-3333e837
-33327e2f
-99999999
-66666666
-33333338
-dddddddd
-88888888
-33333336
-0000b50a
-ffff4b02
-6666666c
-33333339
-0000000b
-aaaaaab0
-5555555b
-00000009
-0000b508
-00000005
-6666666a
-33333337
-55555559
-00000007
-0000b509
-ffff4b01
-6666666b
-33333338
-0000000a
-aaaaaaaf
-5555555a
-00000008
-aaab5faf
-aaa9f5a7
-11111111
-ddddddde
-aaaaaab0
-55555555
-00000000
-aaaaaaae
-aaab5fad
-aaaaaaaa
-1111110f
-dddddddc
-fffffffe
-aaaaaaac
-aaab5fae
-aaa9f5a6
-11111110
-dddddddd
-aaaaaaaf
-55555554
-ffffffff
-aaaaaaad
-55560a5a
-5554a052
-bbbbbbbc
-88888889
-5555555b
-00000000
-aaaaaaab
-55555559
-55560a58
-55555555
-bbbbbbba
-88888887
-aaaaaaa9
-55555557
-55560a59
-5554a051
-bbbbbbbb
-88888888
-5555555a
-ffffffff
-aaaaaaaa
-55555558
-0000b508
-ffff4b00
-6666666a
-33333337
-00000009
-aaaaaaae
-55555559
-00000007
-0000b506
-00000003
-66666668
-33333335
-55555557
-00000005
-0000b507
-ffff4aff
-66666669
-33333336
-00000008
-aaaaaaad
-55555558
-00000006
-66666665
-ccccccca
-99999997
-bbbbbbb9
-66666667
-66671b69
-6665b161
-cccccccb
-99999998
-6666666a
-1111110f
-bbbbbbba
-66666668
-3333e837
-33327e2f
-99999999
-66666666
-33333338
-dddddddd
-88888888
-33333336
-3333e835
-33333332
-99999997
-66666664
-88888886
-33333334
-3333e836
-33327e2e
-99999998
-66666665
-33333337
-dddddddc
-88888887
-33333335
-55560a59
-5554a051
-bbbbbbbb
-88888888
-5555555a
-ffffffff
-aaaaaaaa
-55555558
-55560a57
-55555554
-bbbbbbb9
-88888886
-aaaaaaa8
-55555556
-55560a58
-5554a050
-bbbbbbba
-88888887
-55555559
-fffffffe
-aaaaaaa9
-55555557
-0000b507
-ffff4aff
-66666669
-33333336
-00000008
-aaaaaaad
-55555558
-00000006
-0000b505
-00000002
-66666667
-33333334
-55555556
-00000004
-0000b506
-ffff4afe
-66666668
-33333335
-00000007
-aaaaaaac
-55555557
-00000005
-00016a09
-00000001
-66671b6b
-3333e838
-0000b50a
-aaab5faf
-55560a5a
-0000b508
-00016a07
-0000b504
-66671b69
-3333e836
-55560a58
-0000b506
-00016a08
-00000000
-66671b6a
-3333e837
-0000b509
-aaab5fae
-55560a59
-0000b507
-00000001
-fffe95f9
-6665b163
-33327e30
-ffff4b02
-aaa9f5a7
-5554a052
-ffff4b00
-ffffffff
-ffff4afc
-6665b161
-33327e2e
-5554a050
-ffff4afe
-00000000
-fffe95f8
-6665b162
-33327e2f
-ffff4b01
-aaa9f5a6
-5554a051
-ffff4aff
-66671b6b
-6665b163
-cccccccd
-9999999a
-6666666c
-11111111
-bbbbbbbc
-6666666a
-66671b69
-66666666
-cccccccb
-99999998
-bbbbbbba
-66666668
-66671b6a
-6665b162
-cccccccc
-99999999
-6666666b
-11111110
-bbbbbbbb
-66666669
-3333e838
-33327e30
-9999999a
-66666667
-33333339
-ddddddde
-88888889
-33333337
-3333e836
-e000001f
-f0000003
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output
deleted file mode 100644
index 1052749cb..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output
+++ /dev/null
@@ -1,564 +0,0 @@
-1ffff800
-80000666
-00000000
-e0000555
-efffffee
-f7fffffb
-fbffffff
-00000000
-ff000003
-ff80003f
-ffbffffa
-ffe00554
-ffefffee
-fff7fff5
-fffbfdfe
-fffe0002
-ffff0004
-ffff8005
-ffffbff7
-ffffdff9
-ffffefde
-fffff9ff
-fffffbf9
-fffffdde
-ffffff01
-ffffffac
-ffffffeb
-ffffffe1
-fffffff5
-fffffff2
-00000027
-ffffffd1
-fffffff4
-0000bd02
-ffffffff
-ffffeefe
-07ffff7f
-ffffffc3
-ffffffb6
-00000003
-fffffff9
-80000556
-3ffffc00
-10000000
-03fffff6
-0200002e
-01000667
-007fffbf
-003ffeff
-00200555
-00100000
-00080005
-000403ff
-00020000
-00010200
-00007ff9
-00004333
-00002555
-00000aaa
-00000e65
-000001bf
-000004ff
-000006e6
-00000373
-0000081f
-00000210
-00000008
-ffffffff
-00000101
-000003bf
-00000080
-00000020
-00008010
-00000000
-55555556
-0000b533
-0000b4d9
-0000bb6c
-0000b839
-0000b50b
-0000afb0
-0000ba5b
-0000b509
-0000b531
-0000b505
-0000bb6a
-0000b837
-0000ba59
-0000b507
-0000b532
-0000b4d8
-0000bb6b
-0000b838
-0000b50a
-0000afaf
-0000ba5a
-0000b508
-ffff4b2b
-ffff4ad1
-ffff5164
-ffff4e31
-ffff4b03
-ffff45a8
-ffff5053
-ffff4b01
-ffff4b29
-ffff4afd
-ffff5162
-ffff4e2f
-ffff5051
-ffff4aff
-ffff4b2a
-ffff4ad0
-ffff5163
-ffff4e30
-ffff4b02
-ffff45a7
-ffff5052
-ffff4b00
-66666695
-6666663b
-66666cce
-6666699b
-6666666d
-66666112
-66666bbd
-6666666b
-66666693
-66666667
-66666ccc
-66666999
-66666bbb
-66666669
-66666694
-6666663a
-66666ccd
-6666699a
-6666666c
-66666111
-66666bbc
-6666666a
-33333362
-33333308
-3333399b
-33333668
-3333333a
-33332ddf
-3333388a
-33333338
-33333360
-33333334
-33333999
-33333666
-33333888
-33333336
-33333361
-33333307
-3333399a
-33333667
-33333339
-33332dde
-33333889
-33333337
-00000034
-ffffffda
-0000066d
-0000033a
-0000000c
-fffffab1
-0000055c
-0000000a
-00000032
-00000006
-0000066b
-00000338
-0000055a
-00000008
-00000033
-ffffffd9
-0000066c
-00000339
-0000000b
-fffffab0
-0000055b
-00000009
-aaaaaad9
-aaaaaa7f
-aaaab112
-aaaaaddf
-aaaaaab1
-aaaaa556
-aaaab001
-aaaaaaaf
-aaaaaad7
-aaaaaaab
-aaaab110
-aaaaaddd
-aaaaafff
-aaaaaaad
-aaaaaad8
-aaaaaa7e
-aaaab111
-aaaaadde
-aaaaaab0
-aaaaa555
-aaaab000
-aaaaaaae
-55555584
-5555552a
-55555bbd
-5555588a
-5555555c
-55555001
-55555aac
-5555555a
-55555582
-55555556
-55555bbb
-55555888
-55555aaa
-55555558
-55555583
-55555529
-55555bbc
-55555889
-5555555b
-55555000
-55555aab
-55555559
-00000032
-ffffffd8
-0000066b
-00000338
-0000000a
-fffffaaf
-0000055a
-00000008
-00000030
-00000004
-00000669
-00000336
-00000558
-00000006
-00000031
-ffffffd7
-0000066a
-00000337
-00000009
-fffffaae
-00000559
-00000007
-0000b531
-0000b4d7
-0000bb6a
-0000b837
-0000b509
-0000afae
-0000ba59
-0000b507
-0000b52f
-0000b503
-0000bb68
-0000b835
-0000ba57
-0000b505
-0000b530
-0000b4d6
-0000bb69
-0000b836
-0000b508
-0000afad
-0000ba58
-0000b506
-0000002e
-ffffffd4
-00000667
-00000334
-00000006
-fffffaab
-00000556
-00000004
-0000002c
-00000000
-00000665
-00000332
-00000554
-00000002
-0000002d
-ffffffd3
-00000666
-00000333
-00000005
-fffffaaa
-00000555
-00000003
-66666693
-66666639
-66666ccc
-66666999
-6666666b
-66666110
-66666bbb
-66666669
-66666691
-66666665
-aaaaa555
-aaaab000
-aaaaaaae
-aaaaaad6
-aaaaaaaa
-aaaab10f
-aaaaaddc
-aaaaaffe
-aaaaaaac
-aaaaaad7
-aaaaaa7d
-aaaab110
-aaaaaddd
-aaaaaaaf
-aaaaa554
-aaaaafff
-aaaaaaad
-55555583
-55555529
-55555bbc
-55555889
-5555555b
-55555000
-55555aab
-55555559
-55555581
-55555555
-55555bba
-55555887
-55555aa9
-55555557
-55555582
-55555528
-55555bbb
-55555888
-5555555a
-55554fff
-55555aaa
-55555558
-00000031
-ffffffd7
-0000066a
-00000337
-00000009
-fffffaae
-00000559
-00000007
-0000002f
-00000003
-00000668
-00000335
-00000557
-00000005
-00000030
-ffffffd6
-00000669
-00000336
-00000008
-fffffaad
-00000558
-00000006
-66666cca
-66666997
-66666bb9
-66666667
-66666692
-66666638
-66666ccb
-66666998
-6666666a
-6666610f
-66666bba
-66666668
-33333360
-33333306
-33333999
-33333666
-33333338
-33332ddd
-33333888
-33333336
-3333335e
-33333332
-33333997
-33333664
-33333886
-33333334
-3333335f
-33333305
-33333998
-33333665
-33333337
-33332ddc
-33333887
-33333335
-55555582
-55555528
-55555bbb
-55555888
-5555555a
-55554fff
-55555aaa
-55555558
-55555580
-55555554
-55555bb9
-55555886
-55555aa8
-55555556
-55555581
-55555527
-55555bba
-55555887
-55555559
-55554ffe
-55555aa9
-55555557
-00000030
-ffffffd6
-00000669
-00000336
-00000008
-fffffaad
-00000558
-00000006
-0000002e
-00000002
-00000667
-00000334
-00000556
-00000004
-0000002f
-ffffffd5
-00000668
-00000335
-00000007
-fffffaac
-00000557
-00000005
-0000b532
-0000b4d8
-0000bb6b
-0000b838
-0000b50a
-0000afaf
-0000ba5a
-0000b508
-0000b530
-0000b504
-0000bb69
-0000b836
-0000ba58
-0000b506
-0000b531
-0000b4d7
-0000bb6a
-0000b837
-0000b509
-0000afae
-0000ba59
-0000b507
-ffff4b2a
-ffff4ad0
-ffff5163
-ffff4e30
-ffff4b02
-ffff45a7
-ffff5052
-ffff4b00
-ffff4b28
-ffff4afc
-ffff5161
-ffff4e2e
-ffff5050
-ffff4afe
-ffff4b29
-ffff4acf
-ffff5162
-ffff4e2f
-ffff4b01
-ffff45a6
-ffff5051
-ffff4aff
-66666694
-6666663a
-66666ccd
-6666699a
-6666666c
-66666111
-66666bbc
-6666666a
-66666692
-66666666
-66666ccb
-66666998
-66666bba
-66666668
-66666693
-66666639
-66666ccc
-66666999
-6666666b
-66666110
-66666bbb
-66666669
-33333361
-33333307
-3333399a
-33333667
-33333339
-33332dde
-33333889
-33333337
-3333335f
-33333333
-33333998
-33333665
-33333887
-33333335
-33333360
-33333306
-33333999
-33333666
-33333338
-33332ddd
-33333888
-33333336
-00000033
-ffffffd9
-0000066c
-00000339
-0000000b
-fffffab0
-0000055b
-00000009
-00000031
-00000005
-0000066a
-00000337
-00000559
-00000007
-00000032
-ffffffd8
-0000066b
-00000338
-0000000a
-fffffaaf
-0000055a
-00000008
-aaaaaad8
-aaaaaa7e
-aaaab111
-aaaaadde
-aaaaaab0
-c000003f
-fdffffff
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output
deleted file mode 100644
index e8e6b49d4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output
+++ /dev/null
@@ -1,588 +0,0 @@
-00000000
-00000003
-00000100
-00040000
-00100000
-f3ffffff
-aaaaaaaa
-00400000
-00000000
-ff7fffbf
-01000000
-ffdfbfff
-ffeffbff
-00000000
-02000000
-00000000
-00000004
-55555555
-40000000
-00000004
-00000100
-aaaaa2aa
-00001000
-00000001
-00000007
-00000003
-0000b504
-00000080
-0000b505
-00100000
-00004000
-33333330
-55555554
-7f7fffff
-26666667
-00000003
-effffff8
-00200000
-fdfffeff
-fe7fffff
-ff7ffeff
-ff9fffff
-66466666
-ffef4afd
-0000b504
-fffb7fff
-55555556
-00080000
-ffff3fff
-00000002
-00000020
-ffff42fc
-fff7fdff
-f7fffeff
-55555555
-fffffddf
-00000003
-00000006
-00000001
-ffff4afc
-00000000
-00000000
-20000000
-10000000
-08000000
-04000000
-02000000
-01000000
-00000000
-00000000
-00100000
-00000000
-00020000
-00000000
-00000000
-00000000
-00002000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000080
-00000000
-00000010
-00000004
-00000000
-20000000
-00000000
-04000000
-00800000
-00200000
-00080000
-00020000
-00000000
-00002000
-00000400
-00000200
-00000040
-00000000
-00000000
-0000b505
-00000005
-00002405
-00003104
-00000004
-0000a001
-00001504
-00000004
-0000b501
-00000000
-00002405
-00003100
-00001504
-00000000
-0000b504
-00000004
-00002404
-00003101
-00000005
-0000a000
-00001505
-00000001
-00000005
-ffff4afd
-66664265
-33330234
-00000004
-aaaa0aa9
-55554054
-00000001
-00000000
-66664265
-33330230
-55554054
-00000000
-00000004
-ffff4afc
-66664264
-33330231
-00000005
-aaaa0aa8
-55554055
-00000001
-00002405
-66664265
-66666667
-22222224
-00000006
-22222223
-44444446
-00000004
-00002403
-00000000
-66666665
-22222222
-44444444
-00000002
-00002404
-66664264
-66666666
-22222223
-00000005
-22222222
-44444445
-00000003
-00003104
-33330234
-22222224
-33333334
-00000004
-22222220
-11111114
-00000004
-00003100
-00000000
-22222224
-33333330
-11111114
-00000000
-00003104
-33330234
-22222224
-33333330
-00000004
-22222220
-11111114
-00000000
-00000004
-00000004
-00000006
-00000004
-00000006
-00000002
-00000006
-00000004
-00000002
-00000000
-00000004
-00000002
-00000004
-00000002
-00000004
-00000004
-00000006
-00000002
-00000004
-00000002
-00000004
-00000002
-0000a001
-aaaa0aa9
-22222223
-22222220
-00000002
-aaaaaaab
-00000002
-00000000
-0000a003
-00000000
-22222221
-22222222
-00000000
-00000002
-0000a000
-aaaa0aa8
-22222222
-22222223
-00000001
-aaaaaaaa
-00000001
-00000003
-00001504
-55554054
-44444446
-11111114
-00000006
-00000002
-55555556
-00000004
-00001502
-00000000
-44444444
-11111112
-55555554
-00000002
-00001504
-55554054
-44444446
-11111112
-00000004
-00000002
-55555554
-00000002
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000004
-00000000
-00000000
-00000004
-00000000
-00000004
-00000000
-00000004
-00000004
-00000004
-00000000
-00000004
-00000000
-00000004
-00000000
-0000b501
-00000001
-00002403
-00003100
-00000002
-0000a003
-00001502
-00000000
-0000b503
-00000000
-00002401
-00003102
-00001500
-00000002
-0000b500
-00000000
-00002402
-00003103
-00000001
-0000a002
-00001501
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00002405
-66664265
-66666665
-22222224
-00000004
-22222221
-44444444
-00000004
-00002401
-00000000
-22222221
-33333332
-11111110
-00000002
-00003100
-33330230
-22222222
-33333333
-00000001
-22222222
-11111111
-00000003
-00000005
-00000005
-00000005
-00000004
-00000004
-00000001
-00000004
-00000004
-00000001
-00000000
-00000005
-00000000
-00000004
-00000000
-00000004
-00000004
-00000004
-00000001
-00000005
-00000000
-00000005
-00000001
-0000a000
-aaaa0aa8
-22222222
-22222220
-00000002
-aaaaaaaa
-00000002
-00000000
-0000a002
-00000000
-22222220
-22222222
-00000000
-00000002
-0000a000
-aaaa0aa8
-22222222
-22222222
-00000000
-aaaaaaaa
-00000000
-00000002
-00001505
-55554055
-44444445
-11111114
-00000004
-00000001
-55555554
-00000004
-00001501
-00000000
-44444445
-11111110
-55555554
-00000000
-00001504
-55554054
-44444444
-11111111
-00000005
-00000000
-55555555
-00000001
-00000001
-00000001
-00000003
-00000000
-00000002
-00000003
-00000002
-00000000
-00000003
-00000000
-00000001
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000003
-00000001
-00000002
-00000001
-00000003
-00000000
-66666665
-22222220
-44444444
-00000000
-00002404
-66664264
-66666664
-22222221
-00000005
-22222220
-44444445
-00000001
-00003100
-33330230
-22222222
-33333330
-00000002
-22222222
-11111112
-00000000
-00003102
-00000000
-22222220
-33333332
-11111110
-00000002
-00003100
-33330230
-22222222
-33333332
-00000000
-22222222
-11111110
-00000002
-00001504
-55554054
-44444444
-11111114
-00000004
-00000000
-55555554
-00000004
-00001500
-00000000
-44444444
-11111110
-55555554
-00000000
-00001504
-55554054
-44444444
-11111110
-00000004
-00000000
-55555554
-00000000
-00000000
-00000000
-00000002
-00000000
-00000002
-00000002
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000000
-00000002
-00000000
-00000000
-00000002
-00000002
-00000000
-00000002
-00000000
-00000002
-0000b504
-00000004
-00002404
-00003104
-00000004
-0000a000
-00001504
-00000004
-0000b500
-00000000
-00002404
-00003100
-00001504
-00000000
-0000b504
-00000004
-00002404
-00003100
-00000004
-0000a000
-00001504
-00000000
-00000004
-ffff4afc
-66664264
-33330234
-00000004
-aaaa0aa8
-55554054
-00000004
-00000000
-00000000
-66664264
-33330230
-55554054
-00000000
-00000004
-ffff4afc
-66664264
-33330230
-00000004
-aaaa0aa8
-55554054
-00000000
-00002404
-66664264
-66666666
-22222224
-00000006
-22222222
-44444446
-00000004
-00002402
-00000000
-66666664
-22222222
-44444444
-00000002
-00002404
-66664264
-66666666
-22222222
-00000004
-22222222
-44444444
-00000002
-00003101
-33330231
-22222223
-33333330
-00000002
-22222223
-11111112
-00000000
-00003103
-00040000
-00100000
-fff7fffd
-fffdfff6
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output
deleted file mode 100644
index aefc28d98..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output
+++ /dev/null
@@ -1,556 +0,0 @@
-00000000
-0000002c
-00000004
-00000007
-00000040
-f7fffffb
-00000332
-00000006
-00000000
-00000002
-00000010
-ffdfffbf
-00000006
-fff7fffc
-000007ff
-00000000
-00000334
-00000003
-00000002
-00000200
-ffffeaaa
-00000008
-00000332
-00000080
-00000003
-0000002d
-ffffff93
-ffffffd3
-fffffaaa
-00000334
-00000001
-00000004
-fffffbfe
-66666465
-02000000
-00010000
-00000008
-55555546
-00080000
-00000001
-00000004
-00000000
-00000000
-00000000
-00000000
-00000000
-04000000
-00000000
-00800000
-00000000
-00000000
-00000000
-00040000
-00020000
-00008000
-00004000
-00000000
-00000000
-00000800
-00000400
-00000200
-00000100
-00000000
-00000040
-00000000
-00000000
-00000004
-00000000
-00000001
-00000004
-0000b504
-00000405
-00000104
-00000004
-0000b001
-00000504
-00000004
-00000004
-00000000
-00000405
-00000100
-00000504
-00000000
-00000005
-0000b501
-00000404
-00000101
-00000005
-0000b000
-00000505
-00000001
-0000002c
-ffff4ad4
-00000265
-00000234
-00000004
-ffff4aa9
-00000054
-00000004
-0000002c
-00000000
-00000265
-00000230
-00000054
-00000000
-0000002d
-ffff4ad1
-00000264
-00000231
-00000005
-ffff4aa8
-00000055
-00000001
-00000026
-66666644
-00000667
-00000224
-00000006
-66666223
-00000446
-00000004
-00000024
-00000000
-00000665
-00000222
-00000444
-00000002
-00000025
-66666643
-00000666
-00000223
-00000005
-66666222
-00000445
-00000003
-00000024
-33333314
-00000224
-00000334
-00000004
-33333220
-00000114
-00000004
-00000024
-00000000
-00000224
-00000330
-00000114
-00000000
-00000024
-33333310
-00000224
-00000330
-00000004
-33333220
-00000114
-00000000
-00000006
-00000004
-00000006
-00000004
-00000006
-00000002
-00000006
-00000004
-00000004
-00000000
-00000004
-00000002
-00000004
-00000002
-00000004
-00000002
-00000006
-00000002
-00000004
-00000002
-00000004
-00000002
-0000002a
-aaaaaa80
-00000223
-00000220
-00000002
-aaaaaaab
-00000002
-00000000
-00000028
-00000000
-00000221
-00000222
-00000000
-00000002
-00000029
-aaaaaa83
-00000222
-00000223
-00000001
-aaaaaaaa
-00000001
-00000003
-00000006
-55555554
-00000446
-00000114
-00000006
-55555002
-00000556
-00000004
-00000004
-00000000
-00000444
-00000112
-00000554
-00000002
-00000004
-55555552
-00000446
-00000112
-00000004
-55555002
-00000554
-00000002
-00000004
-00000004
-00000004
-00000004
-00000004
-00000000
-00000004
-00000004
-00000004
-00000000
-00000004
-00000000
-00000004
-00000000
-00000004
-00000000
-00000000
-00000004
-00000000
-00000004
-00000000
-00000002
-0000b500
-00000403
-00000100
-00000002
-0000b003
-00000502
-00000000
-00000000
-00000000
-00000401
-00000102
-00000500
-00000002
-00000001
-0000b503
-00000402
-00000103
-00000001
-0000b002
-00000501
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000024
-66666644
-00000665
-00000224
-00000004
-66666221
-00000444
-00000004
-00000024
-00000000
-00000665
-aaaaaaaa
-00000002
-00000000
-00000028
-00000000
-00000220
-00000222
-00000000
-00000002
-00000028
-aaaaaa82
-00000222
-00000222
-00000000
-aaaaaaaa
-00000000
-00000002
-00000004
-55555554
-00000445
-00000114
-00000004
-55555001
-00000554
-00000004
-00000004
-00000000
-00000445
-00000110
-00000554
-00000000
-00000005
-55555551
-00000444
-00000111
-00000005
-55555000
-00000555
-00000001
-00000002
-00000000
-00000003
-00000000
-00000002
-00000003
-00000002
-00000000
-00000000
-00000000
-00000001
-00000002
-00000000
-00000002
-00000001
-00000003
-00000002
-00000003
-00000001
-00000002
-00000001
-00000003
-00000220
-00000444
-00000000
-00000025
-66666641
-00000664
-00000221
-00000005
-66666220
-00000445
-00000001
-00000022
-33333310
-00000222
-00000330
-00000002
-33333222
-00000112
-00000000
-00000020
-00000000
-00000220
-00000332
-00000110
-00000002
-00000020
-33333312
-00000222
-00000332
-00000000
-33333222
-00000110
-00000002
-00000004
-55555554
-00000444
-00000114
-00000004
-55555000
-00000554
-00000004
-00000004
-00000000
-00000444
-00000110
-00000554
-00000000
-00000004
-55555550
-00000444
-00000110
-00000004
-55555000
-00000554
-00000000
-00000002
-00000000
-00000002
-00000000
-00000002
-00000002
-00000002
-00000000
-00000000
-00000000
-00000000
-00000002
-00000000
-00000002
-00000000
-00000002
-00000002
-00000002
-00000000
-00000002
-00000000
-00000002
-00000004
-0000b504
-00000404
-00000104
-00000004
-0000b000
-00000504
-00000004
-00000004
-00000000
-00000404
-00000100
-00000504
-00000000
-00000004
-0000b500
-00000404
-00000100
-00000004
-0000b000
-00000504
-00000000
-0000002c
-ffff4ad4
-00000264
-00000234
-00000004
-ffff4aa8
-00000054
-00000004
-0000002c
-00000000
-00000264
-00000230
-00000054
-00000000
-0000002c
-ffff4ad0
-00000264
-00000230
-00000004
-ffff4aa8
-00000054
-00000000
-00000026
-66666644
-00000666
-00000224
-00000006
-66666222
-00000446
-00000004
-00000024
-00000000
-00000664
-00000222
-00000444
-00000002
-00000024
-66666642
-00000666
-00000222
-00000004
-66666222
-00000444
-00000002
-00000022
-33333310
-00000223
-00000330
-00000002
-33333223
-00000112
-00000000
-00000020
-00000000
-00000221
-00000332
-00000110
-00000002
-00000021
-33333313
-00000222
-00000333
-00000001
-33333222
-00000111
-00000003
-00000004
-00000004
-00000005
-00000004
-00000004
-00000001
-00000004
-00000004
-00000004
-00000000
-00000005
-00000000
-00000004
-00000000
-00000005
-00000001
-00000004
-00000001
-00000005
-00000000
-00000005
-00000001
-0000002a
-aaaaaa80
-00000222
-00000220
-00000002
-00000002
-00000555
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output
deleted file mode 100644
index 5f432d03a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output
+++ /dev/null
@@ -1,64 +0,0 @@
-fffff000
-7ffff000
-bffff000
-dffff000
-effff000
-f7fff000
-fbfff000
-fdfff000
-fefff000
-00000000
-ffbff000
-ffdff000
-ffeff000
-fff7f000
-fffbf000
-fffdf000
-fffef000
-ffff7000
-ffffb000
-ffffd000
-ffffe000
-80000000
-40000000
-20000000
-10000000
-08000000
-04000000
-02000000
-01000000
-00800000
-00400000
-00200000
-00100000
-00080000
-00040000
-00020000
-00010000
-55555000
-00003000
-aaaaa000
-00000000
-00008000
-00004000
-00002000
-00001000
-002d5000
-66667000
-33334000
-00006000
-aaaab000
-55556000
-003fe000
-002d3000
-66665000
-33332000
-aaaa9000
-55554000
-003ff000
-002d4000
-66666000
-33333000
-00005000
-ff7ff000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output
deleted file mode 100644
index becb2fbf7..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output
+++ /dev/null
@@ -1,592 +0,0 @@
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output
deleted file mode 100644
index fe7d8af34..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output
+++ /dev/null
@@ -1,588 +0,0 @@
-00000001
-00000002
-00000001
-00000002
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000002
-00000002
-00000002
-00000003
-00000001
-00000002
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000003
-00000002
-00000002
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000003
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000003
-00000003
-00000002
-00000003
-00000001
-00000003
-00000003
-00000003
-00000002
-00000001
-00000003
-00000002
-00000003
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000001
-00000002
-00000003
-00000001
-00000001
-00000002
-00000002
-00000002
-00000001
-00000003
-00000003
-00000002
-00000002
-00000003
-00000003
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000002
-00000001
-00000001
-00000001
-00000002
-00000001
-00000001
-00000003
-00000002
-00000003
-00000002
-00000001
-00000003
-00000003
-00000002
-00000003
-00000001
-00000001
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000001
-00000001
-00000002
-00000003
-00000002
-00000001
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000003
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000001
-00000002
-00000003
-00000001
-00000001
-00000003
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000003
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000001
-00000001
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000002
-00000003
-00000002
-00000003
-00000003
-00000001
-00000002
-00000001
-00000003
-00000003
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000001
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000001
-00000003
-00000003
-00000003
-00000002
-00000001
-00000001
-00000003
-00000003
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000001
-00000001
-00000001
-00000003
-00000001
-00000001
-00000003
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000003
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000003
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000003
-00000001
-00000002
-00000001
-00000003
-00000003
-00000002
-00000003
-00000001
-00000003
-00000001
-00000003
-00000002
-00000001
-00000001
-00000003
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000001
-00000001
-00000002
-00000002
-00000002
-00000003
-00000003
-00000001
-00000002
-00000002
-00000001
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000003
-00000001
-00000002
-00000003
-00000001
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output
deleted file mode 100644
index 14516e603..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output
+++ /dev/null
@@ -1,728 +0,0 @@
-00000001
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000002
-00000001
-00000002
-00000001
-00000002
-00000003
-00000003
-00000002
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000002
-00000003
-00000001
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000003
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000002
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000003
-00000001
-00000001
-00000002
-00000003
-00000002
-00000002
-00000003
-00000003
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000001
-00000001
-00000002
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000001
-00000002
-00000003
-00000003
-00000003
-00000003
-00000002
-00000001
-00000003
-00000002
-00000003
-00000001
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000001
-00000003
-00000001
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000001
-00000001
-00000003
-00000002
-00000001
-00000001
-00000002
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000001
-00000002
-00000003
-00000001
-00000003
-00000001
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000003
-00000001
-00000002
-00000003
-00000002
-00000002
-00000003
-00000003
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000002
-00000003
-00000002
-00000001
-00000003
-00000003
-00000001
-00000002
-00000001
-00000003
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000001
-00000001
-00000003
-00000002
-00000002
-00000002
-00000002
-00000001
-00000001
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000001
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000001
-00000002
-00000003
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000003
-00000001
-00000002
-00000001
-00000001
-00000002
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000002
-00000003
-00000001
-00000001
-00000001
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000001
-00000001
-00000001
-00000001
-00000002
-00000003
-00000002
-00000002
-00000003
-00000001
-00000001
-00000002
-00000001
-00000003
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000001
-00000001
-00000003
-00000001
-00000001
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000001
-00000003
-00000003
-00000003
-00000002
-00000001
-00000002
-00000003
-00000001
-00000001
-00000003
-00000002
-00000001
-00000001
-00000002
-00000001
-00000003
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000001
-00000003
-00000003
-00000002
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output
deleted file mode 100644
index cdd9263f4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output
+++ /dev/null
@@ -1,588 +0,0 @@
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000001
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000001
-00000002
-00000003
-00000003
-00000002
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000003
-00000001
-00000002
-00000001
-00000003
-00000003
-00000003
-00000002
-00000002
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000002
-00000002
-00000003
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000001
-00000002
-00000002
-00000003
-00000002
-00000003
-00000001
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000001
-00000003
-00000002
-00000002
-00000002
-00000003
-00000001
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000001
-00000003
-00000001
-00000002
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000002
-00000001
-00000001
-00000001
-00000002
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000001
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000001
-00000003
-00000003
-00000002
-00000003
-00000002
-00000003
-00000001
-00000002
-00000002
-00000001
-00000002
-00000003
-00000001
-00000001
-00000001
-00000003
-00000002
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000001
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000001
-00000001
-00000002
-00000003
-00000002
-00000003
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000003
-00000002
-00000001
-00000002
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000001
-00000003
-00000002
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000001
-00000003
-00000001
-00000002
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000001
-00000003
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000001
-00000002
-00000003
-00000001
-00000001
-00000002
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000002
-00000003
-00000001
-00000002
-00000002
-00000001
-00000002
-00000001
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000002
-00000001
-00000001
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000003
-00000002
-00000001
-00000003
-00000003
-00000002
-00000001
-00000002
-00000001
-00000001
-00000003
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000001
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000001
-00000003
-00000001
-00000002
-00000001
-00000001
-00000001
-00000002
-00000003
-00000003
-00000003
-00000002
-00000001
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000003
-00000003
-00000002
-00000001
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000003
-00000001
-00000001
-00000002
-00000002
-00000002
-00000001
-00000001
-00000002
-00000002
-00000003
-00000002
-00000001
-00000003
-00000003
-00000001
-00000001
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000002
-00000003
-00000001
-00000003
-00000002
-00000003
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000001
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output
deleted file mode 100644
index 8776eb6ab..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output
+++ /dev/null
@@ -1,728 +0,0 @@
-00000002
-00000003
-00000002
-00000001
-00000001
-00000001
-00000002
-00000003
-00000003
-00000002
-00000003
-00000003
-00000002
-00000001
-00000002
-00000002
-00000001
-00000003
-00000003
-00000002
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000001
-00000003
-00000003
-00000003
-00000001
-00000002
-00000002
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000001
-00000001
-00000003
-00000003
-00000002
-00000002
-00000002
-00000001
-00000003
-00000002
-00000001
-00000001
-00000002
-00000001
-00000002
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000002
-00000003
-00000003
-00000002
-00000003
-00000001
-00000002
-00000003
-00000002
-00000002
-00000003
-00000003
-00000001
-00000003
-00000002
-00000001
-00000002
-00000003
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000001
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000002
-00000001
-00000001
-00000003
-00000002
-00000003
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000001
-00000003
-00000003
-00000001
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000002
-00000001
-00000002
-00000001
-00000001
-00000001
-00000001
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000002
-00000003
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000001
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000002
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000001
-00000002
-00000003
-00000003
-00000002
-00000001
-00000002
-00000002
-00000001
-00000003
-00000001
-00000001
-00000002
-00000001
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000001
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000001
-00000003
-00000003
-00000001
-00000001
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000002
-00000002
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000001
-00000003
-00000002
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000001
-00000002
-00000001
-00000002
-00000001
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000003
-00000002
-00000002
-00000001
-00000003
-00000001
-00000003
-00000002
-00000001
-00000002
-00000001
-00000001
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000003
-00000001
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000001
-00000002
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000002
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000003
-00000001
-00000003
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000002
-00000001
-00000002
-00000002
-00000003
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000003
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000002
-00000002
-00000001
-00000002
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000002
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000002
-00000002
-00000001
-00000002
-00000002
-00000002
-00000002
-00000003
-00000002
-00000002
-00000001
-00000003
-00000003
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output
deleted file mode 100644
index b537bf369..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output
+++ /dev/null
@@ -1,588 +0,0 @@
-00000002
-00000001
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000002
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000002
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000001
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000001
-00000001
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000001
-00000001
-00000002
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000002
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000002
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000002
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000002
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000001
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000002
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000002
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000002
-00000002
-00000003
-00000001
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000002
-00000001
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000002
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000003
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000002
-00000001
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000001
-00000002
-00000003
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000003
-00000001
-00000003
-00000001
-00000001
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000002
-00000001
-00000003
-00000003
-00000003
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000003
-00000001
-00000003
-00000003
-00000003
-00000001
-00000001
-00000001
-00000002
-00000003
-00000001
-00000001
-00000003
-00000001
-00000001
-00000001
-00000001
-00000001
-00000003
-00000003
-00000003
-00000003
-00000003
-00000001
-00000001
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output
deleted file mode 100644
index e23848aac..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output
+++ /dev/null
@@ -1,16 +0,0 @@
-00000025
-00000027
-0008001d
-0010001d
-00000000
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
-0010001d
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output
deleted file mode 100644
index 0793fe3ab..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output
+++ /dev/null
@@ -1,28 +0,0 @@
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000000
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000017
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output
deleted file mode 100644
index 4f84c0482..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output
+++ /dev/null
@@ -1,20 +0,0 @@
-fffffffe
-fffffffe
-fffffffe
-fffffffe
-ffffffca
-ffffffca
-ffffffca
-ffffffca
-ffffffbe
-ffffffbe
-fffffffe
-ffffffbe
-ffffffbe
-00000000
-ffffffba
-ffffffba
-ffffffba
-ffffffba
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output
deleted file mode 100644
index 74d8f0919..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output
+++ /dev/null
@@ -1,20 +0,0 @@
-00000000
-000000fe
-000000fe
-000000fe
-000000ca
-000000ca
-000000ca
-000000ca
-000000be
-000000be
-000000fe
-000000be
-000000be
-000000ba
-000000ba
-000000ba
-000000ba
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output
deleted file mode 100644
index 9ec95d1d4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output
+++ /dev/null
@@ -1,16 +0,0 @@
-ffffcafe
-ffffcafe
-ffffcafe
-ffffcafe
-ffffbabe
-ffffbabe
-ffffbabe
-ffffbabe
-00000000
-ffffcafe
-ffffcafe
-ffffcafe
-ffffcafe
-ffffcafe
-ffffcafe
-ffffcafe
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output
deleted file mode 100644
index eabf3f883..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output
+++ /dev/null
@@ -1,16 +0,0 @@
-0000cafe
-0000cafe
-0000cafe
-0000cafe
-0000babe
-0000cafe
-0000babe
-0000babe
-0000babe
-0000cafe
-0000cafe
-0000cafe
-0000cafe
-00000000
-0000cafe
-0000cafe
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output
deleted file mode 100644
index 0e37658c3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output
+++ /dev/null
@@ -1,64 +0,0 @@
-fffff000
-7ffff000
-bffff000
-dffff000
-effff000
-f7fff000
-fbfff000
-fdfff000
-fefff000
-ff7ff000
-ffbff000
-ffdff000
-ffeff000
-00000000
-fffbf000
-fffdf000
-fffef000
-ffff7000
-ffffb000
-ffffd000
-ffffe000
-80000000
-40000000
-20000000
-10000000
-08000000
-04000000
-02000000
-01000000
-00800000
-00400000
-00200000
-00100000
-00080000
-00040000
-00020000
-00010000
-55555000
-00003000
-aaaaa000
-00000000
-00008000
-00004000
-00002000
-00001000
-002d5000
-66667000
-33334000
-00006000
-aaaab000
-55556000
-003fe000
-002d3000
-66665000
-33332000
-aaaa9000
-55554000
-003ff000
-002d4000
-66666000
-33333000
-00005000
-fff7f000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output
deleted file mode 100644
index 0f578dfe8..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output
+++ /dev/null
@@ -1,16 +0,0 @@
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-00000000
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
-babecafe
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output
deleted file mode 100644
index ee838bce3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output
+++ /dev/null
@@ -1,592 +0,0 @@
-ffdfffff
-7fffffff
-ffffffff
-c0000000
-00004000
-ffffffff
-ffffffff
-fdffffff
-00000000
-00000006
-ffbfffff
-ffdfffff
-ffefffff
-fff7ffff
-fffbffff
-ffffffff
-fffeffff
-ffff7fff
-ffffffff
-ffffdfff
-ffffefff
-fffff7ff
-ffffffff
-fffffdff
-fffffeff
-ffffffff
-ffffffbf
-ffffffdf
-ffffffff
-ffffffff
-fffffffb
-ffffffff
-fffffffe
-bfffffff
-ffffffff
-ffffffff
-ffffffff
-fdffffff
-ffffffff
-ff7fffff
-ffffffff
-ffefffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffff7fff
-ffffbfff
-ffffefff
-ffffffff
-fffffbff
-fffffeff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-fffffffb
-80000005
-40008000
-fffff7ff
-08000008
-aeaaaaaa
-0200b504
-ffffdfff
-fffffff9
-00400010
-ffffffff
-ffff4afd
-0004b503
-00020008
-fffffffe
-55557556
-00001002
-00000804
-80000200
-3fffffff
-00000060
-fffff7ff
-00080004
-fffffdff
-00000001
-ffffff7f
-22000000
-10000000
-24000000
-fffffffa
-01400000
-55d55555
-fffffff6
-33333334
-00100080
-00050000
-00021000
-00010006
-00002008
-fffffffd
-55555d55
-00000220
-ffffff7f
-02000001
-0000b505
-fffffffd
-6666f767
-3333b735
-0000b507
-aaaabfaf
-5555f557
-0000b505
-0000b507
-0000b505
-6666f765
-3333b737
-5555f555
-0000b507
-0000b505
-fffffffd
-6666f767
-3333b737
-0000b505
-aaaabfaf
-5555f555
-0000b507
-fffffffd
-ffff4afd
-ffff6eff
-ffff7bfd
-ffff4aff
-ffffeaff
-ffff5fff
-ffff4afd
-ffffffff
-ffff4afd
-ffff6efd
-ffff7bff
-ffff5ffd
-ffff4aff
-fffffffd
-ffff4afd
-ffff6eff
-ffff7bff
-ffff4afd
-ffffeaff
-ffff5ffd
-ffff4aff
-6666f767
-ffff6eff
-66666667
-77777777
-66666667
-eeeeeeef
-77777777
-66666667
-6666f767
-66666667
-66666667
-77777777
-77777777
-66666667
-6666f767
-ffff6eff
-66666667
-77777777
-66666667
-eeeeeeef
-77777777
-66666667
-3333b735
-ffff7bfd
-77777777
-33333334
-33333336
-bbbbbbbf
-77777776
-33333334
-3333b737
-33333334
-77777775
-33333336
-77777774
-33333336
-3333b734
-ffff7bfc
-77777776
-33333337
-33333335
-bbbbbbbe
-77777775
-33333337
-0000b507
-ffff4aff
-66666667
-33333336
-00000006
-aaaaaaaf
-55555556
-00000006
-0000b507
-00000006
-66666667
-33333336
-55555556
-00000006
-0000b506
-ffff4afe
-66666666
-33333337
-00000007
-aaaaaaae
-55555557
-00000007
-aaaabfaf
-ffffeaff
-eeeeeeef
-bbbbbbbf
-aaaaaaaf
-aaaaaaab
-ffffffff
-aaaaaaaf
-aaaabfab
-aaaaaaab
-eeeeeeef
-bbbbbbbb
-ffffffff
-aaaaaaab
-aaaabfaf
-ffffeaff
-eeeeeeef
-bbbbbbbb
-aaaaaaaf
-aaaaaaab
-ffffffff
-aaaaaaab
-5555f557
-ffff5fff
-77777777
-77777776
-55555556
-ffffffff
-55555556
-55555556
-5555f557
-55555556
-77777777
-77777776
-55555556
-55555556
-5555f556
-ffff5ffe
-77777776
-77777777
-55555557
-fffffffe
-55555557
-55555557
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaaf
-55555556
-00000004
-0000b507
-00000004
-66666665
-33333336
-55555554
-00000006
-0000b504
-ffff4afc
-66666666
-33333337
-00000005
-aaaaaaae
-55555555
-00000007
-0000b507
-ffffffff
-6666f767
-3333b737
-0000b507
-aaaabfab
-5555f557
-0000b507
-0000b503
-0000b503
-6666f767
-3333b733
-5555f557
-0000b503
-0000b507
-ffffffff
-6666f767
-3333b733
-0000b507
-aaaabfab
-5555f557
-0000b503
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000003
-6666f765
-ffff6efd
-66666667
-77777775
-66666667
-eeeeeeef
-77777777
-66666665
-6666f767
-66666665
-33333333
-77777777
-33333333
-77777777
-33333333
-3333b737
-ffff7bff
-77777777
-33333333
-33333337
-bbbbbbbb
-77777777
-33333333
-0000b505
-ffff4afd
-66666667
-33333335
-00000007
-aaaaaaaf
-55555557
-00000005
-0000b507
-00000005
-66666665
-33333337
-55555555
-00000007
-0000b505
-ffff4afd
-66666667
-33333337
-00000005
-aaaaaaaf
-55555555
-00000007
-aaaabfaf
-ffffeaff
-eeeeeeef
-bbbbbbbe
-aaaaaaae
-aaaaaaab
-fffffffe
-aaaaaaae
-aaaabfab
-aaaaaaaa
-eeeeeeef
-bbbbbbba
-fffffffe
-aaaaaaaa
-aaaabfae
-ffffeafe
-eeeeeeee
-bbbbbbbb
-aaaaaaaf
-aaaaaaaa
-ffffffff
-aaaaaaab
-5555f555
-ffff5ffd
-77777777
-77777775
-55555557
-ffffffff
-55555557
-55555555
-5555f557
-55555555
-77777775
-77777777
-55555555
-55555557
-5555f555
-ffff5ffd
-77777777
-77777777
-55555555
-ffffffff
-55555555
-55555557
-0000b507
-ffff4aff
-66666667
-33333337
-00000007
-aaaaaaab
-55555557
-00000007
-0000b503
-00000003
-66666667
-33333333
-55555557
-00000003
-0000b507
-ffff4aff
-66666667
-33333333
-00000007
-aaaaaaab
-55555557
-00000003
-66666665
-77777777
-77777775
-66666667
-6666f765
-ffff6efd
-66666667
-77777777
-66666665
-eeeeeeef
-77777775
-66666667
-3333b737
-ffff7bff
-77777777
-33333336
-33333336
-bbbbbbbb
-77777776
-33333336
-3333b733
-33333332
-77777777
-33333332
-77777776
-33333332
-3333b736
-ffff7bfe
-77777776
-33333333
-33333337
-bbbbbbba
-77777777
-33333333
-5555f555
-ffff5ffd
-77777777
-77777774
-55555556
-ffffffff
-55555556
-55555554
-5555f557
-55555554
-77777775
-77777776
-55555554
-55555556
-5555f554
-ffff5ffc
-77777776
-77777777
-55555555
-fffffffe
-55555555
-55555557
-0000b507
-ffff4aff
-66666667
-33333336
-00000006
-aaaaaaab
-55555556
-00000006
-0000b503
-00000002
-66666667
-33333332
-55555556
-00000002
-0000b506
-ffff4afe
-66666666
-33333333
-00000007
-aaaaaaaa
-55555557
-00000003
-0000b505
-fffffffd
-6666f767
-3333b734
-0000b506
-aaaabfaf
-5555f556
-0000b504
-0000b507
-0000b504
-6666f765
-3333b736
-5555f554
-0000b506
-0000b504
-fffffffc
-6666f766
-3333b737
-0000b505
-aaaabfae
-5555f555
-0000b507
-fffffffd
-ffff4afd
-ffff6eff
-ffff7bfc
-ffff4afe
-ffffeaff
-ffff5ffe
-ffff4afc
-ffffffff
-ffff4afc
-ffff6efd
-ffff7bfe
-ffff5ffc
-ffff4afe
-fffffffc
-ffff4afc
-ffff6efe
-ffff7bff
-ffff4afd
-ffffeafe
-ffff5ffd
-ffff4aff
-6666f767
-ffff6eff
-66666667
-77777776
-66666666
-eeeeeeef
-77777776
-66666666
-6666f767
-66666666
-66666667
-77777776
-77777776
-66666666
-6666f766
-ffff6efe
-66666666
-77777777
-66666667
-eeeeeeee
-77777777
-66666667
-3333b737
-ffff7bff
-77777777
-33333337
-33333337
-bbbbbbbb
-77777777
-33333337
-3333b733
-dfffffff
-efffffff
-feffffff
-ff7fffff
-ffffffff
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output
deleted file mode 100644
index e092fd1af..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output
+++ /dev/null
@@ -1,560 +0,0 @@
-fffff800
-00000000
-bfffffff
-dfffffff
-efffffff
-f7ffffff
-fbffffff
-fdffffff
-feffffff
-ffffffff
-ffffffff
-ffdfffff
-ffffffff
-ffffffff
-fffbffff
-fffdffff
-fffeffff
-ffff7fff
-ffffbfff
-ffffffff
-ffffffff
-fffff7ff
-ffffffff
-fffffdff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-fffffff7
-fffffffb
-ffffffff
-ffffffff
-000027ff
-fffffbff
-fffffdff
-ffffffff
-ffffffff
-ffffffff
-80000000
-fffffffe
-20000555
-fffffaaa
-ffffffff
-04000332
-02000556
-fffffbff
-fffffeff
-00400000
-ffffffdf
-fffffbff
-00040556
-00010001
-00008200
-ffffffd4
-fffffff8
-fffffff8
-ffffffd3
-ffffffd4
-00000102
-00000080
-00000046
-fffffff4
-00000555
-fffffffe
-000003ff
-00000002
-00000001
-20000100
-00000044
-33333334
-33333333
-fffffff8
-0000b52f
-ffffffd5
-0000b767
-0000b735
-0000b507
-ffffffaf
-0000b557
-0000b505
-0000b52d
-0000b505
-0000b765
-0000b737
-0000b555
-0000b507
-0000b52d
-ffffffd7
-0000b767
-0000b737
-0000b505
-ffffffaf
-0000b555
-0000b507
-ffff4aff
-fffffffd
-ffff4eff
-ffff4bfd
-ffff4aff
-fffffaff
-ffff4fff
-ffff4afd
-ffff4afd
-ffff4afd
-ffff4efd
-ffff4bff
-ffff4ffd
-ffff4aff
-ffff4afd
-ffffffff
-ffff4eff
-ffff4bff
-ffff4afd
-fffffaff
-ffff4ffd
-ffff4aff
-6666666f
-fffffff7
-66666667
-66666777
-66666667
-fffffeef
-66666777
-66666667
-6666666f
-66666667
-66666667
-66666777
-66666777
-66666667
-6666666f
-fffffff7
-66666667
-66666777
-66666667
-fffffeef
-66666777
-66666667
-3333333e
-fffffff4
-33333777
-33333334
-33333336
-fffffbbf
-33333776
-33333334
-3333333c
-33333334
-33333775
-33333336
-33333774
-33333336
-3333333d
-fffffff7
-33333776
-33333337
-33333335
-fffffbbe
-33333775
-33333337
-0000002e
-ffffffd6
-00000667
-00000336
-00000006
-fffffaaf
-00000556
-00000006
-0000002e
-00000006
-00000667
-00000336
-00000556
-00000006
-0000002f
-ffffffd7
-00000666
-00000337
-00000007
-fffffaae
-00000557
-00000007
-aaaaaaaf
-ffffffff
-aaaaaeef
-aaaaabbf
-aaaaaaaf
-fffffaab
-aaaaafff
-aaaaaaaf
-aaaaaaaf
-aaaaaaab
-aaaaaeef
-aaaaabbb
-aaaaafff
-aaaaaaab
-aaaaaaaf
-fffffffb
-aaaaaeef
-aaaaabbb
-aaaaaaaf
-fffffaab
-aaaaafff
-aaaaaaab
-5555557e
-ffffffd6
-55555777
-55555776
-55555556
-ffffffff
-55555556
-55555556
-5555557e
-55555556
-55555777
-55555776
-55555556
-55555556
-5555557f
-ffffffd7
-55555776
-55555777
-55555557
-fffffffe
-55555557
-55555557
-0000002e
-ffffffd4
-00000667
-00000334
-00000006
-fffffaaf
-00000556
-00000004
-0000002c
-00000004
-00000665
-00000336
-00000554
-00000006
-0000002d
-ffffffd7
-00000666
-00000337
-00000005
-fffffaae
-00000555
-00000007
-0000b52f
-ffffffd7
-0000b767
-0000b737
-0000b507
-ffffffab
-0000b557
-0000b507
-0000b52f
-0000b503
-0000b767
-0000b733
-0000b557
-0000b503
-0000b52f
-ffffffd3
-0000b767
-0000b733
-0000b507
-ffffffab
-0000b557
-0000b503
-0000002e
-ffffffd4
-00000667
-00000334
-00000006
-fffffaab
-00000556
-00000004
-0000002c
-00000000
-00000665
-00000332
-00000554
-00000002
-0000002d
-ffffffd3
-00000666
-00000333
-00000005
-fffffaaa
-00000555
-00000003
-6666666f
-fffffff5
-66666667
-66666775
-66666667
-fffffeef
-66666777
-66666665
-6666666d
-fffffaab
-aaaaaffe
-aaaaaaae
-aaaaaaae
-aaaaaaaa
-aaaaaeef
-aaaaabba
-aaaaaffe
-aaaaaaaa
-aaaaaaaf
-fffffffb
-aaaaaeee
-aaaaabbb
-aaaaaaaf
-fffffaaa
-aaaaafff
-aaaaaaab
-5555557f
-ffffffd5
-55555777
-55555775
-55555557
-ffffffff
-55555557
-55555555
-5555557d
-55555555
-55555775
-55555777
-55555555
-55555557
-5555557d
-ffffffd7
-55555777
-55555777
-55555555
-ffffffff
-55555555
-55555557
-0000002f
-ffffffd7
-00000667
-00000337
-00000007
-fffffaab
-00000557
-00000007
-0000002f
-00000003
-00000667
-00000333
-00000557
-00000003
-0000002f
-ffffffd3
-00000667
-00000333
-00000007
-fffffaab
-00000557
-00000003
-66666665
-66666665
-66666777
-66666775
-66666667
-6666666d
-fffffff7
-66666667
-66666777
-66666665
-fffffeef
-66666775
-66666667
-3333333e
-fffffff6
-33333777
-33333336
-33333336
-fffffbbb
-33333776
-33333336
-3333333e
-33333332
-33333777
-33333332
-33333776
-33333332
-3333333f
-fffffff3
-33333776
-33333333
-33333337
-fffffbba
-33333777
-33333333
-5555557e
-ffffffd4
-55555777
-55555774
-55555556
-ffffffff
-55555556
-55555554
-5555557c
-55555554
-55555775
-55555776
-55555554
-55555556
-5555557d
-ffffffd7
-55555776
-55555777
-55555555
-fffffffe
-55555555
-55555557
-0000002e
-ffffffd6
-00000667
-00000336
-00000006
-fffffaab
-00000556
-00000006
-0000002e
-00000002
-00000667
-00000332
-00000556
-0000002f
-ffffffd3
-00000666
-00000333
-00000007
-fffffaaa
-00000557
-00000003
-0000b52e
-ffffffd4
-0000b767
-0000b734
-0000b506
-ffffffaf
-0000b556
-0000b504
-0000b52c
-0000b504
-0000b765
-0000b736
-0000b554
-0000b506
-0000b52d
-ffffffd7
-0000b766
-0000b737
-0000b505
-ffffffae
-0000b555
-0000b507
-ffff4afe
-fffffffc
-ffff4eff
-ffff4bfc
-ffff4afe
-fffffaff
-ffff4ffe
-ffff4afc
-ffff4afc
-ffff4afc
-ffff4efd
-ffff4bfe
-ffff4ffc
-ffff4afe
-ffff4afd
-ffffffff
-ffff4efe
-ffff4bff
-ffff4afd
-fffffafe
-ffff4ffd
-ffff4aff
-6666666e
-fffffff6
-66666667
-66666776
-66666666
-fffffeef
-66666776
-66666666
-6666666e
-66666666
-66666667
-66666776
-66666776
-66666666
-6666666f
-fffffff7
-66666666
-66666777
-66666667
-fffffeee
-66666777
-66666667
-3333333f
-fffffff7
-33333777
-33333337
-33333337
-fffffbbb
-33333777
-33333337
-3333333f
-33333333
-33333777
-33333333
-33333777
-33333333
-3333333f
-fffffff3
-33333777
-33333333
-33333337
-fffffbbb
-33333777
-33333333
-0000002f
-ffffffd5
-00000667
-00000335
-00000007
-fffffaaf
-00000557
-00000005
-0000002d
-00000005
-00000665
-00000337
-00000555
-00000007
-0000002d
-ffffffd7
-00000667
-00000337
-00000005
-fffffaaf
-00000555
-00000007
-aaaaaaae
-fffffffe
-aaaaaeef
-aaaaabbe
-aaaaaaae
-7fffffff
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output
deleted file mode 100644
index 9c4bc8218..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output
+++ /dev/null
@@ -1,80 +0,0 @@
-deadbe00
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbeff
-deadbe7f
-deadbebf
-deadbedf
-deadbeef
-deadbef7
-deadbefb
-deadbefd
-deadbefe
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe01
-deadbeaa
-deadbe55
-deadfbef
-deadffef
-dead08ef
-deadf8ef
-de00beef
-debfbeef
-def8beef
-de09beef
-10adbeef
-ffadbeef
-00adbeef
-deadbe40
-00adbeef
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe00
-deadbe80
-deadbe20
-deadbe04
-deadbe02
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output
deleted file mode 100644
index 7e989c340..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output
+++ /dev/null
@@ -1,72 +0,0 @@
-dead0001
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-deadffff
-dead0000
-deadffff
-deadffff
-deadffff
-dead7fff
-deadbfff
-deaddfff
-deadefff
-deadf7ff
-deadfbff
-deadfdff
-deadfeff
-deadff7f
-deadffbf
-deadffdf
-deadffef
-deadfff7
-deadfffb
-deadfffd
-deadfffe
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-deadaaaa
-dead5555
-ffffbeef
-0800beef
-0003beef
-fffabeef
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead0000
-dead8000
-dead4000
-dead2000
-dead1000
-dead0400
-dead0200
-dead0100
-dead0080
-dead0040
-dead0020
-dead0010
-dead0008
-dead0004
-dead0002
-deadffff
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output
deleted file mode 100644
index bce59d089..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output
+++ /dev/null
@@ -1,88 +0,0 @@
-c0000000
-fff78000
-7f800000
-c0000000
-00000000
-c0000000
-fffffe00
-fffe0000
-bffffffe
-ffffc000
-c0000000
-ff800000
-ffffff00
-ffffe000
-ffe00000
-fffff800
-fffff800
-ffbffffc
-effffe00
-ffff8000
-f7fffc00
-fffbfffc
-fff7fff0
-ffffbfff
-fbffe000
-c0000000
-f7ff0000
-ffff7fe0
-ffffbfe0
-ff7f0000
-ffdf0000
-fff70000
-fffd8000
-ffffffd0
-fffffff8
-00000000
-00000000
-00000000
-20000000
-00000000
-80000000
-10000000
-00000000
-08000000
-00400000
-00000000
-00000000
-04000000
-00000000
-00000000
-00000000
-08000000
-00000000
-00200000
-00400000
-00200000
-08000000
-00000000
-00008000
-00000000
-00010000
-00008000
-08000000
-00000000
-10000000
-80000000
-a8280000
-ff4afd00
-9999999c
-66666680
-000c0000
-55560000
-aab00000
-0000b503
-00060000
-aaaa0000
-55540000
-00000000
-00000008
-66666500
-cccc8000
-55555554
-d4100000
-ccc00000
-ccccccc0
-00001400
-e0000000
-80000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output
deleted file mode 100644
index 883654689..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output
+++ /dev/null
@@ -1,92 +0,0 @@
-80000000
-f8000000
-ffffff80
-bffffffe
-fffc0000
-f7ffffff
-00000000
-ffff8000
-fff80000
-ffff0000
-80000000
-f8000000
-fffff000
-effffe00
-fffbffff
-00000000
-f7fff800
-fffe0000
-f8000000
-bffe0000
-e0000000
-fdffc000
-ff800000
-ff7fc000
-fdfe0000
-ffdfc000
-ffefc000
-ffffdf00
-fffffbc0
-ffffff70
-fffb0000
-fffffa00
-ffffff00
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00400000
-08000000
-00000000
-00000000
-00000000
-00000000
-40000000
-08000000
-00004000
-00002000
-00002000
-00000000
-00400000
-00001000
-20000000
-00000000
-00001000
-00010000
-00000010
-00400000
-00000040
-00001000
-00004000
-fffffdfc
-5a828000
-7e800000
-38000000
-99a00000
-00003000
-aaac0000
-80000000
-000c0000
-aaaa0000
-aaaaaa80
-ffbffc00
-002d40c0
-cccca000
-66666664
-80000000
-6a080000
-57e00000
-c0000000
-cccccc00
-28000000
-ffffff80
-ffff0000
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output
deleted file mode 100644
index eb7f04427..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output
+++ /dev/null
@@ -1,584 +0,0 @@
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output
deleted file mode 100644
index a0b62cb23..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output
+++ /dev/null
@@ -1,564 +0,0 @@
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output
deleted file mode 100644
index be272395d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output
+++ /dev/null
@@ -1,700 +0,0 @@
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output
deleted file mode 100644
index a0e45d5ab..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output
+++ /dev/null
@@ -1,724 +0,0 @@
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000001
-00000001
-00000000
-00000001
-00000001
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output
deleted file mode 100644
index 40928fa2e..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output
+++ /dev/null
@@ -1,92 +0,0 @@
-aaaaaaaa
-ffffffef
-00000000
-ffffffff
-fff55555
-00000000
-000003ff
-dfffffff
-ffbfffff
-fff7ffff
-f7ffffff
-fffffff7
-00000000
-fffffbff
-ffffffbf
-ffffffff
-ffffffbf
-fffbffff
-fffffdff
-ffffffff
-fffffffe
-ffffffff
-ffffefff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-fffffffd
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-00000000
-fffff000
-00000008
-00100000
-00020000
-00000010
-00004000
-00000100
-00000080
-00800000
-00000800
-00001000
-00080000
-00000200
-00000000
-00000040
-00000040
-00000000
-00000000
-00000000
-00000008
-00000020
-00000000
-00000000
-00000010
-00000002
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-ffffff4a
-00006666
-000ccccc
-00000000
-000002aa
-00000000
-00000000
-00000aaa
-0000016a
-0000000c
-00000199
-00aaaaaa
-00000001
-ffffffff
-00000001
-00000001
-00000000
-fffffffd
-00000000
-fffeffff
-fffeffff
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output
deleted file mode 100644
index 23cef3334..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output
+++ /dev/null
@@ -1,88 +0,0 @@
-00000000
-0007ffff
-ff7fffff
-efffffff
-ffffffbf
-fffeffff
-ff7fffff
-00000000
-ffffffff
-ffffdfff
-ffffbfff
-ffffdfff
-ffffefff
-fffffbff
-ffffffff
-ffffefff
-fffffeff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffff7f
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-00000000
-fffffff5
-00000000
-e0000000
-10000000
-02000000
-00004000
-00000040
-00004000
-00010000
-00000400
-00001000
-00000020
-00020000
-00000000
-00000000
-00000002
-00000100
-00000001
-00000020
-00000000
-00000100
-00000020
-00000000
-00000000
-00000000
-00000020
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000016
-fffffffe
-00666666
-00033333
-00000000
-fff55555
-00000000
-00000001
-00000000
-00000002
-15555555
-00005a81
-00006666
-00000ccc
-0000000a
-00000000
-ffffffff
-00019999
-00000ccc
-ffffffff
-ffffffbf
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output
deleted file mode 100644
index 6cdc318c2..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output
+++ /dev/null
@@ -1,92 +0,0 @@
-fffffff7
-fffffffa
-000001ff
-00000001
-00000001
-00000002
-0000000f
-00001bff
-00000000
-00001eff
-0000001f
-03f7ffff
-0003fdff
-00ffbfff
-00000000
-00000007
-0fffbfff
-00fffdff
-00000003
-00000007
-003fffef
-0003ffff
-00000001
-00000003
-00007fff
-00000007
-0007ffff
-007fffff
-000007ff
-0003ffff
-fffffffb
-00000001
-07ffffff
-00000008
-00002d41
-08000000
-00000100
-01000000
-00080000
-00000400
-00001000
-00000080
-00004000
-00000010
-00000800
-00002000
-00000040
-00000002
-00000008
-00000000
-00000001
-00000001
-00000020
-00000040
-00000000
-00000000
-00000040
-00000000
-00000000
-00000004
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-03fffd2b
-00019999
-00199999
-00000000
-0002aaaa
-55555556
-00000005
-00000000
-0aaaaaaa
-00aaaaaa
-00000000
-0000000c
-00001999
-00000aaa
-00000000
-0ffff4af
-0000000c
-00000199
-00000000
-0000001f
-00000007
-0003bfff
-0ffdffff
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output
deleted file mode 100644
index 8cd9ce217..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output
+++ /dev/null
@@ -1,88 +0,0 @@
-00000001
-007fffff
-00000000
-037fffff
-003bffff
-3dffffff
-00003eff
-0000fdff
-7f7fffff
-00007fbf
-0001ff7f
-01ffbfff
-00000000
-000007ff
-0000fffb
-00007ffe
-001fffdf
-00003fff
-ffffbfff
-00001fff
-003ffffb
-000007ff
-03ffffef
-00001fff
-00fffffe
-00ffffff
-3ffffff7
-00003fff
-3ffffffd
-03ffffff
-0001ffff
-000fffff
-00000000
-00000006
-00000000
-00200000
-40000000
-00001000
-00000800
-00010000
-00000000
-00000040
-00000800
-00010000
-00010000
-00020000
-00000800
-00000100
-00000002
-00010000
-00000000
-00000100
-00000200
-00000000
-00000008
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000005
-01fffe95
-000ccccc
-0000cccc
-00000000
-55555555
-00005555
-00000000
-00000000
-00000000
-2aaaaaaa
-000aaaaa
-00000000
-00000333
-00cccccc
-01555555
-00000000
-00ffff4a
-00333333
-00000000
-00000000
-0000017f
-000ffeff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output
deleted file mode 100644
index 69e62adb8..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output
+++ /dev/null
@@ -1,584 +0,0 @@
-01c00000
-ffbfffff
-3ffffffb
-00000000
-00000000
-07fffffc
-04000001
-01fffc00
-01000011
-00800081
-00400003
-00200005
-000ffe00
-00000000
-00040001
-ffe20000
-0000fffc
-00008041
-f0004000
-33335333
-20001001
-ffc00800
-00000421
-fffc0200
-ffe00100
-ffff4b7e
-55555597
-00000023
-aaaaaabc
-00010009
-00040005
-0000b508
-ffff4aff
-d5555555
-bbffffff
-bfffffff
-f8008000
-fbffffff
-cbcccccb
-ccbccccb
-ff77ffff
-fffdfff9
-ffff0080
-fffecafc
-ffffbff7
-ffffe003
-fffbefff
-1ffff800
-07ffff00
-fffff77f
-0000ffc0
-0007ffe0
-001ffff0
-07fffff8
-ffffdffd
-2aaaaaab
-bfff7fff
-f2000000
-a2aaaaab
-fdffdfff
-feffffef
-ffe00010
-33233333
-fef7ffff
-00060000
-07ff0000
-001f8000
-f7ffbfff
-1ffff000
-3ffffc00
-ffff7dff
-55555454
-333332b3
-ffffffc4
-fffffbdf
-fffffff2
-ffbffffb
-00000000
-1fffffff
-7ffffc00
-0ffffffe
-00000000
-01040001
-08800001
-99d9999a
-80100000
-02020001
-00008000
-00003ffb
-ffff6afb
-00000f80
-80000800
-ff800400
-00000204
-e0000100
-ffffc008
-00020002
-00000000
-00016a08
-999a4e9e
-cccd81d1
-0000b4ff
-55560a5a
-aaab5faf
-0000b501
-00000002
-0000b505
-999a4ea0
-cccd81d3
-aaab5fb1
-0000b503
-00000001
-00016a09
-999a4e9f
-cccd81d2
-0000b500
-55560a5b
-aaab5fb0
-0000b502
-fffe95f8
-00000000
-9998e496
-cccc17c9
-ffff4af7
-5554a052
-aaa9f5a7
-ffff4af9
-fffe95fa
-ffff4afd
-9998e498
-cccc17cb
-aaa9f5a9
-ffff4afb
-fffe95f9
-00000001
-9998e497
-cccc17ca
-ffff4af8
-5554a053
-aaa9f5a8
-ffff4afa
-6665b162
-66671b6a
-00000000
-33333333
-66666661
-bbbbbbbc
-11111111
-66666663
-6665b164
-66666667
-00000002
-33333335
-11111113
-66666665
-6665b163
-66671b6b
-00000001
-33333334
-66666662
-bbbbbbbd
-11111112
-66666664
-33327e2f
-3333e837
-cccccccd
-00000000
-3333332e
-88888889
-ddddddde
-33333330
-33327e31
-33333334
-cccccccf
-00000002
-dddddde0
-33333332
-33327e30
-3333e838
-ccccccce
-00000001
-3333332f
-8888888a
-dddddddf
-33333331
-ffff4b01
-0000b509
-9999999f
-ccccccd2
-00000000
-5555555b
-aaaaaab0
-00000002
-ffff4b03
-00000006
-999999a1
-ccccccd4
-aaaaaab2
-00000004
-ffff4b02
-0000b50a
-999999a0
-ccccccd3
-00000001
-5555555c
-aaaaaab1
-00000003
-aaa9f5a6
-aaab5fae
-44444444
-77777777
-aaaaaaa5
-00000000
-55555555
-aaaaaaa7
-aaa9f5a8
-aaaaaaab
-44444446
-77777779
-55555557
-aaaaaaa9
-aaa9f5a7
-aaab5faf
-44444445
-77777778
-aaaaaaa6
-00000001
-55555556
-aaaaaaa8
-5554a051
-55560a59
-eeeeeeef
-22222222
-55555550
-aaaaaaab
-00000000
-55555552
-5554a053
-55555556
-eeeeeef1
-22222224
-00000002
-55555554
-5554a052
-55560a5a
-eeeeeef0
-22222223
-55555551
-aaaaaaac
-00000001
-55555553
-ffff4aff
-0000b507
-9999999d
-ccccccd0
-fffffffe
-55555559
-aaaaaaae
-00000000
-ffff4b01
-00000004
-9999999f
-ccccccd2
-aaaaaab0
-00000002
-ffff4b00
-0000b508
-9999999e
-ccccccd1
-ffffffff
-5555555a
-aaaaaaaf
-00000001
-fffffffe
-00016a06
-999a4e9c
-cccd81cf
-0000b4fd
-55560a58
-aaab5fad
-0000b4ff
-00000000
-0000b503
-999a4e9e
-cccd81d1
-aaab5faf
-0000b501
-ffffffff
-00016a07
-999a4e9d
-cccd81d0
-0000b4fe
-55560a59
-aaab5fae
-0000b500
-ffff4afb
-0000b503
-99999999
-cccccccc
-fffffffa
-55555555
-aaaaaaaa
-fffffffc
-ffff4afd
-00000000
-9999999b
-ccccccce
-aaaaaaac
-fffffffe
-ffff4afc
-0000b504
-9999999a
-cccccccd
-fffffffb
-55555556
-aaaaaaab
-fffffffd
-6665b160
-66671b68
-fffffffe
-33333331
-6666665f
-bbbbbbba
-1111110f
-66666661
-6665b162
-66666665
-33333333
-ccccccce
-00000001
-dddddddf
-33333331
-33327e2f
-3333e837
-cccccccd
-00000000
-3333332e
-88888889
-ddddddde
-33333330
-ffff4b00
-0000b508
-9999999e
-ccccccd1
-ffffffff
-5555555a
-aaaaaaaf
-00000001
-ffff4b02
-00000005
-999999a0
-ccccccd3
-aaaaaab1
-00000003
-ffff4b01
-0000b509
-9999999f
-ccccccd2
-00000000
-5555555b
-aaaaaab0
-00000002
-aaa9f5a5
-aaab5fad
-44444443
-77777776
-aaaaaaa4
-ffffffff
-55555554
-aaaaaaa6
-aaa9f5a7
-aaaaaaaa
-44444445
-77777778
-55555556
-aaaaaaa8
-aaa9f5a6
-aaab5fae
-44444444
-77777777
-aaaaaaa5
-00000000
-55555555
-aaaaaaa7
-5554a050
-55560a58
-eeeeeeee
-22222221
-5555554f
-aaaaaaaa
-ffffffff
-55555551
-5554a052
-55555555
-eeeeeef0
-22222223
-00000001
-55555553
-5554a051
-55560a59
-eeeeeeef
-22222222
-55555550
-aaaaaaab
-00000000
-55555552
-ffff4afe
-0000b506
-9999999c
-cccccccf
-fffffffd
-55555558
-aaaaaaad
-ffffffff
-ffff4b00
-00000003
-9999999e
-ccccccd1
-aaaaaaaf
-00000001
-ffff4aff
-0000b507
-9999999d
-ccccccd0
-fffffffe
-55555559
-aaaaaaae
-00000000
-00000000
-33333333
-11111111
-66666663
-6665b161
-66671b69
-ffffffff
-33333332
-66666660
-bbbbbbbb
-11111110
-66666662
-33327e2d
-3333e835
-cccccccb
-fffffffe
-3333332c
-88888887
-dddddddc
-3333332e
-33327e2f
-33333332
-cccccccd
-00000000
-ddddddde
-33333330
-33327e2e
-3333e836
-cccccccc
-ffffffff
-3333332d
-88888888
-dddddddd
-3333332f
-5554a04f
-55560a57
-eeeeeeed
-22222220
-5555554e
-aaaaaaa9
-fffffffe
-55555550
-5554a051
-55555554
-eeeeeeef
-22222222
-00000000
-55555552
-5554a050
-55560a58
-eeeeeeee
-22222221
-5555554f
-aaaaaaaa
-ffffffff
-55555551
-ffff4afd
-0000b505
-9999999b
-ccccccce
-fffffffc
-55555557
-aaaaaaac
-fffffffe
-ffff4aff
-00000002
-9999999d
-ccccccd0
-aaaaaaae
-ffff4afe
-0000b506
-9999999c
-cccccccf
-fffffffd
-55555558
-aaaaaaad
-ffffffff
-ffffffff
-00016a07
-999a4e9d
-cccd81d0
-0000b4fe
-55560a59
-aaab5fae
-0000b500
-00000001
-0000b504
-999a4e9f
-cccd81d2
-aaab5fb0
-0000b502
-00000000
-00016a08
-999a4e9e
-cccd81d1
-0000b4ff
-55560a5a
-aaab5faf
-0000b501
-fffe95f7
-ffffffff
-9998e495
-cccc17c8
-ffff4af6
-5554a051
-aaa9f5a6
-ffff4af8
-fffe95f9
-ffff4afc
-9998e497
-cccc17ca
-aaa9f5a8
-ffff4afa
-fffe95f8
-00000000
-9998e496
-cccc17c9
-ffff4af7
-5554a052
-aaa9f5a7
-ffff4af9
-6665b161
-66671b69
-ffffffff
-33333332
-66666660
-bbbbbbbb
-11111110
-66666662
-6665b163
-66666666
-00000001
-33333334
-11111112
-66666664
-6665b162
-66671b6a
-00000000
-33333333
-66666661
-bbbbbbbc
-11111111
-66666663
-33327e2e
-3333e836
-cccccccc
-ffffffff
-3333332d
-88888888
-dddddddd
-3333332f
-33327e30
-7fc00000
-1f800000
-0e000000
-0007ffff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output
deleted file mode 100644
index 3fff83574..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output
+++ /dev/null
@@ -1,68 +0,0 @@
-04000000
-7fffffff
-00000000
-dfffffff
-efffffff
-f7ffffff
-fbffffff
-fdffffff
-feffffff
-ff7fffff
-ffbfffff
-ffdfffff
-ffefffff
-fff7ffff
-fffbffff
-fffdffff
-fffeffff
-ffff7fff
-ffffbfff
-ffffdfff
-ffffefff
-fffff7ff
-fffffbff
-fffffdff
-fffffeff
-ffffff7f
-ffffffbf
-ffffffdf
-ffffffef
-fffffff7
-fffffffb
-fffffffd
-fffffffe
-80000000
-40000000
-20000000
-00000001
-aaaaaaaa
-55555555
-00000000
-10000000
-08000000
-02000000
-01000000
-00800000
-00400000
-00200000
-00100000
-00080000
-00040000
-00020000
-00010000
-00008000
-00004000
-00002000
-00001000
-00000800
-00000400
-00000200
-00000100
-00000080
-00000040
-00000020
-00000010
-00000008
-00000004
-00000002
-bfffffff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output
deleted file mode 100644
index 848bc88e3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output
+++ /dev/null
@@ -1,584 +0,0 @@
-ffedffff
-80100000
-00000000
-00000000
-00000000
-91999998
-04000040
-fdff7fff
-feff4afc
-00800010
-ffbbffff
-ffffffff
-ffffffff
-fffbffff
-00020007
-fffefffd
-00048000
-ffffbffd
-ffffdffa
-04001000
-fffff7fd
-fffffbfd
-fffffdfc
-ffff7eff
-40000080
-08000040
-ffffffd8
-ffffffec
-fffffff7
-00000001
-aaaaaaa8
-fffffffe
-2aaaaaaa
-dfdfffff
-1000b503
-fdfffffd
-01000005
-00800020
-00400002
-55755555
-3ff7ffff
-ffedffff
-ffffcafb
-00004005
-ffffdbff
-01001000
-fffff7f6
-fefffbff
-fbfffdff
-effffeff
-fffdff7f
-ffffffdf
-ccccccc4
-dffffffb
-ffff4afe
-00400001
-80000009
-80000000
-08000007
-02000004
-33b33333
-fdbfffff
-00080100
-33373333
-fffeffff
-ffffcafc
-00004020
-ffffdff6
-33332333
-33333b34
-00000a00
-00000100
-00020080
-aaaaaaeb
-ffffffcf
-fffffdef
-01000008
-08000004
-00400001
-7fff4afd
-afffffff
-dfffffdf
-10020000
-04000000
-fdfff7ff
-0080b503
-00100003
-66676667
-ffffafff
-55554555
-08000200
-00000086
-fffffbbf
-ffffffeb
-ffffffe7
-00000000
-fffffff8
-6666d362
-33338631
-0000b503
-aaaa1fae
-5555e053
-0000b501
-00000006
-0000b505
-6666d360
-33338637
-5555e051
-0000b507
-00000001
-fffffff9
-6666d363
-33338636
-0000b500
-aaaa1faf
-5555e050
-0000b506
-fffffff8
-00000000
-99992c9a
-cccc79c9
-ffff4afb
-5555e056
-aaaa1fab
-ffff4af9
-fffffffe
-ffff4afd
-99992c98
-cccc79cf
-aaaa1fa9
-ffff4aff
-fffffff9
-00000001
-99992c9b
-cccc79ce
-ffff4af8
-5555e057
-aaaa1fa8
-ffff4afe
-6666d362
-99992c9a
-00000000
-55555553
-66666661
-cccccccc
-33333331
-66666663
-6666d364
-66666667
-00000002
-55555555
-33333333
-66666665
-6666d363
-99992c9b
-00000001
-55555554
-66666662
-cccccccd
-33333332
-66666664
-33338631
-cccc79c9
-55555553
-00000000
-33333332
-9999999f
-66666662
-33333330
-33338637
-33333334
-55555551
-00000006
-66666660
-33333336
-33338630
-cccc79c8
-55555552
-00000007
-33333331
-9999999e
-66666661
-33333337
-0000b503
-ffff4afb
-66666661
-33333332
-00000000
-aaaaaaad
-55555550
-00000002
-0000b505
-00000006
-66666663
-33333334
-55555552
-00000004
-0000b502
-ffff4afa
-66666660
-33333335
-00000003
-aaaaaaac
-55555553
-00000005
-aaaa1fae
-5555e056
-cccccccc
-9999999f
-aaaaaaad
-00000000
-fffffffd
-aaaaaaaf
-aaaa1fa8
-aaaaaaab
-ccccccce
-99999999
-ffffffff
-aaaaaaa9
-aaaa1faf
-5555e057
-cccccccd
-99999998
-aaaaaaae
-00000001
-fffffffe
-aaaaaaa8
-5555e053
-aaaa1fab
-33333331
-66666662
-55555550
-fffffffd
-00000000
-55555552
-5555e055
-55555556
-33333333
-66666664
-00000002
-55555554
-5555e052
-aaaa1faa
-33333330
-66666665
-55555553
-fffffffc
-00000003
-55555555
-0000b501
-ffff4af9
-66666663
-33333330
-00000002
-aaaaaaaf
-55555552
-00000000
-0000b507
-00000004
-66666661
-33333336
-55555550
-00000006
-0000b500
-ffff4af8
-66666662
-33333337
-00000001
-aaaaaaae
-55555551
-00000007
-00000006
-fffffffe
-6666d364
-33338637
-0000b505
-aaaa1fa8
-5555e055
-0000b507
-00000000
-0000b503
-6666d366
-33338631
-5555e057
-0000b501
-00000007
-ffffffff
-6666d365
-33338630
-0000b506
-aaaa1fa9
-5555e056
-0000b500
-0000b505
-ffff4afd
-66666667
-33333334
-00000006
-aaaaaaab
-55555556
-00000004
-0000b503
-00000000
-66666665
-33333332
-55555554
-00000002
-0000b504
-ffff4afc
-66666666
-33333333
-00000005
-aaaaaaaa
-55555555
-00000003
-6666d360
-99992c98
-00000002
-55555551
-66666663
-ccccccce
-33333333
-66666661
-6666d366
-66666665
-33333333
-55555556
-00000001
-66666667
-33333331
-33338637
-cccc79cf
-55555555
-00000000
-33333336
-99999999
-66666666
-33333330
-0000b500
-ffff4af8
-66666662
-33333331
-00000003
-aaaaaaae
-55555553
-00000001
-0000b506
-00000005
-66666660
-33333337
-55555551
-00000007
-0000b501
-ffff4af9
-66666663
-33333336
-00000000
-aaaaaaaf
-55555550
-00000006
-aaaa1faf
-5555e057
-cccccccd
-9999999e
-aaaaaaac
-00000001
-fffffffc
-aaaaaaae
-aaaa1fa9
-aaaaaaaa
-cccccccf
-99999998
-fffffffe
-aaaaaaa8
-aaaa1fae
-5555e056
-cccccccc
-99999999
-aaaaaaaf
-00000000
-ffffffff
-aaaaaaa9
-5555e050
-aaaa1fa8
-33333332
-66666661
-55555553
-fffffffe
-00000003
-55555551
-5555e056
-55555555
-33333330
-66666667
-00000001
-55555557
-5555e051
-aaaa1fa9
-33333333
-66666666
-55555550
-ffffffff
-00000000
-55555556
-0000b506
-ffff4afe
-66666664
-33333337
-00000005
-aaaaaaa8
-55555555
-00000007
-0000b500
-00000003
-66666666
-33333331
-55555557
-00000001
-0000b507
-ffff4aff
-66666665
-33333330
-00000006
-aaaaaaa9
-55555556
-00000000
-00000000
-55555557
-33333331
-66666667
-6666d361
-99992c99
-00000003
-55555556
-66666660
-cccccccf
-33333330
-66666666
-33338637
-cccc79cf
-55555555
-00000006
-33333334
-99999999
-66666664
-33333336
-33338631
-33333332
-55555557
-00000000
-66666666
-33333330
-33338636
-cccc79ce
-55555554
-00000001
-33333337
-99999998
-66666667
-33333331
-5555e051
-aaaa1fa9
-33333333
-66666660
-55555552
-ffffffff
-00000002
-55555550
-5555e057
-55555554
-33333331
-66666666
-00000000
-55555556
-5555e050
-aaaa1fa8
-33333332
-66666667
-55555551
-fffffffe
-00000001
-55555557
-0000b507
-ffff4aff
-66666665
-33333336
-00000004
-aaaaaaa9
-55555554
-00000006
-0000b501
-00000002
-66666667
-33333330
-55555556
-00000000
-0000b506
-ffff4afe
-66666664
-33333331
-00000007
-aaaaaaa8
-55555557
-00000001
-00000001
-fffffff9
-6666d363
-33338630
-0000b502
-aaaa1faf
-5555e052
-0000b500
-00000007
-0000b504
-6666d361
-33338636
-5555e050
-0000b506
-00000000
-fffffff8
-6666d362
-33338637
-0000b501
-aaaa1fae
-5555e051
-0000b507
-fffffff9
-00000001
-99992c9b
-cccc79c8
-ffff4afa
-5555e057
-aaaa1faa
-ffff4af8
-ffffffff
-ffff4afc
-99992c99
-cccc79ce
-aaaa1fa8
-ffff4afe
-fffffff8
-00000000
-99992c9a
-cccc79cf
-ffff4af9
-5555e056
-aaaa1fa9
-ffff4aff
-6666d363
-99992c9b
-00000001
-55555552
-66666660
-cccccccd
-33333330
-66666662
-6666d365
-66666666
-00000003
-55555554
-33333332
-66666664
-6666d362
-99992c9a
-00000000
-55555555
-66666663
-cccccccc
-33333333
-66666665
-33338636
-cccc79ce
-55555554
-00000007
-33333335
-99999998
-66666665
-33333337
-33338630
-bffffbff
-dfffdfff
-effffffe
-00050000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output
deleted file mode 100644
index a17012ecf..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output
+++ /dev/null
@@ -1,560 +0,0 @@
-000207ff
-80000555
-40000100
-dffffffd
-effffff9
-0800002b
-fbffffef
-fdfffccc
-fefffffa
-00800040
-ffbffff8
-00200009
-ffeff99a
-00080003
-fffbffd1
-00000200
-00000000
-00004000
-00002003
-ffffefd1
-fffff2ab
-fffffbf9
-00000205
-00000000
-00000480
-ffffffbe
-ffffffdc
-00000012
-fffffaa2
-fffffaaf
-fffffaab
-ffffffd2
-66666199
-00001200
-00020080
-00100020
-00000011
-00100008
-00002004
-fffbfffe
-7ffffff8
-40000040
-20000001
-10000006
-080003ff
-04000005
-fdffffd3
-01000003
-0080002e
-ffbffffd
-ffdfffd4
-00100554
-fff7fdff
-fffdfffe
-00010003
-000087ff
-ffffbfbf
-00002007
-00001004
-00000c00
-00000267
-00000204
-fffffef8
-ffffff7e
-00000040
-00000020
-00000015
-0000000b
-ffffffd7
-00000556
-ffffffee
-3ffffeff
-aaaaaa2a
-00000021
-fffffff1
-0000b52b
-ffff4ad1
-0000b362
-0000b631
-0000b503
-ffff4fae
-0000b053
-0000b501
-0000b529
-0000b505
-0000b360
-0000b637
-0000b051
-0000b507
-0000b528
-ffff4ad6
-0000b363
-0000b636
-0000b500
-ffff4faf
-0000b050
-0000b506
-ffff4ad3
-0000b529
-ffff4c9a
-ffff49c9
-ffff4afb
-0000b056
-ffff4fab
-ffff4af9
-ffff4ad1
-ffff4afd
-ffff4c98
-ffff49cf
-ffff4fa9
-ffff4aff
-ffff4ad0
-0000b52e
-ffff4c9b
-ffff49ce
-ffff4af8
-0000b057
-ffff4fa8
-ffff4afe
-66666649
-999999b3
-66666000
-66666553
-66666661
-99999ccc
-66666331
-66666663
-6666664b
-66666667
-66666002
-66666555
-66666333
-66666665
-6666664a
-999999b4
-66666001
-66666554
-66666662
-99999ccd
-66666332
-66666664
-3333331a
-cccccce0
-33333553
-33333000
-33333332
-ccccc99f
-33333662
-33333330
-33333318
-33333334
-33333551
-33333006
-33333660
-33333336
-33333319
-cccccce7
-33333552
-33333007
-33333331
-ccccc99e
-33333661
-33333337
-00000028
-ffffffd2
-00000661
-00000332
-00000000
-fffffaad
-00000550
-00000002
-0000002a
-00000006
-00000663
-00000334
-00000552
-00000004
-0000002b
-ffffffd5
-00000660
-00000335
-00000003
-fffffaac
-00000553
-00000005
-aaaaaa85
-5555557f
-aaaaaccc
-aaaaa99f
-aaaaaaad
-55555000
-aaaaaffd
-aaaaaaaf
-aaaaaa87
-aaaaaaab
-aaaaacce
-aaaaa999
-aaaaafff
-aaaaaaa9
-aaaaaa86
-55555578
-aaaaaccd
-aaaaa998
-aaaaaaae
-55555001
-aaaaaffe
-aaaaaaa8
-55555578
-aaaaaa82
-55555331
-55555662
-55555550
-aaaaaffd
-55555000
-55555552
-5555557a
-55555556
-55555333
-55555664
-55555002
-55555554
-5555557b
-aaaaaa85
-55555330
-55555665
-55555553
-aaaaaffc
-55555003
-55555555
-0000002a
-ffffffd0
-00000663
-00000330
-00000002
-fffffaaf
-00000552
-00000000
-00000028
-00000004
-00000661
-00000336
-00000550
-00000006
-00000029
-00000662
-00000337
-00000001
-fffffaae
-00000551
-00000007
-0000b52d
-ffff4ad7
-0000b364
-0000b637
-0000b505
-ffff4fa8
-0000b055
-0000b507
-0000b52f
-0000b503
-0000b366
-0000b631
-0000b057
-0000b501
-0000b52e
-ffff4ad0
-0000b365
-0000b630
-0000b506
-ffff4fa9
-0000b056
-0000b500
-0000002e
-ffffffd4
-00000667
-00000334
-00000006
-fffffaab
-00000556
-00000004
-0000002c
-00000000
-00000665
-00000332
-00000554
-00000002
-0000002d
-ffffffd3
-00000666
-00000333
-00000005
-fffffaaa
-00000555
-00000003
-6666664b
-999999b1
-66666002
-66666551
-66666663
-99999cce
-66666333
-66666661
-66666649
-55555001
-aaaaaffc
-aaaaaaae
-aaaaaa86
-aaaaaaaa
-aaaaaccf
-aaaaa998
-aaaaaffe
-aaaaaaa8
-aaaaaa87
-55555579
-aaaaaccc
-aaaaa999
-aaaaaaaf
-55555000
-aaaaafff
-aaaaaaa9
-5555557b
-aaaaaa81
-55555332
-55555661
-55555553
-aaaaaffe
-55555003
-55555551
-55555579
-55555555
-55555330
-55555667
-55555001
-55555557
-55555578
-aaaaaa86
-55555333
-55555666
-55555550
-aaaaafff
-55555000
-55555556
-0000002d
-ffffffd7
-00000664
-00000337
-00000005
-fffffaa8
-00000555
-00000007
-0000002f
-00000003
-00000666
-00000331
-00000557
-00000001
-0000002e
-ffffffd0
-00000665
-00000330
-00000006
-fffffaa9
-00000556
-00000000
-66666665
-66666000
-66666557
-66666331
-66666667
-66666648
-999999b6
-66666003
-66666556
-66666660
-99999ccf
-66666330
-66666666
-3333331c
-cccccce6
-33333555
-33333006
-33333334
-ccccc999
-33333664
-33333336
-3333331e
-33333332
-33333557
-33333000
-33333666
-33333330
-3333331f
-cccccce1
-33333554
-33333001
-33333337
-ccccc998
-33333667
-33333331
-5555557a
-aaaaaa80
-55555333
-55555660
-55555552
-aaaaafff
-55555002
-55555550
-55555578
-55555554
-55555331
-55555666
-55555000
-55555556
-55555579
-aaaaaa87
-55555332
-55555667
-55555551
-aaaaaffe
-55555001
-55555557
-0000002c
-ffffffd6
-00000665
-00000336
-00000004
-fffffaa9
-00000554
-00000006
-0000002e
-00000002
-00000667
-00000330
-00000000
-0000002f
-ffffffd1
-00000664
-00000331
-00000007
-fffffaa8
-00000557
-00000001
-0000b52a
-ffff4ad0
-0000b363
-0000b630
-0000b502
-ffff4faf
-0000b052
-0000b500
-0000b528
-0000b504
-0000b361
-0000b636
-0000b050
-0000b506
-0000b529
-ffff4ad7
-0000b362
-0000b637
-0000b501
-ffff4fae
-0000b051
-0000b507
-ffff4ad2
-0000b528
-ffff4c9b
-ffff49c8
-ffff4afa
-0000b057
-ffff4faa
-ffff4af8
-ffff4ad0
-ffff4afc
-ffff4c99
-ffff49ce
-ffff4fa8
-ffff4afe
-ffff4ad1
-0000b52f
-ffff4c9a
-ffff49cf
-ffff4af9
-0000b056
-ffff4fa9
-ffff4aff
-66666648
-999999b2
-66666001
-66666552
-66666660
-99999ccd
-66666330
-66666662
-6666664a
-66666666
-66666003
-66666554
-66666332
-66666664
-6666664b
-999999b5
-66666000
-66666555
-66666663
-99999ccc
-66666333
-66666665
-3333331d
-cccccce7
-33333554
-33333007
-33333335
-ccccc998
-33333665
-33333337
-3333331f
-33333333
-33333556
-33333001
-33333667
-33333331
-3333331e
-cccccce0
-33333555
-33333000
-33333336
-ccccc999
-33333666
-33333330
-0000002b
-ffffffd1
-00000662
-00000331
-00000003
-fffffaae
-00000553
-00000001
-00000029
-00000005
-00000660
-00000337
-00000551
-00000007
-00000028
-ffffffd6
-00000663
-00000336
-00000000
-fffffaaf
-00000550
-00000006
-aaaaaa84
-5555557e
-aaaaaccd
-aaaaa99e
-aaaaaaac
-fffefdff
-ffff7fff
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output
deleted file mode 100644
index f9c1b5659..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output
+++ /dev/null
@@ -1,12 +0,0 @@
-00000000
-00000001
-ffffffff
-00000001
-00000002
-00000000
-ffffffff
-00000000
-fffffffe
-b6944260
-83edeb47
-0c939c34
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output
deleted file mode 100644
index 6e9ae61d7..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output
+++ /dev/null
@@ -1,12 +0,0 @@
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000001
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output
deleted file mode 100644
index 993b67cd3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output
+++ /dev/null
@@ -1,12 +0,0 @@
-00000000
-00000001
-00000001
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000001
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output
deleted file mode 100644
index d35fb3fdb..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output
+++ /dev/null
@@ -1,12 +0,0 @@
-00000000
-ffffffff
-00000001
-00000001
-00000000
-00000002
-ffffffff
-fffffffe
-00000000
-ebb7926c
-e2aa20ca
-63a59ba8
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output
deleted file mode 100644
index 2448d94c1..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output
+++ /dev/null
@@ -1,12 +0,0 @@
-00000000
-00000001
-ffffffff
-00000001
-00000000
-fffffffe
-ffffffff
-fffffffe
-00000000
-674f4c2c
-d1bb1e6e
-3395fef6

From cea89f27cf6ae8535e70b7fa470480af48161e07 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 07:25:04 -0800
Subject: [PATCH 39/84] Removed unused WALLY test references

---
 .../I/references/WALLY-ADD.reference_output   | 24 -------------------
 .../I/references/WALLY-SLT.reference_output   | 24 -------------------
 .../I/references/WALLY-SLTU.reference_output  | 24 -------------------
 .../I/references/WALLY-SUB.reference_output   | 24 -------------------
 .../I/references/WALLY-XOR.reference_output   | 24 -------------------
 5 files changed, 120 deletions(-)
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output
 delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output
deleted file mode 100644
index 7e1ab4344..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output
+++ /dev/null
@@ -1,24 +0,0 @@
-00000000
-00000000
-00000001
-00000000
-ffffffff
-ffffffff
-00000001
-00000000
-00000002
-00000000
-00000000
-00000000
-ffffffff
-ffffffff
-00000000
-00000000
-fffffffe
-ffffffff
-393cb5d1
-72ca6f49
-7b12609b
-245889d8
-7f42ac28
-af17a2d3
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output
deleted file mode 100644
index 5958e1ed6..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output
+++ /dev/null
@@ -1,24 +0,0 @@
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output
deleted file mode 100644
index 476470e4a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output
+++ /dev/null
@@ -1,24 +0,0 @@
-00000000
-00000000
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000001
-00000000
-00000000
-00000000
-00000001
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output
deleted file mode 100644
index cc7461347..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output
+++ /dev/null
@@ -1,24 +0,0 @@
-00000000
-00000000
-ffffffff
-ffffffff
-00000001
-00000000
-00000001
-00000000
-00000000
-00000000
-00000002
-00000000
-ffffffff
-ffffffff
-fffffffe
-ffffffff
-00000000
-00000000
-0f7dc13a
-f51130ed
-bb2485d0
-9633d6e4
-4557352f
-60fe4e94
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output
deleted file mode 100644
index 477289586..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output
+++ /dev/null
@@ -1,24 +0,0 @@
-00000000
-00000000
-00000001
-00000000
-ffffffff
-ffffffff
-00000001
-00000000
-00000000
-00000000
-fffffffe
-ffffffff
-ffffffff
-ffffffff
-fffffffe
-ffffffff
-00000000
-00000000
-e6f91511
-a770a807
-87ea008b
-3afeadc9
-3e7f1ce8
-a43d2571

From d8f0e3dd709c81b8cc9695943e76e83e1f9e0c73 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 07:25:40 -0800
Subject: [PATCH 40/84] Modified testgen to not produce reference outputs

---
 tests/testgen/testgen.py | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/tests/testgen/testgen.py b/tests/testgen/testgen.py
index c1526356b..02d16a319 100755
--- a/tests/testgen/testgen.py
+++ b/tests/testgen/testgen.py
@@ -76,11 +76,6 @@ def writeVector(a, b, storecmd, xlen):
   lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
 #  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
   f.write(lines)
-  if (xlen == 32):
-    line = formatrefstr.format(expected)+"\n"
-  else:
-    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
-  r.write(line)
   testnum = testnum+1
 
 ##################################
@@ -114,12 +109,10 @@ for xlen in xlens:
     pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
     basename = "WALLY-" + test 
     fname = pathname + "src/" + basename + ".S"
-    refname = pathname + "references/" + basename + ".reference_output"
     testnum = 0
 
     # print custom header part
     f = open(fname, "w")
-    r = open(refname, "w")
     line = "///////////////////////////////////////////\n"
     f.write(line)
     lines="// "+fname+ "\n// " + author + "\n"
@@ -154,7 +147,6 @@ for xlen in xlens:
 #    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
     f.write(lines)
     f.close()
-    r.close()
 
 
 

From 6c86c0389c16eede5f474d15f2cfd0677b003663 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 27 Jan 2023 11:34:45 -0600
Subject: [PATCH 41/84] Very hacky. But I think gshare is now correct with
 respect to repair on instruction class miss prediction.

---
 pipelined/regression/wave.do                  | 30 +++++++++++++++++--
 pipelined/src/ifu/brpred/bpred.sv             |  2 +-
 pipelined/src/ifu/brpred/speculativegshare.sv | 19 ++++++++----
 3 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index 1e34435a5..bfa161dad 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -588,8 +588,34 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
 add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
+add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
+add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
+add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -605,4 +631,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {48955732 ns} {48955990 ns}
+WaveRestoreZoom {2195 ns} {2479 ns}
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 6af314646..3fd021574 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 0
+`define INSTR_CLASS_PRED 1
 
 module bpred (
    input logic              clk, reset,
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index b72aacb44..691693af6 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -51,7 +51,8 @@ module speculativegshare
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
-  logic [k-1:0]            GHRF;
+  logic [k-1:0]            GHRF, OldGHRF;
+  logic 				   OldGHRExtraF;
   logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
   logic [k-1:0]            GHRNextF;
   logic [k:-1] 			   GHRNextD, OldGHRD;
@@ -105,17 +106,23 @@ module speculativegshare
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
 
   // GHR pipeline
-  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
+  assign GHRNextF = FlushD ?  (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) :
                     BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
                     GHRF;
 
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
+  flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
+  assign GHRF = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
+  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit 
+  				OldGHRF[k:0];
   
   assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
+
   flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
-  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
-				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
-				OldGHRD[k:0];
+  //assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
+  //				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
+  //				OldGHRD[k:0];
+  assign GHRD = OldGHRD[k:0];
 
   assign GHRNextE = FlushE ? GHRNextM : GHRD;
   flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);

From 44c710202693919499627b8d947cff4a05cb8ba5 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 09:54:50 -0800
Subject: [PATCH 42/84] Renamed ram2p1rw1be to match modeule name

---
 pipelined/src/generic/mem/{ram2p1rwbe.sv => ram2p1r1wbe.sv} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename pipelined/src/generic/mem/{ram2p1rwbe.sv => ram2p1r1wbe.sv} (100%)

diff --git a/pipelined/src/generic/mem/ram2p1rwbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram2p1rwbe.sv
rename to pipelined/src/generic/mem/ram2p1r1wbe.sv

From cf49c7ddc12f7862643707bda3cc0cc33d4c13f6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 27 Jan 2023 13:13:55 -0600
Subject: [PATCH 43/84] Found issue with branch predictor.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 691693af6..00a49ce24 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -113,8 +113,8 @@ module speculativegshare
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
   flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
   assign GHRF = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
-  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit 
-  				OldGHRF[k:0];
+  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF} : // shift left **** missing bit 
+  				OldGHRF[k-1:0];
   
   assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
 

From 121fbd9646bd0797b3f0fdf12cac929390d0f4a7 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 27 Jan 2023 15:28:31 -0600
Subject: [PATCH 44/84] Removed pessimistic x propagation issue for wally32priv
 test in the branch predictor.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 00a49ce24..f1810f627 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -106,9 +106,21 @@ module speculativegshare
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
 
   // GHR pipeline
+  // this version fails the regression test do to pessimistic x propagation.
+/* -----\/----- EXCLUDED -----\/-----
   assign GHRNextF = FlushD ?  (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) :
                     BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
                     GHRF;
+ -----/\----- EXCLUDED -----/\----- */
+
+  always_comb begin
+	if(FlushD) begin
+	  if(BranchInstrE) GHRNextF =  GHRNextD[k:1];
+	  else             GHRNextF = GHRNextD[k-1:0];
+	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
+	else GHRNextF = GHRF;
+  end
+	
 
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
   flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);

From 717cb4e6c50830f961e2d00ee34a1ac6d67c9843 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 14:27:04 -0800
Subject: [PATCH 45/84] Removed int/integer from parameters)

---
 pipelined/src/ebu/ahbcacheinterface.sv        |  8 ++---
 pipelined/src/ebu/buscachefsm.sv              |  4 +--
 pipelined/src/ifu/bpred/RAsPredictor.sv       | 24 +++++++-------
 pipelined/src/ifu/bpred/btb.sv                | 32 +++++++++----------
 pipelined/src/ifu/bpred/foldedgshare.sv       | 27 +++++++---------
 pipelined/src/ifu/bpred/globalhistory.sv      | 26 +++++++--------
 pipelined/src/ifu/bpred/gshare.sv             | 24 +++++++-------
 .../src/ifu/bpred/localHistoryPredictor.sv    | 29 ++++++++---------
 pipelined/src/ifu/bpred/optgshare.sv          | 26 +++++++--------
 .../src/ifu/bpred/speculativeglobalhistory.sv | 26 +++++++--------
 pipelined/src/ifu/bpred/speculativegshare.sv  | 28 ++++++++--------
 pipelined/src/ifu/bpred/twoBitPredictor.sv    | 24 +++++++-------
 12 files changed, 128 insertions(+), 150 deletions(-)

diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv
index a127e0fab..8bd1bc083 100644
--- a/pipelined/src/ebu/ahbcacheinterface.sv
+++ b/pipelined/src/ebu/ahbcacheinterface.sv
@@ -30,10 +30,10 @@
 `include "wally-config.vh"
 
 module ahbcacheinterface #(
-  parameter integer BEATSPERLINE,  // Number of AHBW words (beats) in cacheline
-  parameter integer AHBWLOGBWPL,   // Log2 of ^
-  parameter integer LINELEN,       // Number of bits in cacheline
-  parameter integer LLENPOVERAHBW  // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+  parameter BEATSPERLINE,  // Number of AHBW words (beats) in cacheline
+  parameter AHBWLOGBWPL,   // Log2 of ^
+  parameter LINELEN,       // Number of bits in cacheline
+  parameter LLENPOVERAHBW  // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
 )(
   input  logic                 HCLK, HRESETn,
   // bus interface controls
diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv
index c3be92fd8..8467f3029 100644
--- a/pipelined/src/ebu/buscachefsm.sv
+++ b/pipelined/src/ebu/buscachefsm.sv
@@ -32,8 +32,8 @@
 
 // HCLK and clk must be the same clock!
 module buscachefsm #(
-  parameter integer BeatCountThreshold,              // Largest beat index
-  parameter integer AHBWLOGBWPL                      // Log2 of BEATSPERLINE
+  parameter BeatCountThreshold,                      // Largest beat index
+  parameter AHBWLOGBWPL                              // Log2 of BEATSPERLINE
 )(
   input  logic              HCLK,
   input  logic              HRESETn,
diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv
index c71ff2966..ae5b31999 100644
--- a/pipelined/src/ifu/bpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/bpred/RAsPredictor.sv
@@ -28,19 +28,17 @@
 
 `include "wally-config.vh"
 
-module RASPredictor
-  #(parameter int StackSize = 16
-    )
-  (input logic              clk,
-   input logic 				reset,
-   input logic 				PopF,
-   output logic [`XLEN-1:0] RASPCF,
-   input logic [3:0] 		WrongPredInstrClassD,
-   input logic [3:0] 		InstrClassD,
-   input logic 				PushE,
-   input logic 				incr,
-   input logic [`XLEN-1:0] 	PCLinkE
-   );
+module RASPredictor #(parameter StackSize = 16) (
+  input  logic             clk,
+  input  logic 				     reset,
+  input  logic 				     PopF,
+  output logic [`XLEN-1:0] RASPCF,
+  input  logic [3:0] 		   WrongPredInstrClassD,
+  input  logic [3:0] 		   InstrClassD,
+  input  logic 				     PushE,
+  input  logic 				     incr,
+  input  logic [`XLEN-1:0] PCLinkE
+);
 
   // *** need to update so it either doesn't push until the memory stage
   // or need to repair flushed push.
diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv
index 5f725b83a..c228964da 100644
--- a/pipelined/src/ifu/bpred/btb.sv
+++ b/pipelined/src/ifu/bpred/btb.sv
@@ -30,23 +30,21 @@
 
 `include "wally-config.vh"
 
-module btb
-  #(parameter int Depth = 10
-    )
-  (input  logic             clk,
-   input  logic             reset,
-   input  logic             StallF, StallE,
-   input  logic [`XLEN-1:0] PCNextF,
-   output logic [`XLEN-1:0] BTBPredPCF,
-   output logic [3:0]       InstrClass,
-   output logic             Valid,
-   // update
-   input  logic             UpdateEN,
-   input  logic [`XLEN-1:0] PCE,
-   input  logic [`XLEN-1:0] IEUAdrE,
-   input  logic [3:0]       InstrClassE,
-   input  logic             UpdateInvalid
-   );
+module btb #(parameter Depth = 10) (
+  input  logic             clk,
+  input  logic             reset,
+  input  logic             StallF, StallE,
+  input  logic [`XLEN-1:0] PCNextF,
+  output logic [`XLEN-1:0] BTBPredPCF,
+  output logic [3:0]       InstrClass,
+  output logic             Valid,
+  // update
+  input  logic             UpdateEN,
+  input  logic [`XLEN-1:0] PCE,
+  input  logic [`XLEN-1:0] IEUAdrE,
+  input  logic [3:0]       InstrClassE,
+  input  logic             UpdateInvalid
+);
 
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv
index 2dfa48244..9de5d5c95 100644
--- a/pipelined/src/ifu/bpred/foldedgshare.sv
+++ b/pipelined/src/ifu/bpred/foldedgshare.sv
@@ -28,22 +28,19 @@
 
 `include "wally-config.vh"
 
-module foldedgshare
-  #(parameter int k = 16,
-	parameter int depth = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, StallW, 
-   input logic             FlushD, FlushE, FlushM, FlushW,
+module foldedgshare #(parameter k = 16, depth = 10) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW, 
+  input logic             FlushD, FlushE, FlushM, FlushW,
 //   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      DirPredictionF, 
-   output logic            DirPredictionWrongE,
-   // update
-   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
-   input logic             PCSrcE
-   );
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+  input logic             PCSrcE
+);
 
   logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
   logic                    MatchNextX, MatchXF;
diff --git a/pipelined/src/ifu/bpred/globalhistory.sv b/pipelined/src/ifu/bpred/globalhistory.sv
index 7aa86dbb9..a8493a8d4 100644
--- a/pipelined/src/ifu/bpred/globalhistory.sv
+++ b/pipelined/src/ifu/bpred/globalhistory.sv
@@ -28,20 +28,18 @@
 
 `include "wally-config.vh"
 
-module globalhistory
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM,
-   input logic             FlushD, FlushE, FlushM,
-//   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      DirPredictionF, 
-   output logic            DirPredictionWrongE,
-   // update
-   input logic [`XLEN-1:0] PCNextF, PCM,
-   input logic             BranchInstrE, BranchInstrM, PCSrcE
-   );
+module globalhistory #(parameter k = 10) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM,
+  input logic             FlushD, FlushE, FlushM,
+  //   input logic [`XLEN-1:0] LookUpPC,
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic             BranchInstrE, BranchInstrM, PCSrcE
+);
 
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
diff --git a/pipelined/src/ifu/bpred/gshare.sv b/pipelined/src/ifu/bpred/gshare.sv
index ce189d268..2fb0c6eaf 100644
--- a/pipelined/src/ifu/bpred/gshare.sv
+++ b/pipelined/src/ifu/bpred/gshare.sv
@@ -28,20 +28,18 @@
 
 `include "wally-config.vh"
 
-module gshare
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, 
-   input logic             FlushD, FlushE, FlushM,
+module gshare #(parameter k = 10) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, 
+  input logic             FlushD, FlushE, FlushM,
 //   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      DirPredictionF, 
-   output logic            DirPredictionWrongE,
-   // update
-   input logic [`XLEN-1:0] PCNextF, PCM,
-   input logic             BranchInstrE, BranchInstrM, PCSrcE
-   );
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic             BranchInstrE, BranchInstrM, PCSrcE
+);
 
   logic [k-1:0]            IndexNextF, IndexM;
   logic [1:0]              DirPredictionD, DirPredictionE;
diff --git a/pipelined/src/ifu/bpred/localHistoryPredictor.sv b/pipelined/src/ifu/bpred/localHistoryPredictor.sv
index 1709772dd..cde1fa7d3 100644
--- a/pipelined/src/ifu/bpred/localHistoryPredictor.sv
+++ b/pipelined/src/ifu/bpred/localHistoryPredictor.sv
@@ -28,23 +28,20 @@
 
 `include "wally-config.vh"
 
-module localHistoryPredictor
-  #(  parameter int m = 6, // 2^m = number of local history branches
-      parameter int k = 10 // number of past branches stored
-      )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF,  StallE,
-   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      Prediction,
-   // update
-   input logic [`XLEN-1:0] UpdatePC,
-   input logic             UpdateEN, PCSrcE, 
-   input logic [1:0]       UpdatePrediction
-  
-   );
+module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local history branches
+                                         k = 10) ( // number of past branches stored
+  input  logic             clk,
+  input  logic             reset,
+  input  logic             StallF,  StallE,
+  input  logic [`XLEN-1:0] LookUpPC,
+  output logic [1:0]       Prediction,
+  // update
+  input logic [`XLEN-1:0]  UpdatePC,
+  input logic              UpdateEN, PCSrcE, 
+  input logic [1:0]        UpdatePrediction
+);
 
-  logic [2**m-1:0]         [k-1:0]  LHRNextF;
+  logic [2**m-1:0][k-1:0]  LHRNextF;
   logic [k-1:0]            LHRF, ForwardLHRNext, LHRFNext;
   logic [m-1:0]            LookUpPCIndex, UpdatePCIndex;
   logic [1:0]              PredictionMemory;
diff --git a/pipelined/src/ifu/bpred/optgshare.sv b/pipelined/src/ifu/bpred/optgshare.sv
index 1f99cfd26..78c98c5e6 100644
--- a/pipelined/src/ifu/bpred/optgshare.sv
+++ b/pipelined/src/ifu/bpred/optgshare.sv
@@ -28,21 +28,19 @@
 
 `include "wally-config.vh"
 
-module optgshare
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, StallW, 
-   input logic             FlushD, FlushE, FlushM, FlushW,
+module optgshare #(parameter k = 10) (
+  input  logic             clk,
+  input  logic             reset,
+  input  logic             StallF, StallD, StallE, StallM, StallW, 
+  input  logic             FlushD, FlushE, FlushM, FlushW,
 //   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      DirPredictionF, 
-   output logic            DirPredictionWrongE,
-   // update
-   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
-   input logic             PCSrcE
-   );
+  output logic [1:0]       DirPredictionF, 
+  output logic             DirPredictionWrongE,
+  // update
+  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input  logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+  input  logic             PCSrcE
+);
 
   logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
   logic                    MatchNextX, MatchXF;
diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
index 094adca99..232351c86 100644
--- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
@@ -28,21 +28,19 @@
 
 `include "wally-config.vh"
 
-module speculativeglobalhistory
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, StallW, 
-   input logic             FlushD, FlushE, FlushM, FlushW,
+module speculativeglobalhistory #(parameter k = 10) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW, 
+  input logic             FlushD, FlushE, FlushM, FlushW,
 //   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      DirPredictionF, 
-   output logic            DirPredictionWrongE,
-   // update
-   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
-   input logic             PCSrcE
-   );
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+  input logic             PCSrcE
+);
 
   logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
   logic                    MatchNextX, MatchXF;
diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv
index 05753c76d..98b590bed 100644
--- a/pipelined/src/ifu/bpred/speculativegshare.sv
+++ b/pipelined/src/ifu/bpred/speculativegshare.sv
@@ -28,22 +28,20 @@
 
 `include "wally-config.vh"
 
-module speculativegshare
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM, StallW, 
-   input logic             FlushD, FlushE, FlushM, FlushW,
+module speculativegshare #(parameter k = 10) (
+  input  logic             clk,
+  input  logic             reset,
+  input  logic             StallF, StallD, StallE, StallM, StallW, 
+  input  logic             FlushD, FlushE, FlushM, FlushW,
 //   input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0]      DirPredictionF, 
-   output logic            DirPredictionWrongE,
-   // update
-   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
-   input logic [3:0]       WrongPredInstrClassD, 
-   input logic             PCSrcE
-   );
+  output logic [1:0]       DirPredictionF, 
+  output logic             DirPredictionWrongE,
+  // update
+  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input  logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
+  input  logic [3:0]       WrongPredInstrClassD, 
+  input  logic             PCSrcE
+);
 
   logic                    MatchF, MatchD, MatchE, MatchM;
   logic                    MatchNextX, MatchXF;
diff --git a/pipelined/src/ifu/bpred/twoBitPredictor.sv b/pipelined/src/ifu/bpred/twoBitPredictor.sv
index 5a04a5fcf..4a7be674d 100644
--- a/pipelined/src/ifu/bpred/twoBitPredictor.sv
+++ b/pipelined/src/ifu/bpred/twoBitPredictor.sv
@@ -28,19 +28,17 @@
 
 `include "wally-config.vh"
 
-module twoBitPredictor
-  #(parameter int k = 10
-    )
-  (input logic             clk,
-   input logic             reset,
-   input logic             StallF, StallD, StallE, StallM,
-   input logic             FlushD, FlushE, FlushM,
-   input logic [`XLEN-1:0] PCNextF, PCM,
-   output logic [1:0]      DirPredictionF,
-   output logic            DirPredictionWrongE,
-   input logic             BranchInstrE, BranchInstrM,
-   input logic             PCSrcE
-   );
+module twoBitPredictor #(parameter k = 10) (
+  input  logic             clk,
+  input  logic             reset,
+  input  logic             StallF, StallD, StallE, StallM,
+  input  logic             FlushD, FlushE, FlushM,
+  input  logic [`XLEN-1:0] PCNextF, PCM,
+  output logic [1:0]       DirPredictionF,
+  output logic             DirPredictionWrongE,
+  input  logic             BranchInstrE, BranchInstrM,
+  input  logic             PCSrcE
+);
 
   logic [k-1:0]            IndexNextF, IndexM;
   logic [1:0]              PredictionMemory;

From a99fc74976ad605ee57875645debfbe2c8cc55f7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 14:40:06 -0800
Subject: [PATCH 46/84] Removed integer from localparams

---
 pipelined/src/cache/cacheLRU.sv         |  6 ++---
 pipelined/src/cache/cacheway.sv         | 16 ++++++-------
 pipelined/src/ebu/ahbcacheinterface.sv  | 12 +++++-----
 pipelined/src/ifu/bpred/foldedgshare.sv |  4 ++--
 pipelined/src/ifu/ifu.sv                |  8 +++----
 pipelined/src/ifu/spill.sv              |  8 +++----
 pipelined/src/lsu/lsu.sv                | 16 ++++++-------
 pipelined/testbench/sdc/sd_top_tb.sv    |  2 +-
 pipelined/testbench/testbench.sv        | 30 ++++++++++++-------------
 9 files changed, 49 insertions(+), 53 deletions(-)

diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv
index be42036e0..2e3057f0c 100644
--- a/pipelined/src/cache/cacheLRU.sv
+++ b/pipelined/src/cache/cacheLRU.sv
@@ -81,8 +81,8 @@ module cacheLRU
   // expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
   for(row = 0; row < LOGNUMWAYS; row++) begin
     localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
-    localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
-    localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
+    localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
+    localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
     assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
   end
 
@@ -109,8 +109,6 @@ module cacheLRU
   for(s = NUMWAYS/2-1; s >= 0; s--) begin
     localparam int0 = (NUMWAYS/2-1-s)*2;
     localparam int1 = int0 + 1;
-	//localparam int0 = s*2;
-	//localparam int1 = int0 + 1;	
     assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
   end
 
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index d3e996729..671bbcaff 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -55,11 +55,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   output logic                        DirtyWay,       // This way is dirty
   output logic [TAGLEN-1:0]           TagWay);        // THis way's tag if valid
 
-  localparam integer                  WORDSPERLINE = LINELEN/`XLEN;
-  localparam integer                  BYTESPERLINE = LINELEN/8;
+  localparam                          WORDSPERLINE = LINELEN/`XLEN;
+  localparam                          BYTESPERLINE = LINELEN/8;
   localparam                          LOGWPL = $clog2(WORDSPERLINE);
   localparam                          LOGXLENBYTES = $clog2(`XLEN/8);
-  localparam integer                  BYTESPERWORD = `XLEN/8;
+  localparam                          BYTESPERWORD = `XLEN/8;
 
   logic [NUMLINES-1:0]                ValidBits;
   logic [NUMLINES-1:0]                DirtyBits;
@@ -128,12 +128,12 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   // Data Array
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  genvar                             words;
+  genvar               words;
 
-  localparam integer           SRAMLEN = 128;
-  localparam integer           NUMSRAM = LINELEN/SRAMLEN;
-  localparam integer           SRAMLENINBYTES = SRAMLEN/8;
-  localparam integer           LOGNUMSRAM = $clog2(NUMSRAM);
+  localparam           SRAMLEN = 128;
+  localparam           NUMSRAM = LINELEN/SRAMLEN;
+  localparam           SRAMLENINBYTES = SRAMLEN/8;
+  localparam           LOGNUMSRAM = $clog2(NUMSRAM);
   
   for(words = 0; words < NUMSRAM; words++) begin: word
     ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr),
diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv
index 8bd1bc083..7278f4f93 100644
--- a/pipelined/src/ebu/ahbcacheinterface.sv
+++ b/pipelined/src/ebu/ahbcacheinterface.sv
@@ -72,12 +72,12 @@ module ahbcacheinterface #(
   output logic                BusCommitted);           // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
   
 
-  localparam integer           BeatCountThreshold = BEATSPERLINE - 1;  // Largest beat index
-  logic [`PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
-  logic [AHBWLOGBWPL-1:0]           BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
-  logic                        CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
-  logic [`AHBW/8-1:0] 		   BusByteMaskM;                           // Byte enables within a word.  For cache request all 1s
-  logic [`AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
+  localparam                  BeatCountThreshold = BEATSPERLINE - 1;  // Largest beat index
+  logic [`PA_BITS-1:0]        LocalHADDR;                             // Address after selecting between cached and uncached operation
+  logic [AHBWLOGBWPL-1:0]     BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
+  logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
+  logic [`AHBW/8-1:0] 		    BusByteMaskM;                           // Byte enables within a word.  For cache request all 1s
+  logic [`AHBW-1:0]           PreHWDATA;                              // AHB Address phase write data
 
   genvar                       index;
 
diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv
index 9de5d5c95..85b7db383 100644
--- a/pipelined/src/ifu/bpred/foldedgshare.sv
+++ b/pipelined/src/ifu/bpred/foldedgshare.sv
@@ -54,13 +54,13 @@ module foldedgshare #(parameter k = 16, depth = 10) (
   logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE, IndexM, IndexW;
-  logic [depth-1:0] 	   FinalIndexNextF, FinalIndexW;
+  logic [depth-1:0] 	     FinalIndexNextF, FinalIndexW;
   
   logic                    PCSrcM, PCSrcW;
   logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
-  localparam int 		   delta = 2 * depth - k;
+  localparam        		   delta = 2 * depth - k;
   
   assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
   assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 476f666ff..0ff6dc3f9 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -210,11 +210,11 @@ module ifu (
   end
   if (`BUS) begin : bus
     // **** must fix words per line vs beats per line as in lsu.
-    localparam integer   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
-    localparam integer   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
+    localparam   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
+    localparam   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
     if(`ICACHE) begin : icache
-      localparam integer   LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
-      localparam integer   LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+      localparam           LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
+      localparam           LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
       logic [LINELEN-1:0]  FetchBuffer;
       logic [`PA_BITS-1:0] ICacheBusAdr;
       logic                ICacheBusAck;
diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv
index 9df9fca18..aa93c4397 100644
--- a/pipelined/src/ifu/spill.sv
+++ b/pipelined/src/ifu/spill.sv
@@ -50,15 +50,15 @@ module spill #(
   output logic 			   CompressedF);      // The fetched instruction is compressed
 
   // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
-  localparam integer   SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; 
+  typedef enum logic [1:0]     {STATE_READY, STATE_SPILL} statetype;
+  statetype            CurrState, NextState;
+  localparam           SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; 
   logic [`XLEN-1:0]    PCPlus2F;         
   logic                TakeSpillF;
   logic                SpillF;
   logic                SelSpillF;
-  logic 			   SpillSaveF;
+  logic 			         SpillSaveF;
   logic [15:0]         InstrFirstHalf;
-  typedef enum logic [1:0]     {STATE_READY, STATE_SPILL} statetype;
-   statetype CurrState, NextState;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // PC logic 
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index f89fe0da4..19f5ba960 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -238,12 +238,12 @@ module lsu (
   end
   if (`BUS) begin : bus              
     if(`DCACHE) begin : dcache
-      localparam integer   LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN;             // Number of LLEN words in cacheline
-      localparam integer   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                     // Log2 of ^
-      localparam integer   BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW;                 // Number of AHBW words (beats) in cacheline
-      localparam integer   AHBWLOGBWPL = $clog2(BEATSPERLINE);                         // Log2 of ^
-      localparam integer   LINELEN = `DCACHE_LINELENINBITS;                            // Number of bits in cacheline
-      localparam integer   LLENPOVERAHBW = `LLEN / `AHBW;                              // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+      localparam   LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN;             // Number of LLEN words in cacheline
+      localparam   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                     // Log2 of ^
+      localparam   BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW;                 // Number of AHBW words (beats) in cacheline
+      localparam   AHBWLOGBWPL = $clog2(BEATSPERLINE);                         // Log2 of ^
+      localparam   LINELEN = `DCACHE_LINELENINBITS;                            // Number of bits in cacheline
+      localparam   LLENPOVERAHBW = `LLEN / `AHBW;                              // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
 
       logic [LINELEN-1:0]  FetchBuffer;                                                // Temporary buffer to hold partially fetched cacheline
       logic [`PA_BITS-1:0] DCacheBusAdr;                                               // Cacheline address to fetch or writeback.
@@ -251,10 +251,10 @@ module lsu (
       logic                DCacheBusAck;                                               // ahbcacheinterface completed fetch or writeback
       logic                SelBusBeat;                                                 // ahbcacheinterface selects postion in cacheline with BeatCount
       logic [1:0] 		   CacheBusRW;                                                 // Cache sends request to ahbcacheinterface
-	  logic [1:0] 		   BusRW;                                                      // Uncached bus memory access
+	    logic [1:0] 		   BusRW;                                                      // Uncached bus memory access
       logic                CacheableOrFlushCacheM;                                     // Memory address is cacheable or operation is a cache flush
       logic [1:0] 		   CacheRWM;                                                   // Cache read (10), write (01), AMO (11)
-	  logic [1:0] 		   CacheAtomicM;                                               // Cache AMO
+	    logic [1:0] 		   CacheAtomicM;                                               // Cache AMO
       
       assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/pipelined/testbench/sdc/sd_top_tb.sv
index 3282c0e2a..65d9ed454 100644
--- a/pipelined/testbench/sdc/sd_top_tb.sv
+++ b/pipelined/testbench/sdc/sd_top_tb.sv
@@ -32,7 +32,7 @@
 module sd_top_tb();
 
 
-  localparam integer g_COUNT_WIDTH = 8;
+  localparam g_COUNT_WIDTH = 8;
 
   logic a_RST;
   logic i_SD_CMD;
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 5456ce8b9..fbd720109 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -205,8 +205,8 @@ logic [3:0] dummy;
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
-  localparam integer 	   MemStartAddr = 0;
-  localparam integer 	   MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
+  localparam 	   MemStartAddr = 0;
+  localparam 	   MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
 
   initial
     begin
@@ -570,25 +570,23 @@ module DCacheFlushFSM
   logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
   
 	if(`DCACHE) begin
-	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
-	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
-	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
-	  localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
-	  localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
-	  localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
-      
-//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
-	  localparam integer numwords = sramlen/`XLEN;
-      localparam integer lognumlines = $clog2(numlines);
-	  localparam integer loglinebytelen = $clog2(linebytelen);
-	  localparam integer lognumways = $clog2(numways);
-	  localparam integer tagstart = lognumlines + loglinebytelen;
+	  localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+	  localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+	  localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
+	  localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+	  localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+	  localparam numwords = sramlen/`XLEN;
+    localparam lognumlines = $clog2(numlines);
+	  localparam loglinebytelen = $clog2(linebytelen);
+	  localparam lognumways = $clog2(numways);
+	  localparam tagstart = lognumlines + loglinebytelen;
 
 
 
 	  genvar 			 index, way, cacheWord;
 	  logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-      logic [sramlen-1:0] cacheline;
+    logic [sramlen-1:0] cacheline;
 	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
 	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
 	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];

From a953954909142baadfcaf0572fe6bba75aa5bfd3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 27 Jan 2023 16:40:20 -0600
Subject: [PATCH 47/84] Clarified gshare bp.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 21 +++++++------------
 1 file changed, 7 insertions(+), 14 deletions(-)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index f1810f627..85cb3654c 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -55,7 +55,7 @@ module speculativegshare
   logic 				   OldGHRExtraF;
   logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
   logic [k-1:0]            GHRNextF;
-  logic [k:-1] 			   GHRNextD, OldGHRD;
+  logic [k:0] 			   GHRNextD;
   logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE;
@@ -107,11 +107,9 @@ module speculativegshare
 
   // GHR pipeline
   // this version fails the regression test do to pessimistic x propagation.
-/* -----\/----- EXCLUDED -----\/-----
-  assign GHRNextF = FlushD ?  (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) :
-                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
-                    GHRF;
- -----/\----- EXCLUDED -----/\----- */
+  // assign GHRNextF = FlushD ?  (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) :
+  //                  BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+  //                  GHRF;
 
   always_comb begin
 	if(FlushD) begin
@@ -121,20 +119,15 @@ module speculativegshare
 	else GHRNextF = GHRF;
   end
 	
-
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
   flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
   assign GHRF = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
-  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF} : // shift left **** missing bit 
+  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}:       // shift left
   				OldGHRF[k-1:0];
   
-  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
+  assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF};
 
-  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
-  //assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
-  //				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
-  //				OldGHRD[k:0];
-  assign GHRD = OldGHRD[k:0];
+  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
 
   assign GHRNextE = FlushE ? GHRNextM : GHRD;
   flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);

From 848ccd8b909873261c4c3af2b8940ad0246b61e8 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 15:17:17 -0800
Subject: [PATCH 48/84] Fixed license header for config files to SolderPad

---
 pipelined/config/buildroot/wally-config.vh  | 21 +++++++++++----------
 pipelined/config/fpga/wally-config.vh       | 21 +++++++++++----------
 pipelined/config/rv32e/wally-config.vh      | 21 +++++++++++----------
 pipelined/config/rv32gc/wally-config.vh     | 21 +++++++++++----------
 pipelined/config/rv32i/wally-config.vh      | 21 +++++++++++----------
 pipelined/config/rv32ic/wally-config.vh     | 21 +++++++++++----------
 pipelined/config/rv64fpquad/wally-config.vh | 21 +++++++++++----------
 pipelined/config/rv64gc/wally-config.vh     | 21 +++++++++++----------
 pipelined/config/rv64i/wally-config.vh      | 21 +++++++++++----------
 pipelined/config/shared/wally-constants.vh  | 21 +++++++++++----------
 pipelined/config/shared/wally-shared.vh     | 21 +++++++++++----------
 11 files changed, 121 insertions(+), 110 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index 56292c842..5ab833be6 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 16f7ca45d..4989b571b 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index f029e0e68..66d4049f8 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 4d346e5a6..85c207e91 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 7fb355c57..b6330579f 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index 311ce8ab2..085bbad3b 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index 2df9867fa..aab3df73e 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index 29148944f..606c95eb8 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index c7304c724..203ee4552 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -11,18 +11,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // include shared configuration
 `include "wally-shared.vh"
diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh
index 0acc12b86..0999fc207 100644
--- a/pipelined/config/shared/wally-constants.vh
+++ b/pipelined/config/shared/wally-constants.vh
@@ -15,18 +15,19 @@
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // constants defining different privilege modes
 // defined in Table 1.1 of the privileged spec
diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index 2fcb3af7a..4e43c7217 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -9,18 +9,19 @@
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 // division constants
 `define RADIX 32'h4

From 5547179a3c5662974252c0b0ee809fe496f48daf Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 15:23:32 -0800
Subject: [PATCH 49/84] Added missing PLIC_GPIO_ID to two config files

---
 pipelined/config/buildroot/wally-config.vh | 1 +
 pipelined/config/fpga/wally-config.vh      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index 5ab833be6..814e37761 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -127,6 +127,7 @@
 // Interrupt configuration
 `define PLIC_NUM_SRC 53
 `define PLIC_UART_ID 10
+`define PLIC_GPIO_ID 3
 
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 4989b571b..6b977fcbc 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -137,6 +137,7 @@
 // Interrupt configuration
 `define PLIC_NUM_SRC 53
 `define PLIC_UART_ID 10
+`define PLIC_GPIO_ID 3
 
 `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"

From c2ce2947f9663dd2f8357825a192a66d0241f280 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 15:47:15 -0800
Subject: [PATCH 50/84] Removed unused BMU, added CVW configuration

---
 pipelined/src/bmu/bmu.sv      |  45 -------
 pipelined/src/ieu/datapath.sv |   8 +-
 pipelined/src/ieu/ieu.sv      |   6 +-
 pipelined/src/wally/cvw.sv    | 218 ++++++++++++++++++++++++++++++++++
 4 files changed, 221 insertions(+), 56 deletions(-)
 delete mode 100644 pipelined/src/bmu/bmu.sv
 create mode 100644 pipelined/src/wally/cvw.sv

diff --git a/pipelined/src/bmu/bmu.sv b/pipelined/src/bmu/bmu.sv
deleted file mode 100644
index ba6ab0b08..000000000
--- a/pipelined/src/bmu/bmu.sv
+++ /dev/null
@@ -1,45 +0,0 @@
-///////////////////////////////////////////
-// bmu.sv
-//
-// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023
-// Modified: 
-//
-// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs
-//          Single-cycle operation in Execute stage
-// 
-// Documentation: n/a
-// See RISC-V Bit-Manipulation ISA-extensions
-//     Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module bmu(
-	input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
-  input  logic [31:0] 			InstrD,                           // instruction        
-  output logic              BMUE,                             // bit manipulation instruction  								
-	output logic [`XLEN-1:0] 	BMUResultE												// bit manipulation result
-);
-
-
-
-endmodule // mdu
-
-
diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index 9ca880836..60d43de92 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -48,7 +48,6 @@ module datapath (
   output logic [1:0]       FlagsE,                  // Comparison flags ({eq, lt})
   output logic [`XLEN-1:0] IEUAdrE,                 // Address computed by ALU
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
-  input  logic             BMUE,                    // Bit manipulation instruction
   // Memory stage signals
   input  logic             StallM, FlushM,          // Stall, flush Memory stage
   input  logic             FWriteIntM, FCvtIntW,    // FPU writes integer register file, FPU converts float to int
@@ -64,7 +63,6 @@ module datapath (
   input  logic [`XLEN-1:0] ReadDataW,               // Read data from LSU
   input  logic [`XLEN-1:0] CSRReadValW,             // CSR read result
   input  logic [`XLEN-1:0] MDUResultW,              // MDU (Multiply/divide unit) result
-  input  logic [`XLEN-1:0] BMUResultE,              // bit manipulation unit result
   input  logic [`XLEN-1:0] FIntDivResultW,          // FPU's integer divide result
    // Hazard Unit signals 
   output logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E,  // Register sources to read in Decode or Execute stage
@@ -81,7 +79,6 @@ module datapath (
   logic [`XLEN-1:0] ImmExtE;                        // Extended immediate in Execute stage 
   logic [`XLEN-1:0] SrcAE, SrcBE;                   // ALU operands
   logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
-  logic [`XLEN-1:0] IEUBResultE;                    // IEUResultE before optional bit manipulation mux
   // Memory stage signals
   logic [`XLEN-1:0] IEUResultM;                     // Result from execution stage
   logic [`XLEN-1:0] IFResultM;                      // Result from either IEU or single-cycle FPU op writing an integer register
@@ -114,10 +111,7 @@ module datapath (
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
   alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
   mux2 #(`XLEN)   altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
-  mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE);
-  if (`B_SUPPORTED)
-    mux2 #(`XLEN)   bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE);
-  else assign IEUResultE = IEUBResultE;
+  mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
 
   // Memory stage pipeline register
   flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv
index fd8a74c2b..681bd9826 100644
--- a/pipelined/src/ieu/ieu.sv
+++ b/pipelined/src/ieu/ieu.sv
@@ -43,7 +43,6 @@ module ieu (
   output logic 		          IntDivE, W64E,                   // Integer divide, RV64 W-type instruction 
   output logic [2:0] 	      Funct3E,                         // Funct3 instruction field
   output logic [`XLEN-1:0]  ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
-  input  logic              BMUE,                            // This is a bit manipulation instruction
   output logic [4:0]        RdE,                             // Destination register
   // Memory stage signals
   input  logic 		          SquashSCW,                       // Squash store conditional, from LSU
@@ -60,7 +59,6 @@ module ieu (
   input  logic [`XLEN-1:0]  FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
   input  logic [`XLEN-1:0]  CSRReadValW,                     // CSR read value, 
   input  logic [`XLEN-1:0]  MDUResultW,                      // multiply/divide unit result
-  input  logic [`XLEN-1:0]  BMUResultE,                      // bit manipulation unit result
   input  logic [`XLEN-1:0]  FCvtIntResW,                     // FPU's float to int conversion result
   input  logic              FCvtIntW,                        // FPU converts float to int
   output logic [4:0]        RdW,                             // Destination register
@@ -105,10 +103,10 @@ module ieu (
   datapath   dp(
     .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
     .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, 
-    .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
+    .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
     .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
-    .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
+    .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
   
   forward    fw(
     .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv
new file mode 100644
index 000000000..e35b22fb2
--- /dev/null
+++ b/pipelined/src/wally/cvw.sv
@@ -0,0 +1,218 @@
+//////////////////////////////////////////
+// cvw.sv
+//
+// Written: David_Harris@hmc.edu 27 January 2022
+//
+// Purpose: package with shared CORE-V-Wally global parameters
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// Usiing global `define statements isn't ideal in a large SystemVerilog system because
+// of the risk of `define name conflicts across different subsystems.
+// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
+// that is referenced by all Wally modules but not by other subsystems.
+
+// Load configuration-specific information
+`include "wally-config.vh"
+
+// Place configuration in a package
+package cvw;
+  parameter XLEN = `XLEN;
+  parameter FPGA = `FPGA;
+  parameter QEMU = `QEMU;
+  parameter DESIGN_COMPILER = `DESIGN_COMPILER;
+  parameter IEEE754 = `IEEE754;
+  parameter MISA = `MISA;
+  parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED;
+  parameter ZIFENCEI_SUPPORTED = `ZIFENCEI_SUPPORTED;
+  parameter COUNTERS = `COUNTERS;
+  parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
+  parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
+  parameter BUS = `BUS;
+  parameter DCACHE = `DCACHE;
+  parameter ICACHE = `ICACHE;
+  parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
+  parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED;
+  parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED;
+  parameter ITLB_ENTRIES = `ITLB_ENTRIES;
+  parameter DTLB_ENTRIES = `DTLB_ENTRIES;
+  parameter DCACHE_NUMWAYS = `DCACHE_NUMWAYS;
+  parameter DCACHE_WAYSIZEINBYTES = `DCACHE_WAYSIZEINBYTES;
+  parameter DCACHE_LINELENINBITS = `DCACHE_LINELENINBITS;
+  parameter ICACHE_NUMWAYS = `ICACHE_NUMWAYS;
+  parameter ICACHE_WAYSIZEINBYTES = `ICACHE_WAYSIZEINBYTES;
+  parameter ICACHE_LINELENINBITS = `ICACHE_LINELENINBITS;
+  parameter IDIV_BITSPERCYCLE = `IDIV_BITSPERCYCLE;
+  parameter IDIV_ON_FPU = `IDIV_ON_FPU;
+  parameter PMP_ENTRIES = `PMP_ENTRIES;
+  parameter RESET_VECTOR = `RESET_VECTOR;
+  parameter WFI_TIMEOUT_BIT = `WFI_TIMEOUT_BIT;
+  parameter DTIM_SUPPORTED = `DTIM_SUPPORTED;
+  parameter DTIM_BASE = `DTIM_BASE;
+  parameter DTIM_RANGE = `DTIM_RANGE;
+  parameter IROM_SUPPORTED = `IROM_SUPPORTED;
+  parameter IROM_BASE = `IROM_BASE;
+  parameter IROM_RANGE = `IROM_RANGE;
+  parameter BOOTROM_SUPPORTED = `BOOTROM_SUPPORTED;
+  parameter BOOTROM_BASE = `BOOTROM_BASE;
+  parameter BOOTROM_RANGE = `BOOTROM_RANGE;
+  parameter UNCORE_RAM_SUPPORTED = `UNCORE_RAM_SUPPORTED;
+  parameter UNCORE_RAM_BASE = `UNCORE_RAM_BASE;
+  parameter UNCORE_RAM_RANGE = `UNCORE_RAM_RANGE;
+  parameter EXT_MEM_SUPPORTED = `EXT_MEM_SUPPORTED;
+  parameter EXT_MEM_BASE = `EXT_MEM_BASE;
+  parameter EXT_MEM_RANGE = `EXT_MEM_RANGE;
+  parameter CLINT_SUPPORTED = `CLINT_SUPPORTED;
+  parameter CLINT_BASE = `CLINT_BASE;
+  parameter CLINT_RANGE = `CLINT_RANGE;
+  parameter GPIO_SUPPORTED = `GPIO_SUPPORTED;
+  parameter GPIO_BASE = `GPIO_BASE;
+  parameter GPIO_RANGE = `GPIO_RANGE;
+  parameter UART_SUPPORTED = `UART_SUPPORTED;
+  parameter UART_BASE = `UART_BASE;
+  parameter UART_RANGE = `UART_RANGE;
+  parameter PLIC_SUPPORTED = `PLIC_SUPPORTED;
+  parameter PLIC_BASE = `PLIC_BASE;
+  parameter PLIC_RANGE = `PLIC_RANGE;
+  parameter SDC_SUPPORTED = `SDC_SUPPORTED;
+  parameter SDC_BASE = `SDC_BASE;
+  parameter SDC_RANGE = `SDC_RANGE;
+  parameter AHBW = `AHBW;
+  parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST;
+  parameter UART_PRESCALE = `UART_PRESCALE;
+  parameter PLIC_NUM_SRC = `PLIC_NUM_SRC;
+//  parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32;
+  parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
+  parameter PLIC_UART_ID = `PLIC_UART_ID;
+  parameter BPRED_ENABLED = `BPRED_ENABLED;
+  parameter BPTYPE = `BPTYPE;
+  parameter TESTSBP = `TESTSBP;
+  parameter BPRED_SIZE = `BPRED_SIZE;
+  parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED;
+//  parameter  = `;
+
+
+  // Shared parameters
+
+  // constants defining different privilege modes
+  // defined in Table 1.1 of the privileged spec
+  parameter M_MODE = (2'b11);
+  parameter S_MODE = (2'b01);
+  parameter U_MODE = (2'b00);
+
+  // Virtual Memory Constants
+  parameter VPN_SEGMENT_BITS = (`XLEN == 32 ? 10 : 9);
+  parameter VPN_BITS = (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS));
+  parameter PPN_BITS = (`XLEN==32 ? 22 : 44);
+  parameter PA_BITS = (`XLEN==32 ? 34 : 56);
+  parameter SVMODE_BITS = (`XLEN==32 ? 1 : 4);
+  parameter ASID_BASE = (`XLEN==32 ? 22 : 44);
+  parameter ASID_BITS = (`XLEN==32 ? 9 : 16);
+
+  // constants to check SATP_MODE against
+  // defined in Table 4.3 of the privileged spec
+  parameter NO_TRANSLATE = 0;
+  parameter SV32 = 1;
+  parameter SV39 = 8;
+  parameter SV48 = 9;
+
+  // macros to define supported modes
+  parameter A_SUPPORTED = ((`MISA >> 0) % 2 == 1);
+  parameter B_SUPPORTED = ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)); // not based on MISA
+  parameter C_SUPPORTED = ((`MISA >> 2) % 2 == 1);
+  parameter D_SUPPORTED = ((`MISA >> 3) % 2 == 1);
+  parameter E_SUPPORTED = ((`MISA >> 4) % 2 == 1);
+  parameter F_SUPPORTED = ((`MISA >> 5) % 2 == 1);
+  parameter I_SUPPORTED = ((`MISA >> 8) % 2 == 1);
+  parameter M_SUPPORTED = ((`MISA >> 12) % 2 == 1);
+  parameter Q_SUPPORTED = ((`MISA >> 16) % 2 == 1);
+  parameter S_SUPPORTED = ((`MISA >> 18) % 2 == 1);
+  parameter U_SUPPORTED = ((`MISA >> 20) % 2 == 1);
+  // N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+
+  // logarithm of XLEN, used for number of index bits to select
+  parameter LOG_XLEN = (`XLEN == 32 ? 5 : 6);
+
+  // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
+  parameter PMPCFG_ENTRIES = (`PMP_ENTRIES/8);
+
+  // Floating point constants for Quad, Double, Single, and Half precisions
+  parameter Q_LEN = 32'd128;
+  parameter Q_NE = 32'd15;
+  parameter Q_NF = 32'd112;
+  parameter Q_BIAS = 32'd16383;
+  parameter Q_FMT = 2'd3;
+  parameter D_LEN = 32'd64;
+  parameter D_NE = 32'd11;
+  parameter D_NF = 32'd52;
+  parameter D_BIAS = 32'd1023;
+  parameter D_FMT = 2'd1;
+  parameter S_LEN = 32'd32;
+  parameter S_NE = 32'd8;
+  parameter S_NF = 32'd23;
+  parameter S_BIAS = 32'd127;
+  parameter S_FMT = 2'd0;
+  parameter H_LEN = 32'd16;
+  parameter H_NE = 32'd5;
+  parameter H_NF = 32'd10;
+  parameter H_BIAS = 32'd15;
+  parameter H_FMT = 2'd2;
+
+  // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
+  parameter FLEN = (`Q_SUPPORTED ? `Q_LEN  : `D_SUPPORTED ? `D_LEN  : `S_LEN);
+  parameter NE   = (`Q_SUPPORTED ? `Q_NE   : `D_SUPPORTED ? `D_NE   : `S_NE);
+  parameter NF   = (`Q_SUPPORTED ? `Q_NF   : `D_SUPPORTED ? `D_NF   : `S_NF);
+  parameter FMT  = (`Q_SUPPORTED ? 2'd3    : `D_SUPPORTED ? 2'd1    : 2'd0);
+  parameter BIAS = (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS);
+  
+  // Floating point constants needed for FPU paramerterization
+  parameter FPSIZES = ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED));
+  parameter FMTBITS = ((32)'(`FPSIZES>=3)+1);
+  parameter LEN1  = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN  : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN  : `H_LEN);
+  parameter NE1   = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE   : `H_NE);
+  parameter NF1   = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF   : `H_NF);
+  parameter FMT1  = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1    : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0    : 2'd2);
+  parameter BIAS1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS);
+  parameter LEN2  = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN  : `H_LEN);
+  parameter NE2   = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE   : `H_NE);
+  parameter NF2   = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF   : `H_NF);
+  parameter FMT2  = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0    : 2'd2);
+  parameter BIAS2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS);
+
+  // largest length in IEU/FPU
+  parameter CVTLEN = ((`NF<`XLEN) ? (`XLEN) : (`NF));
+  parameter LLEN = ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN));
+  parameter LOGCVTLEN = $unsigned($clog2(`CVTLEN+1));
+  parameter NORMSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)));
+  parameter LOGNORMSHIFTSZ = ($clog2(`NORMSHIFTSZ));
+  parameter CORRSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)));
+
+  // division constants
+
+  parameter DIVN        = (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2); // standard length of input
+  parameter LOGR        = ($clog2(`RADIX));            // r = log(R)
+  parameter RK          = (`LOGR*`DIVCOPIES);          // r*k used for intdiv preproc
+  parameter LOGRK       = ($clog2(`RK));               // log2(r*k)
+  parameter FPDUR       = ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4));
+  parameter DURLEN      = ($clog2(`FPDUR+1));
+  parameter DIVb        = (`FPDUR*`LOGR*`DIVCOPIES-1); // canonical fdiv size (b)
+  parameter DIVBLEN     = ($clog2(`DIVb+1)-1);
+  parameter DIVa        = (`DIVb+1-`XLEN);             // used for idiv on fpu
+
+endpackage;

From aee984ca69815fbd9b6acecb16161bac5a8002fe Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 15:47:36 -0800
Subject: [PATCH 51/84] Use CVW configuration in top-level

---
 pipelined/src/wally/wallypipelinedcore.sv | 85 ++++++++++-------------
 pipelined/src/wally/wallypipelinedsoc.sv  | 14 ++--
 2 files changed, 43 insertions(+), 56 deletions(-)

diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 2b71851f5..fa244b4f4 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -26,7 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+import cvw::*;  // global CORE-V-Wally parameters
+
 /* verilator lint_on UNUSED */
 
 module wallypipelinedcore (
@@ -35,12 +36,12 @@ module wallypipelinedcore (
    input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
    input  logic [63:0]           MTIME_CLINT, 
    // Bus Interface
-   input  logic [`AHBW-1:0]      HRDATA,
+   input  logic [AHBW-1:0]       HRDATA,
    input  logic                  HREADY, HRESP,
    output logic                  HCLK, HRESETn,
-   output logic [`PA_BITS-1:0]   HADDR,
-   output logic [`AHBW-1:0]      HWDATA,
-   output logic [`XLEN/8-1:0]    HWSTRB,
+   output logic [PA_BITS-1:0]    HADDR,
+   output logic [AHBW-1:0]       HWDATA,
+   output logic [XLEN/8-1:0]     HWSTRB,
    output logic                  HWRITE,
    output logic [2:0]            HSIZE,
    output logic [2:0]            HBURST,
@@ -58,15 +59,15 @@ module wallypipelinedcore (
   logic                          IntDivE, W64E;
   logic                          CSRReadM, CSRWriteM, PrivilegedM;
   logic [1:0]                    AtomicM;
-  logic [`XLEN-1:0]              ForwardedSrcAE, ForwardedSrcBE;
-  logic [`XLEN-1:0] 			 SrcAM;
+  logic [XLEN-1:0]               ForwardedSrcAE, ForwardedSrcBE;
+  logic [XLEN-1:0] 			  SrcAM;
   logic [2:0]                    Funct3E;
   logic [31:0]                   InstrD;
   logic [31:0] 					 InstrM;
-  logic [`XLEN-1:0]              PCF, PCE, PCLinkE;
-  logic [`XLEN-1:0] 			 PCM;
-  logic [`XLEN-1:0]              CSRReadValW, MDUResultW;
-  logic [`XLEN-1:0]              UnalignedPCNextF, PCNext2F;
+  logic [XLEN-1:0]               PCF, PCE, PCLinkE;
+  logic [XLEN-1:0] 			  PCM;
+  logic [XLEN-1:0]               CSRReadValW, MDUResultW;
+  logic [XLEN-1:0]               UnalignedPCNextF, PCNext2F;
   logic [1:0] 					 MemRWM;
   logic 						 InstrValidM;
   logic                          InstrMisalignedFaultM;
@@ -86,9 +87,9 @@ module wallypipelinedcore (
   logic [4:0]                    RdE, RdM, RdW;
   logic                          FPUStallD;
   logic                          FWriteIntE;
-  logic [`FLEN-1:0]              FWriteDataM;
-  logic [`XLEN-1:0]              FIntResM;  
-  logic [`XLEN-1:0]              FCvtIntResW; 
+  logic [FLEN-1:0]               FWriteDataM;
+  logic [XLEN-1:0]               FIntResM;  
+  logic [XLEN-1:0]              FCvtIntResW; 
   logic                          FCvtIntW; 
   logic                          FDivBusyE;
   logic                          IllegalFPUInstrM;
@@ -96,23 +97,23 @@ module wallypipelinedcore (
   logic                          FCvtIntStallD;
   logic                          FpLoadStoreM;
   logic [4:0]                    SetFflagsM;
-  logic [`XLEN-1:0]              FIntDivResultW;
+  logic [XLEN-1:0]               FIntDivResultW;
 
   // memory management unit signals
   logic                          ITLBWriteF;
   logic                          ITLBMissF;
-  logic [`XLEN-1:0]              SATP_REGW;
+  logic [XLEN-1:0]               SATP_REGW;
   logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
   logic  [1:0]                   STATUS_MPP, STATUS_FS;
   logic [1:0]                    PrivilegeModeW;
-  logic [`XLEN-1:0]              PTE;
+  logic [XLEN-1:0]               PTE;
   logic [1:0]                    PageType;
   logic                          sfencevmaM, WFIStallM;
   logic                          SelHPTW;
 
   // PMA checker signals
-  var logic [`XLEN-1:0]          PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
-  var logic [7:0]                PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
+  var logic [XLEN-1:0]           PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
+  var logic [7:0]                PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
 
   // IMem stalls
   logic                          IFUStallF;
@@ -120,14 +121,14 @@ module wallypipelinedcore (
 
   // cpu lsu interface
   logic [2:0]                    Funct3M;
-  logic [`XLEN-1:0]              IEUAdrE;
-  logic [`XLEN-1:0] WriteDataM;
-  logic [`XLEN-1:0] IEUAdrM;  
-  logic [`LLEN-1:0]              ReadDataW;  
+  logic [XLEN-1:0]               IEUAdrE;
+  logic [XLEN-1:0]  WriteDataM;
+  logic [XLEN-1:0]  IEUAdrM;  
+  logic [LLEN-1:0]               ReadDataW;  
   logic                          CommittedM;
 
   // AHB ifu interface
-  logic [`PA_BITS-1:0]           IFUHADDR;
+  logic [PA_BITS-1:0]            IFUHADDR;
   logic [2:0]                    IFUHBURST;
   logic [1:0]                    IFUHTRANS;
   logic [2:0]                    IFUHSIZE;
@@ -135,9 +136,9 @@ module wallypipelinedcore (
   logic                          IFUHREADY;
   
   // AHB LSU interface
-  logic [`PA_BITS-1:0]           LSUHADDR;
-  logic [`XLEN-1:0]              LSUHWDATA;
-  logic [`XLEN/8-1:0]            LSUHWSTRB;
+  logic [PA_BITS-1:0]            LSUHADDR;
+  logic [XLEN-1:0]               LSUHWDATA;
+  logic [XLEN/8-1:0]             LSUHWSTRB;
   logic                          LSUHWRITE;
   logic                          LSUHREADY;
   
@@ -161,11 +162,7 @@ module wallypipelinedcore (
   logic                          BigEndianM;
   logic                          FCvtIntE;
   logic                          CommittedF;
-  
-  // Bit manipulation unit
-  logic [`XLEN-1:0]              BMUResultE;    // Bit manipuation result BMU -> IEU
-  logic                          BMUE;          // is this a BMU instruction
- 
+   
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@@ -193,7 +190,7 @@ module wallypipelinedcore (
      .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
      // Execute Stage interface
      .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
+     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, 
      // Memory stage interface
      .SquashSCW, // from LSU
      .MemRWM, // read/write control goes to LSU
@@ -203,7 +200,7 @@ module wallypipelinedcore (
      .SrcAM, // to privilege and fpu
      .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
      // Writeback stage
-     .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
+     .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
      .InstrValidM, .FCvtIntResW, .FCvtIntW,
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@@ -242,7 +239,7 @@ module wallypipelinedcore (
     .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
     .LSUStallM);                    
 
-  if(`BUS) begin : ebu
+  if(BUS) begin : ebu
     ebu ebu(// IFU connections
       .clk, .reset,
       // IFU interface
@@ -280,7 +277,7 @@ module wallypipelinedcore (
     .FlushD, .FlushE, .FlushM, .FlushW);    
 
   // privileged unit
-  if (`ZICSR_SUPPORTED) begin:priv
+  if (ZICSR_SUPPORTED) begin:priv
     privileged priv(
       .clk, .reset,
       .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
@@ -313,7 +310,7 @@ module wallypipelinedcore (
   end
 
   // multiply/divide unit
-  if (`M_SUPPORTED) begin:mdu
+  if (M_SUPPORTED) begin:mdu
     mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
       .ForwardedSrcAE, .ForwardedSrcBE, 
       .Funct3E, .Funct3M, .IntDivE, .W64E,
@@ -324,12 +321,12 @@ module wallypipelinedcore (
   end
 
   // floating point unit
-  if (`F_SUPPORTED) begin:fpu
+  if (F_SUPPORTED) begin:fpu
     fpu fpu(
       .clk, .reset,
       .FRM_REGW, // Rounding mode from CSR
       .InstrD, // instruction from IFU
-      .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
+      .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
       .ForwardedSrcAE, // Integer input being processed (from IEU)
       .StallE, .StallM, .StallW, // stall signals from HZU
       .FlushE, .FlushM, .FlushW, // flush signals from HZU
@@ -360,15 +357,5 @@ module wallypipelinedcore (
     assign SetFflagsM = 0;
     assign FpLoadStoreM = 0;
   end
-
-  // bit manipulation unit
-  if (`B_SUPPORTED) begin:bmu
-    bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE); 
-  end else begin // no B instructions supported
-    assign BMUResultE = 0; 
-    assign BMUE = 0;
-  end
-
-
   
 endmodule
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv
index 59f213ad0..26979545c 100644
--- a/pipelined/src/wally/wallypipelinedsoc.sv
+++ b/pipelined/src/wally/wallypipelinedsoc.sv
@@ -26,21 +26,21 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+import cvw::*;  // global CORE-V-Wally parameters
 
 module wallypipelinedsoc (
   input  logic 		            clk, 
   input  logic                reset_ext,        // external asynchronous reset pin
   output logic                reset,            // reset synchronized to clk to prevent races on release
   // AHB Interface
-  input  logic [`AHBW-1:0]    HRDATAEXT,
+  input  logic [AHBW-1:0]     HRDATAEXT,
   input  logic 		            HREADYEXT, HRESPEXT,
   output logic 		            HSELEXT,
   // outputs to external memory, shared with uncore memory
   output logic 		            HCLK, HRESETn,
-  output logic [`PA_BITS-1:0] HADDR,
-  output logic [`AHBW-1:0]    HWDATA,
-  output logic [`XLEN/8-1:0]  HWSTRB,
+  output logic [PA_BITS-1:0]  HADDR,
+  output logic [AHBW-1:0]     HWDATA,
+  output logic [XLEN/8-1:0]   HWSTRB,
   output logic 		            HWRITE,
   output logic [2:0] 	        HSIZE,
   output logic [2:0] 	        HBURST,
@@ -63,7 +63,7 @@ module wallypipelinedsoc (
 );
 
   // Uncore signals
-  logic [`AHBW-1:0]           HRDATA;           // from AHB mux in uncore
+  logic [AHBW-1:0]            HRDATA;           // from AHB mux in uncore
   logic                       HRESP;            // response from AHB
   logic                       MTimerInt, MSwInt; // timer and software interrupts from CLINT
   logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
@@ -80,7 +80,7 @@ module wallypipelinedsoc (
    );
 
   // instantiate uncore if a bus interface exists
-  if (`BUS) begin : uncore
+  if (BUS) begin : uncore
     uncore uncore(.HCLK, .HRESETn, .TIMECLK,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,

From eeaa5d9982afe4e8f5523e8b5858878313c78181 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 27 Jan 2023 15:48:30 -0800
Subject: [PATCH 52/84] Removed unneeded lint directive from core

---
 pipelined/src/wally/wallypipelinedcore.sv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index fa244b4f4..5c2c6efce 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -28,8 +28,6 @@
 
 import cvw::*;  // global CORE-V-Wally parameters
 
-/* verilator lint_on UNUSED */
-
 module wallypipelinedcore (
    input  logic                  clk, reset,
    // Privileged

From ff9171aba776fa9a8037ba3501f2feee4edf6c7b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 10:22:59 -0800
Subject: [PATCH 53/84] Added libppa.pl to characterize liberty files

---
 bin/libppa.pl | 246 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 246 insertions(+)
 create mode 100755 bin/libppa.pl

diff --git a/bin/libppa.pl b/bin/libppa.pl
new file mode 100755
index 000000000..56b3702dd
--- /dev/null
+++ b/bin/libppa.pl
@@ -0,0 +1,246 @@
+#!/bin/perl -W
+
+###########################################
+## libppa.pl
+##
+## Written: David_Harris@hmc.edu 
+## Created: 28 January 2023
+##
+## Purpose: Extract PPA information from Liberty files
+##          presently characterizes Skywater 90 and TSMC28hpc+
+##
+## The user will need to change $libpath to point to the desired library in your local installation
+## and for TSMC change the $cellname to the actual name of the inverter.
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+use strict;
+use warnings;
+
+# global variables for simplicity
+my @index1; my @index2;
+my @values;
+my @cr; my @cf; my @rt; my @ft;
+
+# cell and corners to analyze
+my $libpath; my $libbase; my $cellname; my @corners;
+
+# Sky90
+$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
+$libbase = "scc9gena_";
+$cellname = "scc9gena_inv_1";
+@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C");
+printf("Library $libbase Cell $cellname\n");
+foreach my $corner (@corners) {
+    &analyzeCell($corner);
+}
+
+# TSMC
+$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
+$libbase = "tcbn28hpcplusbwp30p140";
+$cellname = "INVD1..."; // replace this with the full name of the library cell
+@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
+printf("\nLibrary $libbase Cell $cellname\n");
+foreach my $corner (@corners) {
+    &analyzeCell($corner);
+}
+
+#############
+# subroutines
+#############
+
+sub analyzeCell {
+    my $corner = shift;
+    my $fname = $libpath."/".$libbase.$corner.".lib";
+    open (FILE, $fname) || die("Can't read $fname");
+    my $incell = 0;
+    my $inleakage = 0;
+    my $inpin = 0;
+    my $incellrise = 0;
+    my $incellfall = 0;
+    my $inrisetrans = 0;
+    my $infalltrans = 0;
+    my $inindex = 0;
+    my $invalues = 0;
+    my $searchstring = "cell (".$cellname.")";
+    my $area; my $leakage; my $cap;
+     while (<FILE>) {
+	if (index($_, $searchstring) != -1) { $incell = 1;}
+	elsif ($incell) {
+	    if (/cell \(/) {
+		$incell = 0;
+		close(FILE);
+		last;
+	    }
+	    if (/area\s*:\s*(.*);/) { $area = $1; }
+	    if (/cell_leakage_power\s*:\s*(.*);/) { $leakage = $1; $inleakage = 2; }
+	    if ($inleakage == 0 && /leakage_power/) { $inleakage = 1; }
+	    if ($inleakage == 1 && /value\s*:\s*(.*);/) {
+		$leakage = $1;
+		$inleakage = 2;
+	    }
+	    if ($inpin == 0 && /pin/) { $inpin = 1; }
+	    if ($inpin == 1 && /\s+capacitance\s*:\s*(.*);/) {
+		$cap = $1;
+		$inpin = 2;
+	    }
+	    if ($inindex == 0 && /index_1/) { $inindex = 1; }
+	    if ($inindex == 1) {
+		if (/index_1\s*\(\"(.*)\"\);/) { @index1 = split(/, /, $1); }
+		if (/index_2\s*\(\"(.*)\"\);/) { @index2 = split(/, /, $1); $inindex = 2; }
+	    }
+	    if ($incellrise == 0 && /cell_rise/) { $incellrise = 1; $invalues = 0;}
+	    if ($incellfall == 0 && /cell_fall/) { $incellfall = 1; $invalues = 0; }
+	    if ($inrisetrans == 0 && /rise_trans/) { $inrisetrans = 1; $invalues = 0; }
+	    if ($infalltrans == 0 && /fall_trans/) { $infalltrans = 1; $invalues = 0; }
+	    if ($incellrise == 1 || $incellfall == 1 || $inrisetrans == 1 || $infalltrans == 1) {
+		if (/values/) { $invalues = 1; @values = (); }
+		elsif ($invalues == 1) {
+		    if (/\);/) {
+			$invalues = 2;
+			if ($incellrise == 1) { @cr = &parseVals(); $incellrise = 2; }
+			if ($incellfall == 1) { @cf = &parseVals(); $incellfall = 2; }
+			if ($inrisetrans == 1) { @rt = &parseVals(); $inrisetrans = 2; }
+			if ($infalltrans == 1) { @ft = &parseVals(); $infalltrans = 2; }
+		    }
+		    elsif (/\"(.*)\"/) { push(@values, $1); }
+		}
+	    }
+#	    print $_;
+	}
+    }
+    
+    my $delay = &computeDelay($cap);
+    my $cornerr = sprintf("%20s", $corner);
+    my $delayr = sprintf("%2.1f", $delay*1000);
+    my $leakager = sprintf("%3.1f", $leakage);
+    
+    print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
+    #print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
+    #print(" index1: @index1\n");
+    #print(" index2: @index2\n");
+    #print("Cell Rise\n"); printMatrix(\@cr);
+    #print("Cell Fall\n"); printMatrix(\@cf);
+    #print("Rise Trans\n"); printMatrix(\@rt);
+    #print("Fall Trans\n"); printMatrix(\@ft);
+}
+
+sub computeDelay {
+    # relies on cr, cf, rt, ft, index1, index2
+    # index1 for rows of matrix (different trans times, units of ns)
+    # index2 for cols of matrix (different load capacitances, units of pF)
+
+    # first, given true load, create a rise/fall delay and transition
+    # as a function of trans time, interpolated
+    my $cap = shift;
+    my $fo4cap = 4*$cap;
+    my @cri = &interp2(\@cr, $fo4cap);
+    my @cfi = &interp2(\@cf, $fo4cap);
+    my @rti = &interp2(\@rt, $fo4cap);
+    my @fti = &interp2(\@ft, $fo4cap);
+
+    # initially guess second smallest transition time
+    my $tt = $index1[1];
+    # assume falling input with this transition, compute rise delay & trans
+    my $cr0 = &interp1(\@cri, \@index1, $tt);
+    my $rt0 = &interp1(\@rti, \@index1, $tt);
+    # now assuming rising input with rt0, compute fall delay & trans
+    my $cf1 = &interp1(\@cfi, \@index1, $rt0);
+    my $ft1 = &interp1(\@fti, \@index1, $rt0);
+    # now assuming falling input with ft1, compute rise delay & trans
+    my $cr2 = &interp1(\@cri, \@index1, $ft1);
+    my $rt2 = &interp1(\@rti, \@index1, $ft1);
+    # now assuming rising input with rt2, compute fall delay & trans
+    my $cf3 = &interp1(\@cfi, \@index1, $rt2);
+    my $ft3 = &interp1(\@fti, \@index1, $rt2);
+
+    # delay is average of rising and falling
+    my $delay = ($cr2 + $cf3)/2;
+    return $delay;
+    
+#    print("tt $tt cr0 $cr0 rt0 $rt0\n");
+#    print("cf1 $cf1 ft1 $ft1 cr2 $cr2 rt2 $rt2 cf3 $cf3 ft3 $ft3 delay $delay\n");
+}
+
+sub interp2 {
+    my $matref = shift;
+    my @matrix = @$matref;
+    my $fo4cap = shift;
+    my @interp = ();
+    
+    my $i;
+    # interpolate row by row
+    for ($i=0; $i <= $#index1; $i++) {
+	my @row = @{$matrix[$i]};
+	#print ("Extracted row $i = @row\n");
+	$interp[$i] = &interp1(\@row, \@index2, $fo4cap);
+    }
+    return @interp;
+}
+
+sub interp1 {
+    my $vecref = shift;
+    my @vec = @$vecref;
+    my $indexref = shift;
+    my @index = @$indexref;
+    my $x = shift;
+
+    # find entry i containing the first index greater than x
+    my $i = 0;
+    while ($index[$i] < $x) {$i++}
+    my $start = $index[$i-1];
+    my $end = $index[$i];
+    my $fract = ($x-$start)/($end-$start);
+    my $interp = $vec[$i-1] + ($vec[$i] - $vec[$i-1])*$fract;
+
+#    print ("Interpolating $x as $interp from i $i start $start end $end based on index @index and vec @vec\n");
+
+    return $interp;
+}
+
+sub parseVals {
+    # relies on global variables @values, @index1, @index2
+    my @vals;
+    my $i; my $j;
+    for ($i=0; $i <= $#index1; $i++) {
+	my @row = split(/, /,$values[$i]);
+	for ($j = 0; $j <= $#index2; $j++) {
+	    $vals[$i][$j] = $row[$j];
+	}
+    }
+    return @vals;
+}
+
+sub printMatrix {
+    my $mat = shift;
+    my @matrix = @$mat;
+    my $i; my $j;
+    for ($i=0; $i <= $#index1; $i++) {
+	for ($j = 0; $j <= $#index2; $j++) {
+	    print($matrix[$i][$j]." ");
+	}
+	print("\n");
+    }
+}
+
+    
+    
+
+
+

From 1041775be4c71210a5e607ff90413e0f392cc38e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 10:51:39 -0800
Subject: [PATCH 54/84] Removed DEISGN_COMPILER configuration paramter

---
 pipelined/config/buildroot/wally-config.vh  | 1 -
 pipelined/config/fpga/wally-config.vh       | 2 --
 pipelined/config/rv32e/wally-config.vh      | 1 -
 pipelined/config/rv32gc/wally-config.vh     | 1 -
 pipelined/config/rv32i/wally-config.vh      | 1 -
 pipelined/config/rv32ic/wally-config.vh     | 1 -
 pipelined/config/rv64fpquad/wally-config.vh | 1 -
 pipelined/config/rv64gc/wally-config.vh     | 1 -
 pipelined/config/rv64i/wally-config.vh      | 1 -
 9 files changed, 10 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index 814e37761..a4ec7fb47 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -42,7 +42,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 `define COUNTERS 32
-`define DESIGN_COMPILER 0
 
 // LSU microarchitectural Features
 `define BUS 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 6b977fcbc..56bf10402 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 1
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
@@ -44,7 +43,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 `define COUNTERS 32
-`define DESIGN_COMPILER 0
 
 // LSU microarchitectural Features
 `define BUS 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index 66d4049f8..b42633679 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 85c207e91..2704a9a00 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index b6330579f..119354aa8 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index 085bbad3b..49281c289 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index aab3df73e..4d36ff303 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index 606c95eb8..c00e02843 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index 203ee4552..b0df9bc30 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -30,7 +30,6 @@
 
 `define FPGA 0
 `define QEMU 0
-`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64

From 6c59c21a26eb52857a55eeb5b2670450cdf11d4d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 10:58:02 -0800
Subject: [PATCH 55/84] Updated cvw to be consistent with configs

---
 pipelined/src/wally/cvw.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv
index e35b22fb2..5fd28163e 100644
--- a/pipelined/src/wally/cvw.sv
+++ b/pipelined/src/wally/cvw.sv
@@ -36,7 +36,6 @@ package cvw;
   parameter XLEN = `XLEN;
   parameter FPGA = `FPGA;
   parameter QEMU = `QEMU;
-  parameter DESIGN_COMPILER = `DESIGN_COMPILER;
   parameter IEEE754 = `IEEE754;
   parameter MISA = `MISA;
   parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED;
@@ -215,4 +214,4 @@ package cvw;
   parameter DIVBLEN     = ($clog2(`DIVb+1)-1);
   parameter DIVa        = (`DIVb+1-`XLEN);             // used for idiv on fpu
 
-endpackage;
+endpackage

From 1b0b9314c4cd009bdf7af5a1740d958fa4c0f979 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 10:58:36 -0800
Subject: [PATCH 56/84] removed unused memory model

---
 pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v | 1 -
 1 file changed, 1 deletion(-)
 delete mode 120000 pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v

diff --git a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v
deleted file mode 120000
index c81975209..000000000
--- a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v
+++ /dev/null
@@ -1 +0,0 @@
-/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v
\ No newline at end of file

From ed1aaa6c8f81ae321ed091785fc52e6fb97c08be Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 11:00:05 -0800
Subject: [PATCH 57/84] Comment cleanup in subcachelineread

---
 pipelined/src/cache/subcachelineread.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv
index 346ec710e..490618070 100644
--- a/pipelined/src/cache/subcachelineread.sv
+++ b/pipelined/src/cache/subcachelineread.sv
@@ -30,8 +30,8 @@
 `include "wally-config.vh"
 
 module subcachelineread #(parameter LINELEN, WORDLEN, 
-  parameter MUXINTERVAL                                                        // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
-)(
+  parameter MUXINTERVAL )(     // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
+
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,       // Physical address 
   input  logic [LINELEN-1:0] 									  ReadDataLine,// Read data of the whole cacheline
   output logic [WORDLEN-1:0] 									  ReadDataWord // read data of selected word.

From 3f25123c6358edabf3fa3d7486ce05e542d29853 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 28 Jan 2023 16:14:19 -0600
Subject: [PATCH 58/84] Possible fix for speculative gshare.

---
 pipelined/regression/wave.do                  | 78 ++++++++++---------
 pipelined/src/ifu/brpred/bpred.sv             |  2 +-
 pipelined/src/ifu/brpred/speculativegshare.sv | 43 +++++-----
 3 files changed, 68 insertions(+), 55 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index bfa161dad..b2d2cfd2f 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -61,10 +61,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/Inst
 add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
 add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
-add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
-add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
-add wave -noupdate -group {Memory Stage} /testbench/InstrMName
-add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
@@ -99,6 +99,7 @@ add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
 add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
@@ -573,12 +574,6 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM
@@ -588,34 +583,47 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
 add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
+add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
+add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
-add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
-add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
-add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
-add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
-add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
-add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -631,4 +639,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {2195 ns} {2479 ns}
+WaveRestoreZoom {5721 ns} {5893 ns}
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 3fd021574..6af314646 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 1
+`define INSTR_CLASS_PRED 0
 
 module bpred (
    input logic              clk, reset,
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 85cb3654c..649800975 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -53,10 +53,10 @@ module speculativegshare
 
   logic [k-1:0]            GHRF, OldGHRF;
   logic 				   OldGHRExtraF;
-  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
-  logic [k-1:0]            GHRNextF;
-  logic [k:0] 			   GHRNextD;
-  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
+  logic [k-1:0] 		   GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0] 		   GHRNextF;
+  logic [k-1:0] 		   GHRNextD;
+  logic [k-1:0] 		   GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE;
   
@@ -113,31 +113,36 @@ module speculativegshare
 
   always_comb begin
 	if(FlushD) begin
-	  if(BranchInstrE) GHRNextF =  GHRNextD[k:1];
-	  else             GHRNextF = GHRNextD[k-1:0];
+	  //if(BranchInstrE) GHRNextF =  {PCSrcE, GHRNextD[k-1:1]};
+	  //else             GHRNextF = GHRNextD[k-1:0];
+	  GHRNextF = GHRNextD[k-1:0];
 	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
 	else GHRNextF = GHRF;
   end
-	
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
-  flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
-  assign GHRF = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
-  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}:       // shift left
-  				OldGHRF[k-1:0];
+
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);	
+  //flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
+  //flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
+//  assign GHRF = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
+//  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}:       // shift left
+//  				OldGHRF[k-1:0];
   
-  assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF};
+  //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]};
+  assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
 
-  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+  flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
 
-  assign GHRNextE = FlushE ? GHRNextM : GHRD;
-  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
-  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+  assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed and was mispredicted
+					FlushE ? GHRNextM :                                // branch is flushed
+					GHRD;
+  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
+  //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
 
   assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+  flopenr  #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
 
   assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  flopenr  #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 

From b52990e2ceeb9bb97eab97ee545573098c105928 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 28 Jan 2023 16:42:19 -0600
Subject: [PATCH 59/84] Possible workign instruction class prediction repair.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 24 +++++++++----------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 649800975..7760cbef9 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -52,7 +52,7 @@ module speculativegshare
   logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
   logic [k-1:0]            GHRF, OldGHRF;
-  logic 				   OldGHRExtraF;
+  logic 				   GHRExtraF;
   logic [k-1:0] 		   GHRD, OldGHRE, GHRE, GHRM, GHRW;
   logic [k-1:0] 		   GHRNextF;
   logic [k-1:0] 		   GHRNextD;
@@ -113,30 +113,28 @@ module speculativegshare
 
   always_comb begin
 	if(FlushD) begin
-	  //if(BranchInstrE) GHRNextF =  {PCSrcE, GHRNextD[k-1:1]};
-	  //else             GHRNextF = GHRNextD[k-1:0];
 	  GHRNextF = GHRNextD[k-1:0];
 	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
 	else GHRNextF = GHRF;
   end
 
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);	
-  //flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
-  //flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
-//  assign GHRF = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
-//  				WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}:       // shift left
-//  				OldGHRF[k-1:0];
-  
-  //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]};
-  assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
+  flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
+
+  // use with out instruction class prediction
+  //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
+  // with instruction class prediction
+  assign GHRNextD = FlushD ? GHRNextE[k-1:0] :
+					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
+  					WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}:       // shift left
+					GHRF[k-1:0];
 
   flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
 
-  assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed and was mispredicted
+  assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed
 					FlushE ? GHRNextM :                                // branch is flushed
 					GHRD;
   flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
-  //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
 
   assign GHRNextM = FlushM ? GHRNextW : GHRE;
   flopenr  #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);

From 3ddf95ac6e3d63ed890b5a3f11223cbefc28fc24 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 28 Jan 2023 17:00:50 -0600
Subject: [PATCH 60/84] Found an issue where the btb was not forwarding the
 valid bit!

---
 pipelined/src/ifu/brpred/btb.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 9b6c66b85..20500226a 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -56,6 +56,7 @@ module btb
   logic [`XLEN-1:0] 		PredPCD;  
   logic [3:0] 				PredInstrClassD;  // *** copy of reg outside module
   logic 					UpdateEn;
+  logic 					TablePredValidF;
     
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
@@ -93,9 +94,11 @@ module btb
     end else if ((UpdateEn) & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
-	PredValidF = ValidBits[PCNextFIndex];
+	TablePredValidF = ValidBits[PCNextFIndex];
   end
 
+  assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
+  
   assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
 
   // An optimization may be using a PC relative address.

From 684a7214cbacc3509f778cbe6e6825e9d0a4f137 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 28 Jan 2023 17:50:46 -0600
Subject: [PATCH 61/84] Added another performance counter to track overall
 branch miss-predictions.

---
 pipelined/regression/wave.do              |  6 ++++--
 pipelined/src/ifu/brpred/bpred.sv         |  2 +-
 pipelined/src/ifu/ifu.sv                  |  3 ++-
 pipelined/src/privileged/csr.sv           |  3 ++-
 pipelined/src/privileged/csrc.sv          |  4 +++-
 pipelined/src/privileged/privileged.sv    | 11 ++++++-----
 pipelined/src/wally/wallypipelinedcore.sv |  6 +++---
 pipelined/testbench/testbench.sv          |  3 ++-
 8 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index b2d2cfd2f..cdae10c6b 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -531,6 +531,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -lab
 add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
@@ -622,8 +623,9 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {217131 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -639,4 +641,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {5721 ns} {5893 ns}
+WaveRestoreZoom {135840 ns} {362253 ns}
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 6af314646..639dbcd50 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -59,6 +59,7 @@ module bpred (
 
    // Report branch prediction status
    output logic             BPPredWrongE,              // Prediction is wrong
+   output logic             BPPredWrongM,              // Prediction is wrong
    output logic             DirPredictionWrongM,       // Prediction direction is wrong
    output logic             BTBPredPCWrongM,           // Prediction target wrong
    output logic             RASPredPCWrongM,           // RAS prediction is wrong
@@ -79,7 +80,6 @@ module bpred (
   
   logic                     SelBPPredF;
   logic [`XLEN-1:0]         BPPredPCF;
-  logic                     BPPredWrongM;
   logic [`XLEN-1:0]         PCNext0F;
   logic [`XLEN-1:0] 		PCCorrectE;
   logic [3:0] 				WrongPredInstrClassD;
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 9be88d568..242fb6944 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -51,6 +51,7 @@ module ifu (
   input  logic [`XLEN-1:0] 	IEUAdrE,                                  // The branch/jump target address
   output logic [`XLEN-1:0] 	PCE,                                      // Execution stage instruction address
   output logic 				BPPredWrongE,                             // Prediction is wrong
+  output logic 				BPPredWrongM,                             // Prediction is wrong
   // Mem
   output logic              CommittedF,                               // I$ or bus memory operation started, delay interrupts
   input  logic [`XLEN-1:0] 	UnalignedPCNextF,                         // The next PCF, but not aligned to 2 bytes. 
@@ -328,7 +329,7 @@ module ifu (
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM,
+                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
 
   end else begin : bpred
diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index 9a91d371e..ef4d73cb2 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -61,6 +61,7 @@ module csr #(parameter
   input  logic             BTBPredPCWrongM,
   input  logic             RASPredPCWrongM,
   input  logic             PredictionInstrClassWrongM,
+  input  logic             BPPredWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,
   input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,
@@ -256,7 +257,7 @@ module csr #(parameter
   if (`ZICOUNTERS_SUPPORTED) begin:counters
     csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
-      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM,
+      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .BPPredWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index 83e3ccdfe..bd5ede793 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -48,6 +48,7 @@ module csrc #(parameter
   input  logic 	            BTBPredPCWrongM,
   input  logic 	            RASPredPCWrongM,
   input  logic 	            PredictionInstrClassWrongM,
+  input  logic              BPPredWrongM,                              // branch predictor is wrong
   input  logic [3:0]        InstrClassM,
   input  logic              JumpOrTakenBranchM,                               // actual instruction class
   input  logic 	            DCacheMiss,
@@ -96,7 +97,8 @@ module csrc #(parameter
     assign CounterEvent[12] = DCacheMiss;                                               // data cache miss
     assign CounterEvent[13] = ICacheAccess;                                             // instruction cache access
     assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss
-    assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+	assign CounterEvent[15] = BPPredWrongM;                                             // branch predictor wrong
+    assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end
   
   // Counter update and write logic
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index c3f321753..29d65f131 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -46,10 +46,11 @@ module privileged (
   // processor events for performance counter logging
   input  logic             FRegWriteM,                                // instruction will write floating-point registers
   input  logic             LoadStallD,                                // load instruction is stalling
-  input  logic 		         DirPredictionWrongM,                       // branch predictor guessed wrong directoin
-  input  logic 		         BTBPredPCWrongM,                           // branch predictor guessed wrong target
-  input  logic 		         RASPredPCWrongM,                           // return adddress stack guessed wrong target
-  input  logic 		         PredictionInstrClassWrongM,                // branch predictor guessed wrong instruction class
+  input  logic 		         DirPredictionWrongM,                     // branch predictor guessed wrong directoin
+  input  logic 		         BTBPredPCWrongM,                         // branch predictor guessed wrong target
+  input  logic 		         RASPredPCWrongM,                         // return adddress stack guessed wrong target
+  input  logic 		         PredictionInstrClassWrongM,              // branch predictor guessed wrong instruction class
+  input  logic             BPPredWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,                               // actual instruction class
   input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,                                // data cache miss
@@ -124,7 +125,7 @@ module privileged (
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
-    .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
+    .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredWrongM,
     .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index c6f5240a3..e2f04682a 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -141,7 +141,7 @@ module wallypipelinedcore (
   logic                          LSUHWRITE;
   logic                          LSUHREADY;
   
-  logic                          BPPredWrongE;
+  logic                          BPPredWrongE, BPPredWrongM;
   logic                          DirPredictionWrongM;
   logic                          BTBPredPCWrongM;
   logic                          RASPredPCWrongM;
@@ -175,7 +175,7 @@ module wallypipelinedcore (
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
     .ICacheAccess, .ICacheMiss,
     // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, 
+    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,  .BPPredWrongM, 
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
@@ -290,7 +290,7 @@ module wallypipelinedcore (
       .RetM, .TrapM, .sfencevmaM,
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD,
-      .DirPredictionWrongM, .BTBPredPCWrongM,
+      .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM,
       .RASPredPCWrongM, .PredictionInstrClassWrongM,
       .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 5456ce8b9..1e373de57 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -424,7 +424,8 @@ logic [3:0] dummy;
                             "D Cache Access",
                             "D Cache Miss",
                             "I Cache Access",
-                            "I Cache Miss"};
+                            "I Cache Miss",
+							"Br Pred Wrong"};
     always @(negedge clk) begin
       if(DCacheFlushStart & ~DCacheFlushDone) begin
         for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin

From 6945eaf045507b97f175f36374b934d74cfaa6d8 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 28 Jan 2023 17:56:56 -0600
Subject: [PATCH 62/84] Fixed bug with the new csr.

---
 pipelined/src/privileged/csrc.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index bd5ede793..94dbcaf48 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -97,7 +97,7 @@ module csrc #(parameter
     assign CounterEvent[12] = DCacheMiss;                                               // data cache miss
     assign CounterEvent[13] = ICacheAccess;                                             // instruction cache access
     assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss
-	assign CounterEvent[15] = BPPredWrongM;                                             // branch predictor wrong
+	assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM;                     // branch predictor wrong
     assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end
   

From ee1bcf62ee99fda127cc7ab28da731697edef2f4 Mon Sep 17 00:00:00 2001
From: Kip Macsai-Goren <kmacsaigoren@hmc.edu>
Date: Sat, 28 Jan 2023 17:29:35 -0800
Subject: [PATCH 63/84] Fixed regression test dependance on bp status by adding
 handling of UART tx empty interrupts.

---
 .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 45 ++++++++++---------
 .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 45 ++++++++++---------
 2 files changed, 48 insertions(+), 42 deletions(-)

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 07813da16..1171786f4 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -1068,33 +1068,36 @@ uart_save_iir_status:
     j test_loop
 
 uart_data_wait:
-    li t2, 0x10000005 // LSR
-    li t3, 0x10000002 // IIR
-    li a4, 0x61
-uart_read_LSR_IIR:
-    lbu t4, 0(t3) // save IIR before reading LSR might clear it
-    //  check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this.
-    li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
-    beq t4, t5, uart_rxfifo_timout
-    lb t5, 0(t2) // read LSR
-    andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
-    bne a4, t6, uart_read_LSR_IIR
+    li t2, 0x10000002
+    lbu t3, 0(t2) // save IIR before reading LSR might clear it
+    // Check IIR to see if theres an rxfifio or txempty interrupt and handle it before continuing.
+    li t2, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
+    beq t3, t2, uart_rxfifo_timout
+    li t2, 0xC2 // Value in IIR for Fifo Enabled, with txempty interrupt pending.
+    beq t3, t2, uart_txempty_intr
+    li t2, 0x10000005 // There needs to be an instruction here between the beq and the lb or the tests will hang
+    lb t4, 0(t2) // read LSR
+    li t2, 0x61
+    bne t4, t2, uart_data_wait // wait until all transmissions are done and data is ready
     j uart_data_ready
 uart_rxfifo_timout:
-    li t4, 0x10000000 // read from the fifo to clear the rx timeout error
-    lb t5, 0(t4)
-    sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
-    //read the fifo until empty
-    j uart_read_LSR_IIR
-
+    li t2, 0x10000000 // read from the fifo to clear the rx timeout error
+    lb t5, 0(t2)
+    sb t5, 0(t2) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
+    j uart_data_wait
+uart_txempty_intr:
+    li t2, 0x10000002
+    lb t5, 0(t2) // Read IIR to clear this bit in LSR
+    j uart_data_wait
 
 uart_data_ready:
+    li t2, 0x10000002
+    lbu t3, 0(t2) // re read IIR
+    andi t4, t4, 0x9F // mask THRE and TEMT from IIR signature
     li t2, 0
     sw t2, 0(t1) // clear entry deadbeef from memory
-    lbu t4, 0(t3) // re read IIR
-    andi t5, t5, 0x9F // mask THRE and TEMT from signature
-    sb t4, 1(t1) // IIR
-    sb t5, 0(t1) // LSR
+    sb t3, 1(t1) // IIR
+    sb t4, 0(t1) // LSR
     addi t1, t1, 4
     addi a6, a6, 4
     j test_loop
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 86568c12b..576636deb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -1107,33 +1107,36 @@ uart_save_iir_status:
     j test_loop
 
 uart_data_wait:
-    li t2, 0x10000005 // LSR
-    li t3, 0x10000002 // IIR
-    li a4, 0x61
-uart_read_LSR_IIR:
-    lbu t4, 0(t3) // save IIR before reading LSR might clear it
-    //  check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this.
-    li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
-    beq t4, t5, uart_rxfifo_timout
-    lb t5, 0(t2) // read LSR
-    andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
-    bne a4, t6, uart_read_LSR_IIR
+    li t2, 0x10000002
+    lbu t3, 0(t2) // save IIR before reading LSR might clear it
+    // Check IIR to see if theres an rxfifio or txempty interrupt and handle it before continuing.
+    li t2, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
+    beq t3, t2, uart_rxfifo_timout
+    li t2, 0xC2 // Value in IIR for Fifo Enabled, with txempty interrupt pending.
+    beq t3, t2, uart_txempty_intr
+    li t2, 0x10000005 // There needs to be an instruction here between the beq and the lb or the tests will hang
+    lb t4, 0(t2) // read LSR
+    li t2, 0x61
+    bne t4, t2, uart_data_wait // wait until all transmissions are done and data is ready
     j uart_data_ready
 uart_rxfifo_timout:
-    li t4, 0x10000000 // read from the fifo to clear the rx timeout error
-    lb t5, 0(t4)
-    sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
-    //read the fifo until empty
-    j uart_read_LSR_IIR
-
+    li t2, 0x10000000 // read from the fifo to clear the rx timeout error
+    lb t5, 0(t2)
+    sb t5, 0(t2) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
+    j uart_data_wait
+uart_txempty_intr:
+    li t2, 0x10000002
+    lb t5, 0(t2) // Read IIR to clear this bit in LSR
+    j uart_data_wait
 
 uart_data_ready:
+    li t2, 0x10000002
+    lbu t3, 0(t2) // re read IIR
+    andi t4, t4, 0x9F // mask THRE and TEMT from IIR signature
     li t2, 0
     sd t2, 0(t1) // clear entry deadbeef from memory
-    lbu t4, 0(t3) // re read IIR
-    andi t5, t5, 0x9F // mask THRE and TEMT from signature
-    sb t4, 1(t1) // IIR
-    sb t5, 0(t1) // LSR
+    sb t3, 1(t1) // IIR
+    sb t4, 0(t1) // LSR
     addi t1, t1, 8
     addi a6, a6, 8
     j test_loop

From 5a0d8aed23d269c33d2f2954a126ef54bfcebe97 Mon Sep 17 00:00:00 2001
From: James Stine <James Stine>
Date: Sat, 28 Jan 2023 19:33:00 -0600
Subject: [PATCH 64/84] Modified changes as follows * Add docs directory for
 Docker including Dockerfile * Change to synthesis script to include fpu stuff
 * Add wrappers for IP (may need some cleanup but will cleanup shortly)

---
 docs/D-Docker-Install.md                      | 206 ++++++++++++++++++
 docs/Dockerfile                               | 132 +++++++++++
 pipelined/src/generic/mem/ram1p1rwbe.sv       |  28 ++-
 .../src/generic/mem/ram1p1rwbe_64x128.sv      |  40 ++++
 pipelined/src/generic/mem/ram1p1rwbe_64x44.sv |  40 ++++
 .../src/generic/mem/ram2p1rwbe_1024x69.sv     |  48 ++++
 pipelined/src/generic/mem/rom1p1r_128x32.sv   |  38 ++++
 synthDC/scripts/synth.tcl                     |   1 +
 8 files changed, 523 insertions(+), 10 deletions(-)
 create mode 100644 docs/D-Docker-Install.md
 create mode 100755 docs/Dockerfile
 create mode 100755 pipelined/src/generic/mem/ram1p1rwbe_64x128.sv
 create mode 100644 pipelined/src/generic/mem/ram1p1rwbe_64x44.sv
 create mode 100755 pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv
 create mode 100755 pipelined/src/generic/mem/rom1p1r_128x32.sv

diff --git a/docs/D-Docker-Install.md b/docs/D-Docker-Install.md
new file mode 100644
index 000000000..25fb3c4d1
--- /dev/null
+++ b/docs/D-Docker-Install.md
@@ -0,0 +1,206 @@
+D Wally Toolchain Docker Container
+
+Installing RISC-V tools from source gives you maximum control, but has several disadvantages:
+
+* Building the executables takes several hours.
+* Linux is poorly standardized, and the build steps might not work on your version
+* The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
+
+Docker is a tools to run applications in a prepackaged container including all of the operating system support required.  Wally offers a ~30GB container image with the open-source tools pre-installed from Section D.1. In particular, using the container solves the long build time for gcc and the fussy installation of sail. The container runs on any platform supporting Docker, including Windows and Mac as well as Linux.  It can access files outside the container, including local installation of CAD tools such as Questa, and a local clone of the core-v-wally repository.
+
+Docker can be run on most operating systems, including Linux, Windows, and Mac. The Wally Docker container is hosted at DockerHub (http://docker.io).
+
+Podman is a more secure and easier-to-use variation of Docker for Linux developed by RedHat.  Both Docker and Podman run the same containers.  
+
+D.3.1	Podman Installation on Linux
+
+A system administrator must install Podman if it is not already present.
+
+For Ubuntu 20.10 or later:
+
+$ sudo apt-get -y install podman
+
+For RedHat / Rocky:
+
+$ sudo yum -y install podman
+
+D.3.2	Pulling the Wally Container
+
+Once Podman is installed, a user can pull the Wally container image.  The user must sign up for a free account at docker.io, and will be prompted for the credentials when running podman login.
+
+$ podman login docker.io
+$ podman pull docker.io/wallysoc/wally-docker:latest
+
+D.3.3	Running the Docker Container in Podman
+
+To activate podman with GUI support, first identify your display port in the /tmp/.X11-unix file as shown below.  For example, the user ben is on port X51.  
+
+$ ls -la /tmp/.X11-unix/
+drwxrwxrwt   2 root    root     4096 Jan  6 05:01 .
+drwxrwxrwt 122 root    root    40960 Jan 17 08:09 ..
+srwxrwxrwx   1 root    root        0 Jan  5 08:48 X0
+srwxrwxrwx   1 xwalter xwalter     0 Jan  5 09:21 X50
+srwxrwxrwx   1 ben     ben         0 Jan  6 05:01 X51
+
+Then run podman with the display number after the X (51 in this case).  The -v options also mount the user’s home directory (/home/ben) and cad tools (/cad) to be visible from the container.  Change these as necessary based on your local system configuration.
+
+$ podman run -it --net=host -e DISPLAY=:51 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/ben:/home/ben -v /cad:/cad -p 8080:8080 docker.io/wallysoc/wally-docker
+
+Podman sets up all the RISC-V software in the same location of /opt/riscv as the cad user as discussed previously.  This shared directory is called $RISCV.  This environmental variable should also be set up within the Docker container automatically and ready to use once the container is run.  It is important to understand that Docker containers are self-contained, and any data created within your container is lost when you exit the container. Therefore, be sure to work in your mounted home directory (e.g. /home/ben) to permanently save your work outside the container.
+
+To have permission to write to your mounted home directory, you must become root inside the Wally container.  This is an acceptable practice as the security will be maintained within podman for the user that runs podman.  To become root once inside your container:
+  
+$ su			# when prompted for password, enter wally
+
+D.3.4	Cleaning up a Podman Container
+
+The Docker container image is large, so users may need to clean up a container when they aren’t using it anymore.
+The images that are loaded can be examined, once you pull the Wally container, by typing:
+
+$ podman images 
+
+To remove individual podman images, the following Linux command will remove the specific podman image where the image name is obtained from the  podman images command (this command also works equally well using the <Image_ID> instead of the <Image_name>, as well). 
+
+$ podman rmi -f <Image_name> 
+
+D.3.5	Running the Docker Container on Windows or MacOS
+
+Docker Desktop is easiest to use for Mac OS or Windows and can be installed by downloading from http://docker.com.  Once the desktop application is installed, users can log into their DockerHub account through the Docker Desktop application and manage their containers easily.  
+
+*** with Questa
+*** questa unavailable native on Mac
+
+
+D.3.6	Regenerating the Docker File
+
+We use the following steps to generate the Docker file.  You can adapt them is you wish to make your own custom Docker image, such as one with commercial CAD tools installed in your local environment.
+
+*** how to use this
+
+# Compliance Development Environment Image
+FROM debian
+
+# UPDATE / UPGRADE
+RUN apt update
+
+# INSTALL
+RUN apt install -y git gawk make texinfo bison flex build-essential python libz-
+dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build
+-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-
+dev python3-pip pkg-config libglib2.0-dev opam  build-essential z3 pkg-config zl
+ib1g-dev verilator cpio bc vim emacs gedit nano
+
+RUN pip3 install chardet==3.0.4
+RUN pip3 install urllib3==1.22
+RUN pip3 install testresources
+RUN pip3 install riscof --ignore-installed PyYAML
+RUN echo "root:wally" | chpasswd
+
+# ADD RISCV
+WORKDIR /opt/riscv
+
+# Create a user group 'xyzgroup'
+ARG USERNAME=cad
+ARG USER_UID=1000
+ARG USER_GID=$USER_UID
+
+# Create the user
+RUN groupadd --gid $USER_GID $USERNAME \
+    && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
+    # [Optional] Add sudo support. Omit if you don't need to install software af
+ter connecting.
+    && apt-get update \
+    && apt-get install -y sudo \
+    && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
+    && chmod 0440 /etc/sudoers.d/$USERNAME
+
+# Change RISCV user
+run chown -Rf cad:cad /opt
+
+# Add cad user
+USER $USERNAME
+
+# SET ENVIRONMENT VARIABLES
+ENV RISCV=/opt/riscv
+ENV PATH=$PATH:$RISCV/bin
+
+# TOOLCHAIN
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
+    cd riscv-gnu-toolchain && \
+    ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="r
+v32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32
+imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv6
+4imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
+    make --jobs && \
+    make install
+
+# elf2hex
+ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+WORKDIR /opt/riscv
+RUN git clone https://github.com/sifive/elf2hex.git && \
+  cd elf2hex && \
+  autoreconf -i && \
+  ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
+  make && \
+  make install
+
+# QEMU
+WORKDIR /opt/riscv
+RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
+  cd qemu && \
+  ./configure --target-list=riscv64-softmmu --prefix=$RISCV  && \
+  make --jobs && \
+  make install
+
+# Spike
+WORKDIR /opt/riscv
+RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
+  mkdir riscv-isa-sim/build && \
+  cd riscv-isa-sim/build && \
+  ../configure --prefix=$RISCV --enable-commitlog && \
+  make --jobs && \
+  make install  && \
+  cd ../arch_test_target/spike/device && \
+  sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
+  sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
+
+# SAIL
+WORKDIR /opt/riscv
+RUN opam init -y --disable-sandboxing
+RUN opam switch create ocaml-base-compiler.4.06.1
+RUN opam install sail -y
+RUN eval $(opam config env) && \
+ cd $RISCV && \
+ git clone https://github.com/riscv/sail-riscv.git && \
+ cd sail-riscv && \
+ make && \
+ ARCH=RV32 make && \
+ ARCH=RV64 make && \
+ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && 
+\
+ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
+
+# Buildroot
+WORKDIR /opt/riscv
+RUN git clone --recurse-submodules https://stineje:ghp_kXIHqiMSv4tFec2BCAvrhSrIh
+3KNUD06IejU@github.com/davidharrishmc/riscv-wally.git
+ENV export WALLY=/opt/riscv/riscv-wally
+RUN git clone https://github.com/buildroot/buildroot.git && \
+  cd buildroot && \
+  git checkout 2021.05 && \
+  cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
+  cp ./board/wally/main.config .config && \
+  make --jobs
+
+# change to cad's hometown
+WORKDIR /home/cad
+
+
+D.3.7	Integrating Commercial CAD Tools into a Local Docker Container
+
+
+
+RISC-V System-on-Chip Design Lecture Notes 
+© 2023 D. Harris, J. Stine, , R. Thompson, and S. Harris
+These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.
+
diff --git a/docs/Dockerfile b/docs/Dockerfile
new file mode 100755
index 000000000..cdc3dbcfc
--- /dev/null
+++ b/docs/Dockerfile
@@ -0,0 +1,132 @@
+###########################################
+## Dockerfile
+##
+## Written: james.stine@okstate.edu 28 January 2023
+## Modified: 
+##
+## Purpose: Dockerfile for Wally docker container creation
+## 
+## A component of the CORE-V-WALLY configurable RISC-V project.
+## 
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org#licenses#SHL-2.1#
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+# Compliance Development Environment Image
+FROM debian
+
+# UPDATE / UPGRADE
+RUN apt update
+
+# INSTALL
+RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam  build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano
+
+RUN pip3 install chardet==3.0.4
+RUN pip3 install urllib3==1.22
+RUN pip3 install testresources
+RUN pip3 install riscof --ignore-installed PyYAML
+RUN echo "root:wally" | chpasswd
+
+# ADD RISCV
+WORKDIR /opt/riscv
+
+# Create a user group 'xyzgroup'
+ARG USERNAME=cad
+ARG USER_UID=1000
+ARG USER_GID=$USER_UID
+
+# Create the user
+RUN groupadd --gid $USER_GID $USERNAME \
+    && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
+    # [Optional] Add sudo support. Omit if you don't need to install software after connecting.
+    && apt-get update \
+    && apt-get install -y sudo \
+    && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
+    && chmod 0440 /etc/sudoers.d/$USERNAME
+
+# Change RISCV user
+run chown -Rf cad:cad /opt
+
+# Add cad user
+USER $USERNAME
+
+# SET ENVIRONMENT VARIABLES
+ENV RISCV=/opt/riscv
+ENV PATH=$PATH:$RISCV/bin
+
+# TOOLCHAIN
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
+    cd riscv-gnu-toolchain && \
+    ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
+    make --jobs && \
+    make install
+
+# elf2hex
+ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+WORKDIR /opt/riscv
+RUN git clone https://github.com/sifive/elf2hex.git && \
+  cd elf2hex && \
+  autoreconf -i && \
+  ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
+  make && \
+  make install
+
+# QEMU
+WORKDIR /opt/riscv
+RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
+  cd qemu && \
+  ./configure --target-list=riscv64-softmmu --prefix=$RISCV  && \
+  make --jobs && \
+  make install
+
+# Spike
+WORKDIR /opt/riscv
+RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
+  mkdir riscv-isa-sim/build && \
+  cd riscv-isa-sim/build && \
+  ../configure --prefix=$RISCV --enable-commitlog && \
+  make --jobs && \
+  make install  && \
+  cd ../arch_test_target/spike/device && \
+  sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
+  sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
+
+# SAIL
+WORKDIR /opt/riscv
+RUN opam init -y --disable-sandboxing
+RUN opam switch create ocaml-base-compiler.4.06.1
+RUN opam install sail -y
+RUN eval $(opam config env) && \
+ cd $RISCV && \
+ git clone https://github.com/riscv/sail-riscv.git && \
+ cd sail-riscv && \
+ make && \
+ ARCH=RV32 make && \
+ ARCH=RV64 make && \
+ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \
+ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
+
+# Buildroot
+WORKDIR /opt/riscv
+RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git
+ENV export WALLY=/opt/riscv/riscv-wally
+RUN git clone https://github.com/buildroot/buildroot.git && \
+  cd buildroot && \
+  git checkout 2021.05 && \
+  cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
+  cp ./board/wally/main.config .config && \
+  make --jobs
+
+# change to cad's hometown
+WORKDIR /home/cad
diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv
index 7b79eb35c..47b3f1fe7 100644
--- a/pipelined/src/generic/mem/ram1p1rwbe.sv
+++ b/pipelined/src/generic/mem/ram1p1rwbe.sv
@@ -49,17 +49,25 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
   // ***************************************************************************
   // TRUE SRAM macro
   // ***************************************************************************
-  if (`USE_SRAM == 1) begin
+ if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin
     genvar index;
-    // 64 x 128-bit SRAM
-    // check if the size is ok, complain if not***
-    logic [WIDTH-1:0] BitWriteMask;
-    for (index=0; index < WIDTH; index++) 
-      assign BitWriteMask[index] = bwe[index/8];
-    TS1N28HPCPSVTB64X128M4SW sram(
-      .CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB(~BitWriteMask), .Q(dout));
+     // 64 x 128-bit SRAM
+     logic [WIDTH-1:0] BitWriteMask;
+     for (index=0; index < WIDTH; index++) 
+       assign BitWriteMask[index] = bwe[index/8];
+    ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+			      .A(addr), .D(din), 
+			      .BWEB(~BitWriteMask), .Q(dout));
+     
+  end else if (`USE_SRAM == 1 && WIDTH == 44  && `XLEN == 64) begin
+     genvar index;
+     // 64 x 44-bit SRAM
+     logic [WIDTH-1:0] BitWriteMask;
+     for (index=0; index < WIDTH; index++) 
+       assign BitWriteMask[index] = bwe[index/8];
+     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+			      .A(addr), .D(din), 
+			      .BWEB(~BitWriteMask), .Q(dout));
     
   // ***************************************************************************
   // READ first SRAM model
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv
new file mode 100755
index 000000000..fa8e32f0b
--- /dev/null
+++ b/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv
@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// ram1p1rwbe_64x128.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram1p1rwbe_64x128( 
+  input  logic          CLK, 
+  input  logic 	        CEB, 
+  input  logic          WEB,
+  input  logic [5:0]    A, 
+  input  logic [127:0]  D,
+  input  logic [127:0]  BWEB, 
+  output logic [127:0]  Q
+);
+
+   // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor
+   generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+
+endmodule
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv
new file mode 100644
index 000000000..7fa71f312
--- /dev/null
+++ b/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv
@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// ram1p1rwbe_64x44.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram1p1rwbe_64x44( 
+  input  logic          CLK, 
+  input  logic 	        CEB, 
+  input  logic          WEB,
+  input  logic [5:0]    A, 
+  input  logic [127:0]  D,
+  input  logic [127:0]  BWEB, 
+  output logic [127:0]  Q
+);
+
+   // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
+   generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+
+endmodule
diff --git a/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv b/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv
new file mode 100755
index 000000000..a287942bd
--- /dev/null
+++ b/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv
@@ -0,0 +1,48 @@
+///////////////////////////////////////////
+// ram2p1rwbe_1024x69.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram2p1rwbe_1024x69( 
+  input  logic          CLKA, 
+  input  logic          CLKB, 
+  input  logic 	        CEBA, 
+  input  logic 	        CEBB, 
+  input  logic          WEBA,
+  input  logic          WEBB,
+  input  logic [9:0]    AA, 
+  input  logic [9:0]    AB, 
+  input  logic [68:0]   DA,
+  input  logic [68:0]   DB,
+  input  logic [68:0]   BWEBA, 
+  input  logic [68:0]   BWEBB, 
+  output logic [68:0]   QA,
+  output logic [68:0]   QB,
+);
+
+   // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
+   generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+
+endmodule
diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/pipelined/src/generic/mem/rom1p1r_128x32.sv
new file mode 100755
index 000000000..89d46b8f1
--- /dev/null
+++ b/pipelined/src/generic/mem/rom1p1r_128x32.sv
@@ -0,0 +1,38 @@
+///////////////////////////////////////////
+// rom1p1r_128x32.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module rom1p1r_128x32( 
+  input  logic          CLK, 
+  input  logic 	        CEB, 
+  input  logic [6:0]    A, 
+  output logic [31:0]   Q
+);
+
+   // replace "generic128x32ROM" with "TS3N..128X32.." module from your memory vendor
+   generic64x128ROM sramIP (.CLK, .CEB, .A, .Q);
+
+endmodule 
+
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index ed43a1ab3..b1342456c 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -30,6 +30,7 @@ eval file copy -force ${cfg} {$outputDir/hdl/}
 #eval file copy -force ${cfg} $outputDir
 eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
+eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/}
 
 # Only for FMA class project; comment out when done

From 8b4c3920dbf872bd9df2cb1f853c3e8852d00067 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Sat, 28 Jan 2023 19:46:43 -0600
Subject: [PATCH 65/84] Update Appendix D + wrapped memories

---
 addins/docker/Dockerfile | 107 ---------------------------------------
 addins/docker/README.md  |  48 ------------------
 2 files changed, 155 deletions(-)
 delete mode 100755 addins/docker/Dockerfile
 delete mode 100644 addins/docker/README.md

diff --git a/addins/docker/Dockerfile b/addins/docker/Dockerfile
deleted file mode 100755
index e06fa039d..000000000
--- a/addins/docker/Dockerfile
+++ /dev/null
@@ -1,107 +0,0 @@
-# Compliance Development Environment Image
-FROM debian
-
-# UPDATE / UPGRADE
-RUN apt update
-
-# INSTALL
-RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam  build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano
-
-RUN pip3 install chardet==3.0.4
-RUN pip3 install urllib3==1.22
-RUN pip3 install testresources
-RUN pip3 install riscof --ignore-installed PyYAML
-RUN echo "root:wally" | chpasswd
-
-# ADD RISCV
-WORKDIR /opt/riscv
-
-# Create a user group 'xyzgroup'
-ARG USERNAME=cad
-ARG USER_UID=1000
-ARG USER_GID=$USER_UID
-
-# Create the user
-RUN groupadd --gid $USER_GID $USERNAME \
-    && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
-    # [Optional] Add sudo support. Omit if you don't need to install software after connecting.
-    && apt-get update \
-    && apt-get install -y sudo \
-    && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
-    && chmod 0440 /etc/sudoers.d/$USERNAME
-
-# Change RISCV user
-run chown -Rf cad:cad /opt
-
-# Add cad user
-USER $USERNAME
-
-# SET ENVIRONMENT VARIABLES
-ENV RISCV=/opt/riscv
-ENV PATH=$PATH:$RISCV/bin
-
-# TOOLCHAIN
-RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
-    cd riscv-gnu-toolchain && \
-    ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
-    make --jobs && \
-    make install
-
-# elf2hex
-ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
-WORKDIR /opt/riscv
-RUN git clone https://github.com/sifive/elf2hex.git && \
-  cd elf2hex && \
-  autoreconf -i && \
-  ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
-  make && \
-  make install
-
-# QEMU
-WORKDIR /opt/riscv
-RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
-  cd qemu && \
-  ./configure --target-list=riscv64-softmmu --prefix=$RISCV  && \
-  make --jobs && \
-  make install
-
-# Spike
-WORKDIR /opt/riscv
-RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
-  mkdir riscv-isa-sim/build && \
-  cd riscv-isa-sim/build && \
-  ../configure --prefix=$RISCV --enable-commitlog && \
-  make --jobs && \
-  make install  && \
-  cd ../arch_test_target/spike/device && \
-  sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
-  sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
-
-# SAIL
-WORKDIR /opt/riscv
-RUN opam init -y --disable-sandboxing
-RUN opam switch create ocaml-base-compiler.4.06.1
-RUN opam install sail -y
-RUN eval $(opam config env) && \
- cd $RISCV && \
- git clone https://github.com/riscv/sail-riscv.git && \
- cd sail-riscv && \
- make && \
- ARCH=RV32 make && \
- ARCH=RV64 make && \
- ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \
- ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
-
-# Buildroot
-WORKDIR /opt/riscv
-RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git
-ENV export WALLY=/opt/riscv/riscv-wally
-RUN git clone https://github.com/buildroot/buildroot.git && \
-  cd buildroot && \
-  git checkout 2021.05 && \
-  cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
-  cp ./board/wally/main.config .config && \
-  make --jobs
-
-# change to cad's hometown
-WORKDIR /home/cad
diff --git a/addins/docker/README.md b/addins/docker/README.md
deleted file mode 100644
index 135c7e744..000000000
--- a/addins/docker/README.md
+++ /dev/null
@@ -1,48 +0,0 @@
-Installing Wally, RISC-V tools, and Imperas tests from source gives you maximum control, but has several disadvantages:
-
--Building the executables takes several hours.
--Linux is poorly standardized, and the build steps might not work on your version
--The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
-
-Docker is a tools to run applications in a prepackaged container
-including all of the operating system support required.  Wally offers
-a ~30GB container image with the open-source tools pre-installed from
-Section D.1. In particular, using the container solves the long build
-time for gcc and the fussy installation of sail. The container runs on
-any platform supporting Docker, including Windows and Mac as well as
-Linux.  It can access files outside the container, including local
-installation of CAD tools such as Questa, and a local clone of the
-core-v-wally repository.
-
-Docker can be run on most operating systems, including Linux, Windows,
-and Mac. The Wally Docker container is hosted at DockerHub
-(http://docker.io).
-
-Podman is a more secure and easier-to-use variation of Docker for
-Linux developed by RedHat.  Both Docker and Podman run the same
-containers.
-
-This directory has a copy of the file utilized to create the Docker
-for the toolchain discussed in the text. To build this docker, you can
-type the following where the last argument is the name where you want
-to store your docker.
-
-docker build -t docker.io/wallysoc/wally-docker:latest .
-
-This can also be changed if you make a mistake by using the tag
-command.  For example, if I wanted to change my docker from
-wally-docker to wally-docker2, I would type:
-
-docker tag wallysoc/wally-docker:latest docker.io/wallysoc/wally-docker2:latest
-
-Once you build your docker, you can run it as given in the Readme.
-However, you can also push it to DockerHub with the following command.
-
-docker push docker.io/wallysoc/wally-docker:latest
-
-To run your docker, you can type the following at a command prompt or
-terminal.
-
-docker run -it -p 8080:8080 docker.io/wallysoc/wally-docker
-
-

From c73fe4041e9647d03071fd3717fa8e37b763213c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 18:07:33 -0800
Subject: [PATCH 66/84] Fixed typo in ram2p1r1wbe_1024x69 and renamed for
 consistency

---
 .../mem/{ram2p1rwbe_1024x69.sv => ram2p1r1wbe_1024x69.sv}     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 rename pipelined/src/generic/mem/{ram2p1rwbe_1024x69.sv => ram2p1r1wbe_1024x69.sv} (96%)

diff --git a/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv
similarity index 96%
rename from pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv
rename to pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv
index a287942bd..4437c09bf 100755
--- a/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv
+++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv
@@ -24,7 +24,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ram2p1rwbe_1024x69( 
+module ram2p1r1wbe_1024x69( 
   input  logic          CLKA, 
   input  logic          CLKB, 
   input  logic 	        CEBA, 
@@ -38,7 +38,7 @@ module ram2p1rwbe_1024x69(
   input  logic [68:0]   BWEBA, 
   input  logic [68:0]   BWEBB, 
   output logic [68:0]   QA,
-  output logic [68:0]   QB,
+  output logic [68:0]   QB
 );
 
    // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor

From 8a96dcf0ae61fc6aa1d815051372134fd0ff67a6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 18:17:42 -0800
Subject: [PATCH 67/84] Config cleanup and renamed BPRED_ENABLED to
 BPRED_SUPPORTED

---
 pipelined/config/buildroot/wally-config.vh  | 2 +-
 pipelined/config/fpga/wally-config.vh       | 4 ++--
 pipelined/config/rv32e/wally-config.vh      | 4 ++--
 pipelined/config/rv32gc/wally-config.vh     | 4 ++--
 pipelined/config/rv32i/wally-config.vh      | 6 +++---
 pipelined/config/rv32ic/wally-config.vh     | 4 ++--
 pipelined/config/rv64fpquad/wally-config.vh | 4 ++--
 pipelined/config/rv64gc/wally-config.vh     | 2 +-
 pipelined/config/rv64i/wally-config.vh      | 4 ++--
 pipelined/src/ifu/ifu.sv                    | 2 +-
 pipelined/src/wally/cvw.sv                  | 2 +-
 pipelined/testbench/testbench.sv            | 2 +-
 pipelined/testbench/testbench_imperas.sv    | 2 +-
 13 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index a4ec7fb47..ccad97cb6 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -128,7 +128,7 @@
 `define PLIC_UART_ID 10
 `define PLIC_GPIO_ID 3
 
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 56bf10402..ddbb18c0b 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -71,7 +71,7 @@
 `define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
+`define PMP_ENTRIES 16
 
 // Address space
 `define RESET_VECTOR 64'h0000000000001000
@@ -139,7 +139,7 @@
 
 `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 1
 `define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define TESTSBP 1
 `define BPRED_SIZE 10
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index b42633679..c81faeb85 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -69,7 +69,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 1
-`define IDIV_ON_FPU 1
+`define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 0
@@ -132,7 +132,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 0
+`define BPRED_SUPPORTED 0
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 2704a9a00..94d56d835 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -68,7 +68,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
+`define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 16
@@ -131,7 +131,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 119354aa8..80a4773d8 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -69,10 +69,10 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
+`define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
+`define PMP_ENTRIES 0
 
 // Address space
 `define RESET_VECTOR 32'h80000000
@@ -132,7 +132,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 0
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index 49281c289..eb6627624 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -68,7 +68,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
+`define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 0
@@ -131,7 +131,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 0
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index 4d36ff303..2570ff1df 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -72,7 +72,7 @@
 `define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
+`define PMP_ENTRIES 16
 
 // Address space
 `define RESET_VECTOR 64'h0000000080000000
@@ -134,7 +134,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index c00e02843..bdef122ff 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -134,7 +134,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 1
+`define BPRED_SUPPORTED 1
 //`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 //`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index b0df9bc30..bb7b71c0e 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -69,7 +69,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
+`define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 0
@@ -134,7 +134,7 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define BPRED_ENABLED 0
+`define BPRED_SUPPORTED 0
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 0ff6dc3f9..0010403a7 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -322,7 +322,7 @@ module ifu (
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // Branch and Jump Predictor
   ////////////////////////////////////////////////////////////////////////////////////////////////
-  if (`BPRED_ENABLED) begin : bpred
+  if (`BPRED_SUPPORTED) begin : bpred
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW,
diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv
index 5fd28163e..66512e947 100644
--- a/pipelined/src/wally/cvw.sv
+++ b/pipelined/src/wally/cvw.sv
@@ -99,7 +99,7 @@ package cvw;
 //  parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32;
   parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
   parameter PLIC_UART_ID = `PLIC_UART_ID;
-  parameter BPRED_ENABLED = `BPRED_ENABLED;
+  parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
   parameter BPTYPE = `BPTYPE;
   parameter TESTSBP = `TESTSBP;
   parameter BPRED_SIZE = `BPRED_SIZE;
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index fbd720109..2bbe1d113 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -465,7 +465,7 @@ logic [3:0] dummy;
 		    	.done(DCacheFlushDone));
 
   // initialize the branch predictor
-  if (`BPRED_ENABLED == 1)
+  if (`BPRED_SUPPORTED == 1)
     begin
       genvar adrindex;
       
diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv
index 6e84e879b..7e472a99b 100644
--- a/pipelined/testbench/testbench_imperas.sv
+++ b/pipelined/testbench/testbench_imperas.sv
@@ -219,7 +219,7 @@ module testbench;
 		    	.done(DCacheFlushDone));
 
   // initialize the branch predictor
-  if (`BPRED_ENABLED == 1)
+  if (`BPRED_SUPPORTED == 1)
     begin
       genvar adrindex;
       

From fa3643a0643d058a2eda96630d69cb4287af0d69 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 18:35:53 -0800
Subject: [PATCH 68/84] Renamed BUS to BUS_SUPPORTED

---
 pipelined/config/buildroot/wally-config.vh  | 2 +-
 pipelined/config/fpga/wally-config.vh       | 2 +-
 pipelined/config/rv32e/wally-config.vh      | 2 +-
 pipelined/config/rv32gc/wally-config.vh     | 2 +-
 pipelined/config/rv32i/wally-config.vh      | 2 +-
 pipelined/config/rv32ic/wally-config.vh     | 2 +-
 pipelined/config/rv64fpquad/wally-config.vh | 2 +-
 pipelined/config/rv64gc/wally-config.vh     | 2 +-
 pipelined/config/rv64i/wally-config.vh      | 2 +-
 pipelined/src/ifu/ifu.sv                    | 2 +-
 pipelined/src/lsu/lsu.sv                    | 4 ++--
 pipelined/src/wally/cvw.sv                  | 2 +-
 pipelined/src/wally/wallypipelinedcore.sv   | 2 +-
 pipelined/src/wally/wallypipelinedsoc.sv    | 2 +-
 pipelined/testbench/testbench.sv            | 4 ++--
 pipelined/testbench/testbench_imperas.sv    | 6 +++---
 16 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index ccad97cb6..4ef61acf1 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -44,7 +44,7 @@
 `define COUNTERS 32
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index ddbb18c0b..ca5261cfe 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -45,7 +45,7 @@
 `define COUNTERS 32
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index c81faeb85..8a1bc54e3 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -46,7 +46,7 @@
 `define ZFH_SUPPORTED 0
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 0
 `define ICACHE 0
 `define VIRTMEM_SUPPORTED 0
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 94d56d835..e18c99b64 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -45,7 +45,7 @@
 `define ZFH_SUPPORTED 0
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 80a4773d8..23fa30fa2 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -46,7 +46,7 @@
 `define ZFH_SUPPORTED 0
 
 // LSU microarchitectural Features
-`define BUS 0
+`define BUS_SUPPORTED 0
 `define DCACHE 0
 `define ICACHE 0
 `define VIRTMEM_SUPPORTED 0
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index eb6627624..7f210ee88 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -45,7 +45,7 @@
 `define ZFH_SUPPORTED 0
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 0
 `define ICACHE 0
 `define VIRTMEM_SUPPORTED 0
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index 2570ff1df..6072ea459 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -46,7 +46,7 @@
 `define ZFH_SUPPORTED 1
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index bdef122ff..c24f4538c 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -46,7 +46,7 @@
 `define ZFH_SUPPORTED 0
 
 // LSU microarchitectural Features
-`define BUS 1
+`define BUS_SUPPORTED 1
 `define DCACHE 1
 `define ICACHE 1
 `define VIRTMEM_SUPPORTED 1
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index bb7b71c0e..2f01f50c9 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -46,7 +46,7 @@
 `define ZFH_SUPPORTED 0
 
 // LSU microarchitectural Features
-`define BUS 0
+`define BUS_SUPPORTED 0
 `define DCACHE 0
 `define ICACHE 0
 `define VIRTMEM_SUPPORTED 0
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 0010403a7..ee0745875 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -208,7 +208,7 @@ module ifu (
   end else begin
     assign IFURWF = 2'b10;
   end
-  if (`BUS) begin : bus
+  if (`BUS_SUPPORTED) begin : bus
     // **** must fix words per line vs beats per line as in lsu.
     localparam   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
     localparam   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 19f5ba960..c28dc5006 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -206,7 +206,7 @@ module lsu (
     assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
     assign PAdrM = IHAdrM[`PA_BITS-1:0];
     assign CacheableM = 1'b1;
-    assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM.  If there is 
+    assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM.  If there is 
     // a bus then this is always 0. Cannot have both without PMA.
   end
   
@@ -236,7 +236,7 @@ module lsu (
               .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
   end else begin
   end
-  if (`BUS) begin : bus              
+  if (`BUS_SUPPORTED) begin : bus              
     if(`DCACHE) begin : dcache
       localparam   LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN;             // Number of LLEN words in cacheline
       localparam   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                     // Log2 of ^
diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv
index 66512e947..5aa6d2321 100644
--- a/pipelined/src/wally/cvw.sv
+++ b/pipelined/src/wally/cvw.sv
@@ -43,7 +43,7 @@ package cvw;
   parameter COUNTERS = `COUNTERS;
   parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
   parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
-  parameter BUS = `BUS;
+  parameter BUS_SUPPORTED = `BUS_SUPPORTED;
   parameter DCACHE = `DCACHE;
   parameter ICACHE = `ICACHE;
   parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 5c2c6efce..b50746477 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -237,7 +237,7 @@ module wallypipelinedcore (
     .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
     .LSUStallM);                    
 
-  if(BUS) begin : ebu
+  if(BUS_SUPPORTED) begin : ebu
     ebu ebu(// IFU connections
       .clk, .reset,
       // IFU interface
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv
index 26979545c..e792f6f89 100644
--- a/pipelined/src/wally/wallypipelinedsoc.sv
+++ b/pipelined/src/wally/wallypipelinedsoc.sv
@@ -80,7 +80,7 @@ module wallypipelinedsoc (
    );
 
   // instantiate uncore if a bus interface exists
-  if (BUS) begin : uncore
+  if (BUS_SUPPORTED) begin : uncore
     uncore uncore(.HCLK, .HRESETn, .TIMECLK,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 2bbe1d113..6d0eec950 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -246,7 +246,7 @@ logic [3:0] dummy;
         force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       end else begin
         if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-        else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+        else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
         if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
       end
 
@@ -545,7 +545,7 @@ module riscvassertions;
     assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
     assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
     assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
+    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
     assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv
index 7e472a99b..1bd5d45c0 100644
--- a/pipelined/testbench/testbench_imperas.sv
+++ b/pipelined/testbench/testbench_imperas.sv
@@ -100,8 +100,8 @@ module testbench;
 	  pathname = "../../tests/riscof/work/wally-riscv-arch-test/";
 	  
 	  memfilename = {pathname, testName, "/ref/ref.elf.memfile"};
-      if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-	  else $error("Imperas test bench requires BUS.");
+      if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+	  else $error("Imperas test bench requires BUS_SUPPORTED.");
 
       ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"};
@@ -287,7 +287,7 @@ module riscvassertions;
     assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
     assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
     assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
+    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS.");
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
     assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");

From b89fe9989ec3c91d2adb1cb966c6db491aa58f23 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 18:52:00 -0800
Subject: [PATCH 69/84] Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to
 ICACHE_SUPPORTED

---
 pipelined/config/buildroot/wally-config.vh  |  4 +--
 pipelined/config/fpga/wally-config.vh       |  4 +--
 pipelined/config/rv32e/wally-config.vh      |  4 +--
 pipelined/config/rv32gc/wally-config.vh     |  4 +--
 pipelined/config/rv32i/wally-config.vh      |  4 +--
 pipelined/config/rv32ic/wally-config.vh     |  4 +--
 pipelined/config/rv64fpquad/wally-config.vh |  4 +--
 pipelined/config/rv64gc/wally-config.vh     |  4 +--
 pipelined/config/rv64i/wally-config.vh      |  4 +--
 pipelined/src/ieu/controller.sv             |  4 +--
 pipelined/src/ifu/ifu.sv                    | 10 +++----
 pipelined/src/lsu/lsu.sv                    |  2 +-
 pipelined/src/wally/cvw.sv                  |  4 +--
 pipelined/testbench/testbench.sv            | 32 ++++++++++-----------
 pipelined/testbench/testbench_imperas.sv    | 18 ++++++------
 15 files changed, 53 insertions(+), 53 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index 4ef61acf1..bb687da51 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -45,8 +45,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 1
-`define ICACHE 1
+`define DCACHE_SUPPORTED 1
+`define ICACHE_SUPPORTED 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index ca5261cfe..a57f98a08 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -46,8 +46,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 1
-`define ICACHE 1
+`define DCACHE_SUPPORTED 1
+`define ICACHE_SUPPORTED 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index 8a1bc54e3..66cec123b 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -47,8 +47,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 0
-`define ICACHE 0
+`define DCACHE_SUPPORTED 0
+`define ICACHE_SUPPORTED 0
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 0 
 `define BIGENDIAN_SUPPORTED 0
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index e18c99b64..b420894ea 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -46,8 +46,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 1
-`define ICACHE 1
+`define DCACHE_SUPPORTED 1
+`define ICACHE_SUPPORTED 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 1
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 23fa30fa2..8f9e9dd06 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -47,8 +47,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 0
-`define DCACHE 0
-`define ICACHE 0
+`define DCACHE_SUPPORTED 0
+`define ICACHE_SUPPORTED 0
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 1
 `define BIGENDIAN_SUPPORTED 0
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index 7f210ee88..bdb0d4f42 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -46,8 +46,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 0
-`define ICACHE 0
+`define DCACHE_SUPPORTED 0
+`define ICACHE_SUPPORTED 0
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 0
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index 6072ea459..f92abcb5c 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -47,8 +47,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 1
-`define ICACHE 1
+`define DCACHE_SUPPORTED 1
+`define ICACHE_SUPPORTED 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 1
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index c24f4538c..dcdda74f4 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -47,8 +47,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
-`define DCACHE 1
-`define ICACHE 1
+`define DCACHE_SUPPORTED 1
+`define ICACHE_SUPPORTED 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 1
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index 2f01f50c9..d35e21632 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -47,8 +47,8 @@
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 0
-`define DCACHE 0
-`define ICACHE 0
+`define DCACHE_SUPPORTED 0
+`define ICACHE_SUPPORTED 0
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 `define BIGENDIAN_SUPPORTED 0
diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv
index e875c99fa..1819de17c 100644
--- a/pipelined/src/ieu/controller.sv
+++ b/pipelined/src/ieu/controller.sv
@@ -200,7 +200,7 @@ module controller(
   // Fences
   // Ordinary fence is presently a nop
   // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
-  if (`ZIFENCEI_SUPPORTED & `ICACHE) begin:fencei
+  if (`ZIFENCEI_SUPPORTED & `ICACHE_SUPPORTED) begin:fencei
     logic FenceID;
     assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
     assign InvalidateICacheD = FenceID;
@@ -249,5 +249,5 @@ module controller(
 
   // the synchronous DTIM cannot read immediately after write
   // a cache cannot read or write immediately after a write
-  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD));
+  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD));
 endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index ee0745875..3e3e59743 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -134,7 +134,7 @@ module ifu (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if(`C_SUPPORTED) begin : Spill
-    spill #(`ICACHE) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
+    spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
       .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpill
     assign PCNextFSpill = PCNextF;
@@ -210,10 +210,10 @@ module ifu (
   end
   if (`BUS_SUPPORTED) begin : bus
     // **** must fix words per line vs beats per line as in lsu.
-    localparam   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
-    localparam   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
-    if(`ICACHE) begin : icache
-      localparam           LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
+    localparam   WORDSPERLINE = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS/`XLEN : 1;
+    localparam   LOGBWPL = `ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
+    if(`ICACHE_SUPPORTED) begin : icache
+      localparam           LINELEN = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS : `XLEN;
       localparam           LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
       logic [LINELEN-1:0]  FetchBuffer;
       logic [`PA_BITS-1:0] ICacheBusAdr;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index c28dc5006..2eb8df1e5 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -237,7 +237,7 @@ module lsu (
   end else begin
   end
   if (`BUS_SUPPORTED) begin : bus              
-    if(`DCACHE) begin : dcache
+    if(`DCACHE_SUPPORTED) begin : dcache
       localparam   LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN;             // Number of LLEN words in cacheline
       localparam   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                     // Log2 of ^
       localparam   BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW;                 // Number of AHBW words (beats) in cacheline
diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv
index 5aa6d2321..3c32ae05a 100644
--- a/pipelined/src/wally/cvw.sv
+++ b/pipelined/src/wally/cvw.sv
@@ -44,8 +44,8 @@ package cvw;
   parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
   parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
   parameter BUS_SUPPORTED = `BUS_SUPPORTED;
-  parameter DCACHE = `DCACHE;
-  parameter ICACHE = `ICACHE;
+  parameter DCACHE_SUPPORTED = `DCACHE_SUPPORTED;
+  parameter ICACHE_SUPPORTED = `ICACHE_SUPPORTED;
   parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
   parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED;
   parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED;
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 6d0eec950..73b6c1845 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -523,19 +523,19 @@ module riscvassertions;
     assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
     assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
     assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
-    assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
+    assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
     assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
-    assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
-    assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
+    assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
     assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
-    assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
     assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
-    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
     assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
     assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
     assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
@@ -543,12 +543,12 @@ module riscvassertions;
     assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
     assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
     assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
-    assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
-    assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
-    assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
+    assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
+    assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
-    assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
+    assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
     assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
   end
 
@@ -569,7 +569,7 @@ module DCacheFlushFSM
 
   logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
   
-	if(`DCACHE) begin
+	if(`DCACHE_SUPPORTED) begin
 	  localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
 	  localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
 	  localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv
index 1bd5d45c0..bc65a3c5b 100644
--- a/pipelined/testbench/testbench_imperas.sv
+++ b/pipelined/testbench/testbench_imperas.sv
@@ -265,14 +265,14 @@ module riscvassertions;
     assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
     assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
     assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
-    assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
+    assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
     assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
     assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
-    assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACH_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
     assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
-    assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
     assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
     assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
     assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
@@ -285,12 +285,12 @@ module riscvassertions;
     assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
     assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
     assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
-    assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
-    assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS.");
+    assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS.");
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
-    assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
+    assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
     assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
   end
 

From 799caef2c9551b1beb36757a14f73fe0013d3f92 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 20:06:12 -0800
Subject: [PATCH 70/84] Renamed BPTYPE to BPRED_TYPE

---
 pipelined/config/buildroot/wally-config.vh  |  2 +-
 pipelined/config/fpga/wally-config.vh       |  2 +-
 pipelined/config/rv32e/wally-config.vh      |  2 +-
 pipelined/config/rv32gc/wally-config.vh     |  2 +-
 pipelined/config/rv32i/wally-config.vh      |  2 +-
 pipelined/config/rv32ic/wally-config.vh     |  2 +-
 pipelined/config/rv64fpquad/wally-config.vh |  2 +-
 pipelined/config/rv64gc/wally-config.vh     |  6 +++---
 pipelined/config/rv64i/wally-config.vh      |  2 +-
 pipelined/src/ifu/bpred/bpred.sv            | 12 ++++++------
 pipelined/src/wally/cvw.sv                  |  3 +--
 11 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index bb687da51..f34874dc3 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -129,7 +129,7 @@
 `define PLIC_GPIO_ID 3
 
 `define BPRED_SUPPORTED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index a57f98a08..3612185e0 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -140,7 +140,7 @@
 `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
 `define BPRED_SUPPORTED 1
-`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define TESTSBP 1
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index 66cec123b..84082fdc8 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index b420894ea..ef98b0028 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -132,7 +132,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 8f9e9dd06..1cc0c5b32 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index bdb0d4f42..a80c00e38 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -132,7 +132,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index f92abcb5c..649956fbe 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -135,7 +135,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index dcdda74f4..01b245b3d 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -135,9 +135,9 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+//`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+//`define BPRED_TYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index d35e21632..b4621d31d 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -135,7 +135,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
index 0319d3a08..22889bb3d 100644
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@@ -81,34 +81,34 @@ module bpred (
   
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
-  if (`BPTYPE == "BPTWOBIT") begin:Predictor
+  if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
     twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
-  end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
+  end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
     globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
-  end else if (`BPTYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
+  end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
     speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .BranchInstrW(InstrClassW[0]), .PCSrcE);
     
-  end else if (`BPTYPE == "BPGSHARE") begin:Predictor
+  end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
     gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
-  end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
+  end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
     speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
 
-  end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
+  end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
 /* -----\/----- EXCLUDED -----\/-----
     localHistoryPredictor DirPredictor(.clk,
diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv
index 3c32ae05a..0a804c9a3 100644
--- a/pipelined/src/wally/cvw.sv
+++ b/pipelined/src/wally/cvw.sv
@@ -96,11 +96,10 @@ package cvw;
   parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST;
   parameter UART_PRESCALE = `UART_PRESCALE;
   parameter PLIC_NUM_SRC = `PLIC_NUM_SRC;
-//  parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32;
   parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
   parameter PLIC_UART_ID = `PLIC_UART_ID;
   parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
-  parameter BPTYPE = `BPTYPE;
+  parameter BPRED_TYPE = `BPRED_TYPE;
   parameter TESTSBP = `TESTSBP;
   parameter BPRED_SIZE = `BPRED_SIZE;
   parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED;

From 0f13941d3b7a40ca580f54ae4678a31f752f149c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 28 Jan 2023 20:22:36 -0800
Subject: [PATCH 71/84] Removed unused BPRED file referenes from fpga config

---
 pipelined/config/fpga/wally-config.vh | 2 --
 1 file changed, 2 deletions(-)

diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 3612185e0..d23ef9684 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -137,8 +137,6 @@
 `define PLIC_UART_ID 10
 `define PLIC_GPIO_ID 3
 
-`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define TESTSBP 1

From 9e3074689d161a6e83210795ccbeeb9344fbc94a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 00:33:40 -0600
Subject: [PATCH 72/84] Fixed another bug with the speculative gshare with
 instruction class prediction.

---
 pipelined/regression/wave.do                  | 6 ++++--
 pipelined/src/ifu/brpred/speculativegshare.sv | 4 ++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index cdae10c6b..a17bc502e 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -584,6 +584,8 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
 add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM
 add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
 add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
 add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
@@ -625,7 +627,7 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Fl
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF
 add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {217131 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {296884 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -641,4 +643,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {135840 ns} {362253 ns}
+WaveRestoreZoom {18545889 ns} {18546113 ns}
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 7760cbef9..6cfb56894 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -112,7 +112,7 @@ module speculativegshare
   //                  GHRF;
 
   always_comb begin
-	if(FlushD) begin
+	if(FlushD | DirPredictionWrongE) begin
 	  GHRNextF = GHRNextD[k-1:0];
 	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
 	else GHRNextF = GHRF;
@@ -124,7 +124,7 @@ module speculativegshare
   // use with out instruction class prediction
   //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
   // with instruction class prediction
-  assign GHRNextD = FlushD ? GHRNextE[k-1:0] :
+  assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
 					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
   					WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}:       // shift left
 					GHRF[k-1:0];

From c8df460b2842f098a1215ce72599f5391108a967 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 00:49:23 -0600
Subject: [PATCH 73/84] Fixed bug with the btb's valid bit not beind held on a
 stall.

---
 pipelined/src/ifu/brpred/btb.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 20500226a..b8c5c6bcd 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -94,7 +94,7 @@ module btb
     end else if ((UpdateEn) & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
-	TablePredValidF = ValidBits[PCNextFIndex];
+	if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
   end
 
   assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;

From 250a8df7c3112bc5e6f3aad30711f9fe8c02bb5b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 00:56:11 -0600
Subject: [PATCH 74/84] Updated testbench for branch logger.

---
 pipelined/testbench/testbench.sv | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 1e373de57..1c2fbb1f0 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -32,8 +32,8 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
+`define PrintHPMCounters 1
+`define BPRED_LOGGER 1
 
 module testbench;
   parameter DEBUG=0;
@@ -484,11 +484,13 @@ logic [3:0] dummy;
       if (`BPRED_LOGGER) begin
         string direction;
         int    file;
+		logic  PCScrM;
+		flopenrc #(1) PCSrcMReg(clk, reset, FlushM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
         initial
           file = $fopen("branch.log", "w");
         always @(posedge clk) begin
            if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-             direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n";
+             direction = PCSrcM ? "t" : "n";
              $fwrite(file, "%h %s\n", dut.core.PCM, direction);
            end
         end

From 6afd7f4fac3b43d2e43ae5c106b6d1ff39321a0d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 00:58:50 -0600
Subject: [PATCH 75/84] Fixed bug in the branch logger.

---
 pipelined/testbench/testbench.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 1c2fbb1f0..1acb8f6a4 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -485,7 +485,7 @@ logic [3:0] dummy;
         string direction;
         int    file;
 		logic  PCScrM;
-		flopenrc #(1) PCSrcMReg(clk, reset, FlushM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
+		flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
         initial
           file = $fopen("branch.log", "w");
         always @(posedge clk) begin

From 5c83de4c463290cf919ea9aef8714f1abfb97194 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 00:59:59 -0600
Subject: [PATCH 76/84] Fixed another bug with the branch logger.

---
 pipelined/testbench/testbench.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 1acb8f6a4..8d974f0c0 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -485,7 +485,7 @@ logic [3:0] dummy;
         string direction;
         int    file;
 		logic  PCScrM;
-		flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
+		flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
         initial
           file = $fopen("branch.log", "w");
         always @(posedge clk) begin

From 49a7d10914309c6c2bff0599916ac5809b89b280 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 01:00:52 -0600
Subject: [PATCH 77/84] Fixed typo in testbench branch logger.

---
 pipelined/testbench/testbench.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 8d974f0c0..fd83c79b1 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -484,7 +484,7 @@ logic [3:0] dummy;
       if (`BPRED_LOGGER) begin
         string direction;
         int    file;
-		logic  PCScrM;
+		logic  PCSrcM;
 		flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
         initial
           file = $fopen("branch.log", "w");

From 5fb3a669b15a52d84ea73ac4b2c21e740b064294 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 14:17:45 -0600
Subject: [PATCH 78/84] Updated benchmark parsing script.

---
 bin/parseHPMC.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 00dcb308c..35bb9c82e 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -45,7 +45,7 @@ def ComputeBranchTargetMissRate(benchmark):
     'Computes and inserts branch target miss prediction rate.'
     # *** this is wrong in the verilog test bench
     (nameString, opt, dataDict) = benchmark
-    branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, ret']) + int(dataDict['ret']))
+    branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, Jal']) + int(dataDict['ret']))
     dataDict['BTMR'] = branchTargetMissRate
 
 def ComputeRASMissRate(benchmark):

From 244885d3fab49b4e81ac04eb562812116c7fa345 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 15:03:25 -0600
Subject: [PATCH 79/84] Found bug in gshare.

---
 pipelined/config/rv32gc/wally-config.vh       | 3 ++-
 pipelined/src/ifu/brpred/bpred.sv             | 2 +-
 pipelined/src/ifu/brpred/speculativegshare.sv | 9 +++------
 pipelined/testbench/testbench.sv              | 6 +++---
 4 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 4d346e5a6..1a1bec35c 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -132,7 +132,8 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_ENABLED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 639dbcd50..497d59876 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 0
+`define INSTR_CLASS_PRED 1
 
 module bpred (
    input logic              clk, reset,
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 6cfb56894..c41282d59 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -51,16 +51,15 @@ module speculativegshare
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
-  logic [k-1:0]            GHRF, OldGHRF;
+  logic [k-1:0]            GHRF;
   logic 				   GHRExtraF;
-  logic [k-1:0] 		   GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0] 		   GHRD, GHRE, GHRM, GHRW;
   logic [k-1:0] 		   GHRNextF;
   logic [k-1:0] 		   GHRNextD;
   logic [k-1:0] 		   GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE;
   
-  logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
@@ -126,7 +125,7 @@ module speculativegshare
   // with instruction class prediction
   assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
 					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
-  					WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}:       // shift left
+  					WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}:       // shift left
 					GHRF[k-1:0];
 
   flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
@@ -144,6 +143,4 @@ module speculativegshare
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
 endmodule
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index fd83c79b1..db36d9379 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -32,8 +32,8 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 1
-`define BPRED_LOGGER 1
+`define PrintHPMCounters 0
+`define BPRED_LOGGER 0
 
 module testbench;
   parameter DEBUG=0;
@@ -408,7 +408,7 @@ logic [3:0] dummy;
     end // always @ (negedge clk)
 
 
-  if(`PrintHPMCounters) begin
+  if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin
     integer HPMCindex;
     string  HPMCnames[] = '{"Mcycle",
                             "------",

From 2a336cfb715faf5002e6da3c172b2a98f5e17a23 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 15:06:35 -0600
Subject: [PATCH 80/84] Gshare cleanup.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index c41282d59..e38561fb1 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -106,7 +106,7 @@ module speculativegshare
 
   // GHR pipeline
   // this version fails the regression test do to pessimistic x propagation.
-  // assign GHRNextF = FlushD ?  (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) :
+  // assign GHRNextF = FlushD | DirPredictionWrongE ?  GHRNextD[k-1:0] :
   //                  BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
   //                  GHRF;
 

From 7c8b2b685ff0f2d743f0fd845ca8b283c651b8cb Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 15:07:45 -0600
Subject: [PATCH 81/84] gshare cleanup.

---
 pipelined/src/ifu/brpred/speculativegshare.sv | 1 -
 1 file changed, 1 deletion(-)

diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index e38561fb1..7f696c452 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -35,7 +35,6 @@ module speculativegshare
    input logic             reset,
    input logic             StallF, StallD, StallE, StallM, StallW, 
    input logic             FlushD, FlushE, FlushM, FlushW,
-//   input logic [`XLEN-1:0] LookUpPC,
    output logic [1:0]      DirPredictionF, 
    output logic            DirPredictionWrongE,
    // update

From dd9d2be89cf3e670f3c4574cacd1bc7a867c6f0d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 16:26:44 -0600
Subject: [PATCH 82/84] Updated global history branch predictcor with the
 gshare improvements.

---
 pipelined/src/ifu/bpred/bpred.sv              | 21 ++-----
 .../src/ifu/bpred/speculativeglobalhistory.sv | 61 +++++++++++--------
 2 files changed, 42 insertions(+), 40 deletions(-)

diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
index bdb489245..cccbe29f0 100644
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@@ -85,41 +85,37 @@ module bpred (
   logic [3:0] 				WrongPredInstrClassD;
 
 
-//************ new resolve issues  
   logic BTBTargetWrongE;
   logic RASTargetWrongE;
   logic JumpOrTakenBranchE;
-  
-  
 
   logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
 
-
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
   if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
-    twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+    twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
-    globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+    globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
-    speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+    speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
 	    
   end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
-    gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+    gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
-    speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
@@ -139,7 +135,6 @@ module bpred (
  -----/\----- EXCLUDED -----/\----- */
   end 
 
-
   // this predictor will have two pieces of data,
   // 1) A direction (1 = Taken, 0 = Not Taken)
   // 2) Any information which is necessary for the predictor to build its next state.
@@ -260,7 +255,6 @@ module bpred (
   // branch class prediction wrong.
   assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
   
-  
   // Selects the BP or PC+2/4.
   mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
   // If the prediction is wrong select the correct address.
@@ -292,8 +286,5 @@ module bpred (
 
   flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
   flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
-
-  
-  
   
 endmodule
diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
index 47203dbdd..3ed9ba3e5 100644
--- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// globalHistoryPredictor.sv
+// speculativeglobalhistory.sv
 //
 // Written: Shreya Sanghai
 // Email: ssanghai@hmc.edu
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-module speculativeglobalhistory #(parameter k = 10) (
+module speculativeglobalhistory #(parameter int k = 10 ) (
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW, 
@@ -36,7 +36,6 @@ module speculativeglobalhistory #(parameter k = 10) (
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
   input logic [3:0]       WrongPredInstrClassD, 
   input logic             PCSrcE
@@ -49,14 +48,14 @@ module speculativeglobalhistory #(parameter k = 10) (
   logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
   logic [k-1:0]            GHRF;
-  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
-  logic [k-1:0]            GHRNextF;
-  logic [k:-1] 			   GHRNextD, OldGHRD;
-  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
+  logic 				   GHRExtraF;
+  logic [k-1:0] 		   GHRD, GHRE, GHRM, GHRW;
+  logic [k-1:0] 		   GHRNextF;
+  logic [k-1:0] 		   GHRNextD;
+  logic [k-1:0] 		   GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE;
   
-  logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
@@ -102,30 +101,42 @@ module speculativeglobalhistory #(parameter k = 10) (
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
 
   // GHR pipeline
-  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
-                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
-                    GHRF;
+  // this version fails the regression test do to pessimistic x propagation.
+  // assign GHRNextF = FlushD | DirPredictionWrongE ?  GHRNextD[k-1:0] :
+  //                  BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+  //                  GHRF;
 
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
-  
-  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
-  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
-  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
-				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
-				OldGHRD[k:0];
+  always_comb begin
+	if(FlushD | DirPredictionWrongE) begin
+	  GHRNextF = GHRNextD[k-1:0];
+	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
+	else GHRNextF = GHRF;
+  end
 
-  assign GHRNextE = FlushE ? GHRNextM : GHRD;
-  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
-  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);	
+  flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
+
+  // use with out instruction class prediction
+  //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
+  // with instruction class prediction
+  assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
+					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
+  					WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}:       // shift left
+					GHRF[k-1:0];
+
+  flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+
+  assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed
+					FlushE ? GHRNextM :                                // branch is flushed
+					GHRD;
+  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
 
   assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+  flopenr  #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
 
   assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  flopenr  #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
 endmodule

From 63267ff378e9291e421c3dedfd6c4942af9dd538 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 29 Jan 2023 22:39:37 -0600
Subject: [PATCH 83/84] optimized branch predictor by removing unnecessary
 registers.

---
 pipelined/src/ifu/bpred/speculativegshare.sv | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv
index e4d624382..62608f0bb 100644
--- a/pipelined/src/ifu/bpred/speculativegshare.sv
+++ b/pipelined/src/ifu/bpred/speculativegshare.sv
@@ -128,15 +128,15 @@ module speculativegshare #(parameter int k = 10 ) (
   flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
 
   assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed
-					FlushE ? GHRNextM :                                // branch is flushed
+					FlushE ? GHRE :                                // branch is flushed
 					GHRD;
-  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
+  flopenr  #(k) GHREReg(clk, reset, (BranchInstrE & ~StallE) | FlushE, GHRNextE, GHRE);
 
-  assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+  //assign GHRNextM = FlushM ? GHRM : GHRE;
+  //flopenr  #(k) GHRMReg(clk, reset, (BranchInstrM & ~StallM) | FlushM, GHRNextM, GHRM);
 
-  assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
+  //assign GHRNextW = FlushW ? GHRW : GHRM;
+  //flopenr  #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 

From 7a4218788cea70779678c8c979dab64ab7bc2f00 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 30 Jan 2023 11:47:51 -0600
Subject: [PATCH 84/84] Imperas found a real bug in virtual memory. If the
 instruction address spilled across two pages and the second page misses the
 TLB, the HPTW received a tlb miss at the address of the first page rather
 than the second. After the walk the TLB was updated with the PTE from the
 first page at the address of the second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
---
 pipelined/regression/wave.do               | 541 +++++++++++----------
 pipelined/src/ifu/ifu.sv                   |   8 +-
 pipelined/src/lsu/lsu.sv                   |   4 +-
 pipelined/src/mmu/hptw.sv                  |   4 +-
 pipelined/src/wally/wallypipelinedcore.sv  |   6 +-
 pipelined/testbench/common/functionName.sv |   2 +-
 6 files changed, 284 insertions(+), 281 deletions(-)

diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index a17bc502e..d3a9d332c 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -43,7 +43,6 @@ add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu
 add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
 add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/core/PCF
 add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
 add wave -noupdate -group PCS /testbench/dut/core/PCE
 add wave -noupdate -group PCS /testbench/dut/core/PCM
@@ -177,199 +176,204 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
-add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
-add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
-add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
-add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCF
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
+add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
+add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -450,77 +454,78 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
 add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
 add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
-add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
-add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
-add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
-add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
-add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
-add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
-add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
-add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
-add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
-add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
-add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
-add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
-add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
-add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
-add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
-add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
-add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF
+add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -expand -group ifu -expand -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
+add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
+add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
+add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
+add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
+add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
+add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
+add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
+add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
+add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
+add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
+add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
+add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
+add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
+add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
+add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
 add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
 add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
@@ -601,7 +606,6 @@ add wave -noupdate -expand -group {branch direction} -expand -group ghr /testben
 add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
 add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
 add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
 add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
 add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
 add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
@@ -624,10 +628,9 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF
 add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {296884 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {1211181 ns} 1} {{Cursor 5} {158657 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -643,4 +646,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {18545889 ns} {18546113 ns}
+WaveRestoreZoom {158482 ns} {158818 ns}
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 79f16c59a..c64049909 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -44,7 +44,7 @@ module ifu (
   output logic [2:0]  IFUHBURST,             // Bus burst from IFU to EBU
   output logic [1:0]  IFUHTRANS,             // Bus transaction type from IFU to EBU
 
-  output logic [`XLEN-1:0] PCF,              // Fetch stage instruction address
+  output logic [`XLEN-1:0]  PCFSpill,                                 // PCF with possible + 2 to handle spill to HPTW
   // Execute
   output logic [`XLEN-1:0] 	PCLinkE,                                  // The address following the branch instruction. (AKA Fall through address)
   input  logic 				PCSrcE,                                   // Executation stage branch is taken
@@ -97,19 +97,19 @@ module ifu (
   logic                        BranchMisalignedFaultE;                // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   logic [`XLEN-1:0] 		   PCPlus2or4F;                           // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
   logic [`XLEN-1:0]			   PCNextFSpill;                          // Next PCF after possible + 2 to handle spill
-  logic [`XLEN-1:0] 		   PCFSpill;                              // PCF with possible + 2 to handle spill
   logic [`XLEN-1:0]            PCLinkD;                               // PCF2or4F delayed 1 cycle.  This is next PC after a control flow instruction (br or j)
   logic [`XLEN-1:2]            PCPlus4F;                              // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
   logic [`XLEN-1:0]            PCD;                                   // Decode stage instruction address
   logic [`XLEN-1:0] 		   NextValidPCE;                          // The PC of the next valid instruction in the pipeline after  csr write or fence
-  logic [`PA_BITS-1:0]         PCPF;         // Physical address after address translation
+  logic [`XLEN-1:0] 		   PCF;                                   // Fetch stage instruction address
+  logic [`PA_BITS-1:0]         PCPF;                                  // Physical address after address translation
   logic [`XLEN+1:0]            PCFExt;                                //
 
   logic [31:0] 				   IROMInstrF;                            // Instruction from the IROM
   logic [31:0] 				   ICacheInstrF;                          // Instruction from the I$
   logic [31:0] 				   InstrRawF;                             // Instruction from the IROM, I$, or bus
   logic                        CompressedF;                           // The fetched instruction is compressed
-  logic [31:0]  PostSpillInstrRawF;          // Fetch instruction after merge two halves of spill
+  logic [31:0] 				   PostSpillInstrRawF;                    // Fetch instruction after merge two halves of spill
   logic [31:0] 				   InstrRawD;                             // Non-decompressed instruction in the Decode stage
   
   logic [1:0]                  IFURWF;                                // IFU alreays read IFURWF = 10
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 2eb8df1e5..9a8226a5e 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -79,7 +79,7 @@ module lsu (
   input  logic [`XLEN-1:0]    SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
   input  logic                STATUS_MXR, STATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
   input  logic [1:0]          STATUS_MPP,                           // Machine previous privilege mode
-  input  logic [`XLEN-1:0]    PCF,                                  // Fetch PC 
+  input  logic [`XLEN-1:0]    PCFSpill,                                  // Fetch PC 
   input  logic                ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
   input  logic                InstrDAPageFaultF,                    // ITLB hit needs to update dirty or access bits
   output logic [`XLEN-1:0]    PTE,                                  // Page table entry write to ITLB
@@ -152,7 +152,7 @@ module lsu (
   if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
     hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
-      .FlushW, .DCacheStallM, .SATP_REGW, .PCF,
+      .FlushW, .DCacheStallM, .SATP_REGW, .PCFSpill,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
       .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
       .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv
index 9e8ac65ba..5cf58ffdf 100644
--- a/pipelined/src/mmu/hptw.sv
+++ b/pipelined/src/mmu/hptw.sv
@@ -34,7 +34,7 @@
 module hptw (
 	input  logic                clk, reset,
 	input  logic [`XLEN-1:0]    SATP_REGW, 					// includes SATP.MODE to determine number of levels in page table
-	input  logic [`XLEN-1:0]    PCF,  							// addresses to translate
+	input  logic [`XLEN-1:0]    PCFSpill,  							// addresses to translate
 	input  logic [`XLEN+1:0]    IEUAdrExtM, 				// addresses to translate
 	input  logic [1:0]          MemRWM, AtomicM,
 	// system status
@@ -109,7 +109,7 @@ module hptw (
 	assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF);
 
 	// Determine which address to translate
-	mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
+	mux2 #(`XLEN) vadrmux(PCFSpill, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
 	assign CurrentPPN = PTE[`PPN_BITS+9:10];
 
 	// State flops
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index aae48f29d..7013d0309 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -62,7 +62,7 @@ module wallypipelinedcore (
   logic [2:0]                    Funct3E;
   logic [31:0]                   InstrD;
   logic [31:0] 					 InstrM;
-  logic [XLEN-1:0]               PCF, PCE, PCLinkE;
+  logic [XLEN-1:0]               PCFSpill, PCE, PCLinkE;
   logic [XLEN-1:0] 			  PCM;
   logic [XLEN-1:0]               CSRReadValW, MDUResultW;
   logic [XLEN-1:0]               UnalignedPCNextF, PCNext2F;
@@ -166,7 +166,7 @@ module wallypipelinedcore (
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
     // Fetch
-    .HRDATA, .PCF, .IFUHADDR, .PCNext2F,
+    .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
     .ICacheAccess, .ICacheMiss,
     // Execute
@@ -235,7 +235,7 @@ module wallypipelinedcore (
     .StoreAmoMisalignedFaultM, // connects to privilege
     .StoreAmoAccessFaultM,     // connects to privilege
     .InstrDAPageFaultF,
-    .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
+    .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
     .LSUStallM);                    
 
   if(BUS_SUPPORTED) begin : ebu
diff --git a/pipelined/testbench/common/functionName.sv b/pipelined/testbench/common/functionName.sv
index 45a11e8c5..f3cb656f5 100644
--- a/pipelined/testbench/common/functionName.sv
+++ b/pipelined/testbench/common/functionName.sv
@@ -48,7 +48,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   logic 	    StallD, StallE, FlushD, FlushE;
   integer 	    ProgramAddrIndex, ProgramAddrIndexQ;
 
-  assign PCF = testbench.dut.core.PCF;
+  assign PCF = testbench.dut.core.ifu.PCF;
   assign StallD = testbench.dut.core.StallD;
   assign StallE = testbench.dut.core.StallE;  
   assign FlushD = testbench.dut.core.FlushD;