diff --git a/.gitignore b/.gitignore
index 8e9c77346..d1dde2a66 100644
--- a/.gitignore
+++ b/.gitignore
@@ -188,6 +188,7 @@ sim/cfi/*
 sim/branch/*
 sim/obj_dir
 examples/verilog/fulladder/obj_dir
+examples/verilog/fulladder/fulladder.vcd
 config/deriv
 docs/docker/buildroot-config-src
 docs/docker/testvector-generation
diff --git a/examples/verilog/fulladder/fulladder.sv b/examples/verilog/fulladder/fulladder.sv
index 478c3db82..156bec3f9 100644
--- a/examples/verilog/fulladder/fulladder.sv
+++ b/examples/verilog/fulladder/fulladder.sv
@@ -19,6 +19,8 @@ module testbench();
   // at start of test, load vectors and pulse reset
   initial
     begin
+      $dumpfile("fulladder.vcd");
+      $dumpvars;
       $readmemb("fulladder.tv", testvectors);
       cycle = 0;
       vectornum = 0; errors = 0;
@@ -47,6 +49,7 @@ module testbench();
         $finish;
       end
     end
+
 endmodule
 
 module fulladder(input  logic a, b, c,
diff --git a/examples/verilog/fulladder/verilate b/examples/verilog/fulladder/verilate
index 2b6d7908d..f1efcc74c 100755
--- a/examples/verilog/fulladder/verilate
+++ b/examples/verilog/fulladder/verilate
@@ -1,5 +1,3 @@
-#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
-#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
-#verilator --binary --top-module testbench fulladder.sv
-verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
+verilator --binary --top-module testbench --trace fulladder.sv
+obj_dir/Vtestbench
 
diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
index 7acce82b8..5235456db 100644
--- a/sim/verilator/Makefile
+++ b/sim/verilator/Makefile
@@ -30,6 +30,10 @@ DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
 
 default: run
 
+run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
+	mkdir -p $(VERILATOR_DIR)/logs
+	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
+	
 profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
 	$(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 
 	mv gmon.out gmon_$(WALLYCONF).out
@@ -39,17 +43,13 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
 	mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
 	echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
 
-run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
-	mkdir -p $(VERILATOR_DIR)/logs
-	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
-	
 wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(DEPENDENCIES)
 	verilator \
 	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
 	--binary --trace \
 	$(OPT) $(PARAMS) $(NONPROF) \
 	$(EXTRA_ARGS) \
-	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
+	--top-module testbench  --relative-includes \
 	$(INCLUDE_PATH) \
 	${WALLY}/sim/verilator/wrapper.c \
 	$(SOURCES)
@@ -61,13 +61,10 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	--binary \
 	--prof-cfuncs $(OPT) $(PARAMS) \
 	$(EXTRA_ARGS) \
-	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
+	--top-module testbench  --relative-includes \
 	$(INCLUDE_PATH) \
 	${WALLY}/sim/verilator/wrapper.c \
 	$(SOURCES)
 
-questa:
-	vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"
-
 clean:
 	rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling
\ No newline at end of file