From 8f09240e6c5a54c02e027028296052652952ccbb Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 14 Jun 2024 03:42:15 -0700 Subject: [PATCH] Simplified outdated documentation pointers --- src/cache/cache.sv | 2 +- src/cache/cacheLRU.sv | 2 +- src/cache/cachefsm.sv | 2 +- src/cache/cacheway.sv | 2 +- src/cache/subcachelineread.sv | 2 +- src/ebu/ahbcacheinterface.sv | 2 +- src/ebu/ahbinterface.sv | 2 +- src/ebu/buscachefsm.sv | 2 +- src/ebu/busfsm.sv | 2 +- src/ebu/controllerinput.sv | 2 +- src/ebu/ebu.sv | 2 +- src/ebu/ebufsmarb.sv | 2 +- src/fpu/fclassify.sv | 2 +- src/fpu/fcmp.sv | 2 +- src/fpu/fctrl.sv | 2 +- src/fpu/fcvt.sv | 2 +- src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtcycles.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage4.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtuslc2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtuslc4.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv | 2 +- src/fpu/fhazard.sv | 2 +- src/fpu/fli.sv | 2 +- src/fpu/fma/fma.sv | 2 +- src/fpu/fma/fmaadd.sv | 2 +- src/fpu/fma/fmaalign.sv | 2 +- src/fpu/fma/fmaexpadd.sv | 2 +- src/fpu/fma/fmalza.sv | 2 +- src/fpu/fma/fmamult.sv | 2 +- src/fpu/fma/fmasign.sv | 2 +- src/fpu/fmtparams.sv | 2 +- src/fpu/fpu.sv | 2 +- src/fpu/fregfile.sv | 2 +- src/fpu/fround.sv | 2 +- src/fpu/fsgninj.sv | 2 +- src/fpu/packoutput.sv | 2 +- src/fpu/postproc/cvtshiftcalc.sv | 2 +- src/fpu/postproc/divshiftcalc.sv | 2 +- src/fpu/postproc/flags.sv | 2 +- src/fpu/postproc/fmashiftcalc.sv | 2 +- src/fpu/postproc/negateintres.sv | 2 +- src/fpu/postproc/normshift.sv | 2 +- src/fpu/postproc/postprocess.sv | 2 +- src/fpu/postproc/resultsign.sv | 2 +- src/fpu/postproc/round.sv | 2 +- src/fpu/postproc/roundsign.sv | 2 +- src/fpu/postproc/shiftcorrection.sv | 2 +- src/fpu/postproc/specialcase.sv | 2 +- src/fpu/unpack.sv | 2 +- src/fpu/unpackinput.sv | 2 +- src/generic/decoder.sv | 3 --- src/generic/mem/ram1p1rwe.sv | 2 +- src/hazard/hazard.sv | 2 +- src/ieu/alu.sv | 2 +- src/ieu/bmu/bitmanipalu.sv | 2 +- src/ieu/bmu/bitreverse.sv | 2 +- src/ieu/bmu/bmuctrl.sv | 2 +- src/ieu/bmu/byteop.sv | 2 +- src/ieu/bmu/clmul.sv | 2 +- src/ieu/bmu/cnt.sv | 2 +- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/bmu/zbb.sv | 2 +- src/ieu/bmu/zbc.sv | 2 +- src/ieu/comparator.sv | 2 +- src/ieu/controller.sv | 2 +- src/ieu/datapath.sv | 2 +- src/ieu/extend.sv | 2 +- src/ieu/ieu.sv | 2 +- src/ieu/regfile.sv | 2 +- src/ieu/shifter.sv | 2 +- src/ifu/bpred/RASPredictor.sv | 2 +- src/ifu/bpred/btb.sv | 2 +- src/ifu/decompress.sv | 4 ---- src/ifu/spill.sv | 2 +- src/lsu/align.sv | 2 +- src/lsu/amoalu.sv | 2 +- src/lsu/atomic.sv | 2 +- src/lsu/dtim.sv | 2 +- src/lsu/endianswap.sv | 2 +- src/lsu/lrsc.sv | 2 +- src/lsu/lsu.sv | 2 +- src/lsu/subwordread.sv | 2 +- src/lsu/subwordwrite.sv | 2 +- src/lsu/swbytemask.sv | 2 +- src/mdu/div.sv | 2 +- src/mdu/divstep.sv | 2 +- src/mdu/mdu.sv | 2 +- src/mdu/mul.sv | 2 +- src/mmu/adrdec.sv | 2 +- src/mmu/adrdecs.sv | 2 +- src/mmu/hptw.sv | 2 +- src/mmu/mmu.sv | 2 +- src/mmu/pmachecker.sv | 2 +- src/mmu/pmpadrdec.sv | 2 +- src/mmu/pmpchecker.sv | 2 +- src/mmu/tlb/tlb.sv | 2 +- src/mmu/tlb/tlbcam.sv | 2 +- src/mmu/tlb/tlbcamline.sv | 2 +- src/mmu/tlb/tlbcontrol.sv | 2 +- src/mmu/tlb/tlblru.sv | 2 +- src/mmu/tlb/tlbmixer.sv | 2 +- src/mmu/tlb/tlbram.sv | 2 +- src/mmu/tlb/tlbramline.sv | 2 +- src/mmu/tlb/vm64check.sv | 2 +- src/privileged/csr.sv | 2 +- src/privileged/csrc.sv | 2 +- src/privileged/csri.sv | 2 +- src/privileged/csrm.sv | 2 +- src/privileged/csrs.sv | 2 +- src/privileged/csrsr.sv | 2 +- src/privileged/csru.sv | 2 +- src/privileged/privdec.sv | 2 +- src/privileged/privileged.sv | 2 +- src/privileged/privmode.sv | 2 +- src/privileged/privpiperegs.sv | 2 +- src/privileged/trap.sv | 2 +- src/uncore/ahbapbbridge.sv | 2 +- src/uncore/clint_apb.sv | 2 +- src/uncore/gpio_apb.sv | 2 +- src/uncore/plic_apb.sv | 2 +- src/uncore/ram_ahb.sv | 2 +- src/uncore/rom_ahb.sv | 2 +- src/uncore/uartPC16550D.sv | 2 +- src/uncore/uart_apb.sv | 2 +- src/uncore/uncore.sv | 2 +- src/wally/wallypipelinedcore.sv | 2 +- src/wally/wallypipelinedsoc.sv | 2 +- studies/comparator.sv | 2 +- 140 files changed, 138 insertions(+), 145 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 53d43a6b3..3569a92e3 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -7,7 +7,7 @@ // // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 3cbadd530..cb111eade 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -7,7 +7,7 @@ // // Purpose: Implements Pseudo LRU. Tested for Powers of 2. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index d3cff2e96..64084f863 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for the cache fsm // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 41e620547..7406ebd83 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -7,7 +7,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 95920ec7e..3e9718c27 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -7,7 +7,7 @@ // // Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes. // -// Documentation: RISC-V System on Chip Design Chapter 7 +// Documentation: RISC-V System on Chip Design // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 5316e215f..59d492ac4 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -7,7 +7,7 @@ // // Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions. // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 8852b52c3..a9bf8f497 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -7,7 +7,7 @@ // // Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ). // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index b0f28966e..5f39e1602 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for cache to AHB bus interface // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 11ba896e4..8aa640673 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -7,7 +7,7 @@ // // Purpose: Simple NON_SEQ (no burst) AHB controller. // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 67e4795a6..97ea0d5b4 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -11,7 +11,7 @@ // Connects core to peripherals and I/O pins on SOC // Bus width presently matches XLEN // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 657f345cd..2eec7db58 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -11,7 +11,7 @@ // Connects core to peripherals and I/O pins on SOC // Bus width presently matches XLEN // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 571bdcc63..daf3da1e8 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -8,7 +8,7 @@ // Purpose: Arbitrates requests from instruction and data streams // LSU has priority. // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index f35f71869..6f52b0eae 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 0944090fc..d1baac3b8 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point comparison unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index d8c1fe1d7..4f1bf042b 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index 0d385b00c..90e8d7a23 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point conversions of configurable size // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // Int component of the Wally configurable RISC-V project. // diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index dba69267a..578996315 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 9e2489eb3..6a44b0ced 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -6,7 +6,7 @@ // // Purpose: Determine number of cycles for divsqrt // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 03d144263..058a3d17b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Exponent caclulation for divide and square root // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index bc9dce536..799ded999 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index a04523e58..90af95643 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8975edeb6..4e05b5e58 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: divsqrt state machine for multi-cycle operations // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 0f092706a..dc6b0057a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: k stages of divsqrt logic, plus registers // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index c3954bc0a..5bfb11b56 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Divide/Square root postprocessing // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index ffc62b5cc..1f668911a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index c3d6e210c..fa13cadeb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: radix-2 divsqrt recurrence stage // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index 47b1d4b26..551a358c4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: radix-4 divsqrt recurrence stage // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 55810665b..db858cb0b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index 5a802934e..3d842f9a8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index 2d4cd5e48..193231eea 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index 610b79395..840215c28 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -6,7 +6,7 @@ // // Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index bf75532b3..606b1202f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index e68934294..c31324ad1 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index cf3b736d7..349189f33 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point float immediate // -// Documentation: RISC-V System on Chip Design Chapter 16 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index 8bf4d4cbb..36d4a0ad5 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 995494f2c..4942f9d9f 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index c6f0afebc..292472f7f 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA alginment shift // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index 06ac7e290..4ad254f79 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 01439f4d1..417b9de28 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14) +// Documentation: RISC-V System on Chip Design // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 8ce492f03..ea0ea2238 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index 891c28746..8220f0aad 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fmtparams.sv b/src/fpu/fmtparams.sv index d83dfd782..ad2dcfa4d 100644 --- a/src/fpu/fmtparams.sv +++ b/src/fpu/fmtparams.sv @@ -7,7 +7,7 @@ // // Purpose: Look up bias of exponent and number of fractional bits for the selected format // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 8163bafff..122888509 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index e907875a2..40933de17 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index d905618ba..bf4a4f7ad 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point round to integer for Zfa // -// Documentation: RISC-V System on Chip Design Chapter 16 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 4fe03522b..68e2eb493 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv index c9a500700..a81527e01 100644 --- a/src/fpu/packoutput.sv +++ b/src/fpu/packoutput.sv @@ -7,7 +7,7 @@ // // Purpose: Pack the output of the FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 19993a996..84f5120a0 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index d45afeea6..d46b58f35 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index cb16cc2a1..be28a490c 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index cf334aa9b..22c354e30 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index 5ca848b0b..b9cb038a4 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f235d4d5b..d0a14cbfd 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 1ce993c33..f4af9d440 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing: normalization, rounding, sign, flags, special cases // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 69f25a2b0..9425ec7ee 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index c99d5185c..4c6d251fb 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 7eedc5eba..fe422b98c 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation for rounding // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index ec1ec1897..b7829a62e 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index b9dbf4b9e..bb655942d 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 2e87d17fc..b24554fc0 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index a6c421e5c..1b27c439b 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 78b816c3c..8af273fc5 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -29,8 +29,5 @@ module decoder #(parameter BINARY_BITS = 3) ( output logic [(2**BINARY_BITS)-1:0] onehot ); - // *** Double check whether this synthesizes as expected - // -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists assign onehot = 1 << binary; - endmodule diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index 240af6db1..fb41d99bf 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -66,7 +66,7 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( // READ first SRAM model ////////////////////////////////////////////////////////////////////////////// end else begin: ram - // *** Vivado is not implementing this as block ram for some reason. + // Vivado is not implementing this as block ram for some reason. // The version with byte write enables it correctly infers block ram. bit [WIDTH-1:0] RAM[DEPTH-1:0]; diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 5d2611dda..a5b6e319d 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine stalls and flushes // -// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 74eb6f7f6..e142de1e7 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 76734f97f..1b05b43e0 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 083033d53..5fc4e8b49 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -7,7 +7,7 @@ // // Purpose: Bit reverse submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 97a0caa45..834270685 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -7,7 +7,7 @@ // // Purpose: Top level bit manipulation instruction decoder // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 263680aea..33a0dc332 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -7,7 +7,7 @@ // // Purpose: RISCV bitmanip byte-wise operation unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index f32fcece9..2ea45606f 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -7,7 +7,7 @@ // // Purpose: Carry-Less multiplication unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index dff468257..f0bc5f72d 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -7,7 +7,7 @@ // // Purpose: Count Instruction Submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 66d69fb21..268f9dad5 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -7,7 +7,7 @@ // // Purpose: Sign/Zero Extension Submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 838468fa1..435c8dff1 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -5,7 +5,7 @@ // // Purpose: Population Count // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index f9957c787..d5f9b269c 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBB top level unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index cb63eb85a..e11e94167 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBC top-level unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 466167fb3..175e7df08 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -7,7 +7,7 @@ // // Purpose: Branch comparison // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index f8d3e2122..21f024942 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -7,7 +7,7 @@ // // Purpose: Top level controller module // -// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 30848ea6d..50a61fc2a 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -7,7 +7,7 @@ // // Purpose: Wally Integer Datapath // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 11ab14419..437797859 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -7,7 +7,7 @@ // // Purpose: Produce sign-extended immediates from various formats // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 38d50e3c3..362ca132b 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 0cb6beaaa..48359d3ca 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -7,7 +7,7 @@ // // Purpose: 3-port register file // -// Documentation: RISC-V System on Chip Design Chapter 4 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 52d87bb1d..8d4da28d9 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 5129e9043..85eda07ca 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -7,7 +7,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index e9e0b5bfd..1ac95bed9 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -8,7 +8,7 @@ // Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions. // It also guesses the type of instrution; jalr(r), return, jump (jr), or branch. // -// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 5a8c65ecf..512dacfd5 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -6,10 +6,6 @@ // Modified: 18 January 2023 // // Purpose: Expand 16-bit compressed instructions to 32 bits -// -// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1) -// RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97 -// *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 49e4ddc82..5b82aac76 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -9,7 +9,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/align.sv b/src/lsu/align.sv index c28c1b9cf..25a2c99d7 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -9,7 +9,7 @@ // It is simlar to the IFU's spill module and probably could be merged together with // some effort. // -// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index a6ee53e73..194573d21 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -7,7 +7,7 @@ // // Purpose: Performs AMO operations // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 704eb4c62..e318260ab 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -7,7 +7,7 @@ // // Purpose: Wrapper for amoalu and lrsc // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 1386db96f..5bd46deb9 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -7,7 +7,7 @@ // // Purpose: tightly integrated memory into the LSU. // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 7c042886a..3634e2322 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -7,7 +7,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 5981035c1..437907e55 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -8,7 +8,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 43176e04b..f0d046679 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -9,7 +9,7 @@ // HPTW, DMMU, data cache, interface to external bus // Atomic, Endian swap, and subword read/write logic // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index a0e1bfc2f..40e3c11c6 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -7,7 +7,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index eec6fe020..4ae097cc3 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -7,7 +7,7 @@ // // Purpose: Masking and muxing for subword writes // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index fc1f95c4e..cbe4070cc 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -7,7 +7,7 @@ // // Purpose: On-chip RAM, external to core // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/div.sv b/src/mdu/div.sv index 2ae35d8f4..66fe5d9d4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index f478ad86f..d47742fa9 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -6,7 +6,7 @@ // // Purpose: Radix-2 restoring integer division step. k steps are used in div // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 8918e5830..34646ac94 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index 65eaefd82..7c3f13a85 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Integer multiplication // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index bf092dbc6..f4de5a7b7 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index d71fef82a..2ef7c25f1 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 32eef1bf6..6cc1fa2a5 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -10,7 +10,7 @@ // // Purpose: Hardware Page Table Walker // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index ec41773a8..cc12a3982 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index b1953cb9b..f2a2e984b 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f5245081..71a6b890a 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 30a525744..a97b7ff2e 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index 5fbd10caf..b1d0966cf 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index aa569f2dd..06b66efcc 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index f5856ef56..057c8766b 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 83074deb3..a75208a14 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 4776b5afb..96359590b 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index d615d1370..502d3ef83 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 620f338a1..3b329705d 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 910db3aec..0b3e3994a 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index d8168dac2..229bb5a5f 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index fac432251..a9d38028e 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index f0704d0cf..fd078b04b 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -7,7 +7,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index fafc5c845..b3db38e8a 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 348002e46..7aaf4c052 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -11,7 +11,7 @@ // - Disabling portions of the instruction set with bits of the MISA register // - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 9623aa8b5..ebd468ad6 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 161bf521c..18a171856 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register (and environment configuration register and others shared across modes) // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 62ac86c8d..eeb364a89 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -6,7 +6,7 @@ // // Purpose: User-Mode Control and Status Registers for Floating Point // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 60828a3f2..6321413d4 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index c0dffcaa6..a02d59383 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index f1c5bfd76..f9a38d501 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -6,7 +6,7 @@ // // Purpose: Track privilege mode. Change on traps and returns. // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index ed43571bd..4cab65c34 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 788b39618..247bfe678 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -6,7 +6,7 @@ // // Purpose: Handle Traps: Exceptions and Interrupts // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index df41c9541..84979ddee 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// Documentation: RISC-V System on Chip Design Chapter 6 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index c416f2938..1f69a4529 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index e072700c3..c398e8d15 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -8,7 +8,7 @@ // See FE310-G002-Manual-v19p05 for specifications // No interrupts, drive strength, or pull-ups supported // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 960aa799a..607994906 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -11,7 +11,7 @@ // This PLIC implementation serves as both the PLIC Gateways and PLIC Core. // It assumes interrupt sources are level-triggered wires. // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index ed4b4d9ec..0b4e777e4 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core, with AHB interface // -// Documentation: RISC-V System on Chip Design Chapter 6 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index 91528c2e8..d20ef64da 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip ROM, external to core // -// Documentation: RISC-V System on Chip Design Chapter 6 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index f93795be5..8a1b461fc 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -13,7 +13,7 @@ // Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 // Timeout not yet implemented // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index c3f8bb31c..f7dcf2a60 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -8,7 +8,7 @@ // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index fb7bb8360..9390b35cf 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -7,7 +7,7 @@ // Purpose: System-on-Chip components outside the core // Memories, peripherals, external bus control // -// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 6ef3e2a54..b20472732 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -6,7 +6,7 @@ // // Purpose: Pipelined RISC-V Processor // -// Documentation: RISC-V System on Chip Design (Figure 4.1) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 4489646fe..9f5e5ee00 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -6,7 +6,7 @@ // // Purpose: System on chip including pipelined processor and uncore memories/peripherals // -// Documentation: RISC-V System on Chip Design (Figure 6.20) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/studies/comparator.sv b/studies/comparator.sv index 01d38181b..1f9877077 100644 --- a/studies/comparator.sv +++ b/studies/comparator.sv @@ -7,7 +7,7 @@ // // Purpose: Branch comparison // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw