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Fixed c.jr instruction improperly writing ra

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This commit is contained in:
David Harris 2021-01-28 15:18:23 -05:00
parent 9a45b49536
commit 8eebf01dca
2 changed files with 23 additions and 25 deletions
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46
wally-pipelined/src/datapath.sv
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@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Wally Datapath
// Purpose: Wally Integer Datapath
//
// A component of the Wally configurable RISC-V project.
//
@ -27,39 +27,37 @@
module datapath (
input logic clk, reset,
// Fetch stage signals
// Decode stage signals
input logic StallD, FlushD,
input logic [2:0] ImmSrcD,
input logic LoadStallD, // for performance counter
input logic [31:0] InstrD,
input logic StallD, FlushD,
input logic [2:0] ImmSrcD,
input logic [31:0] InstrD,
// Execute stage signals
input logic FlushE,
input logic [1:0] ForwardAE, ForwardBE,
input logic PCSrcE,
input logic [4:0] ALUControlE,
input logic ALUSrcAE, ALUSrcBE,
input logic TargetSrcE,
input logic FlushE,
input logic [1:0] ForwardAE, ForwardBE,
input logic PCSrcE,
input logic [4:0] ALUControlE,
input logic ALUSrcAE, ALUSrcBE,
input logic TargetSrcE,
input logic [`XLEN-1:0] PCE,
output logic [2:0] FlagsE,
output logic [2:0] FlagsE,
output logic [`XLEN-1:0] PCTargetE,
// Memory stage signals
input logic FlushM,
input logic [2:0] Funct3M,
output logic [`XLEN-1:0] SrcAM,
input logic FlushM,
input logic [2:0] Funct3M,
input logic [`XLEN-1:0] CSRReadValM,
output logic [`XLEN-1:0] WriteDataFullM, DataAdrM,
input logic [`XLEN-1:0] ReadDataExtM,
input logic RetM, TrapM,
input logic RetM, TrapM,
output logic [`XLEN-1:0] SrcAM,
output logic [`XLEN-1:0] WriteDataFullM, DataAdrM,
// Writeback stage signals
input logic FlushW,
input logic RegWriteW,
input logic [1:0] ResultSrcW,
input logic FlushW,
input logic RegWriteW,
input logic [1:0] ResultSrcW,
input logic [`XLEN-1:0] PCLinkW,
// Hazard Unit signals
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
output logic [4:0] RdE, RdM, RdW);
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
output logic [4:0] RdE, RdM, RdW
);
// Fetch stage signals
// Decode stage signals

2
wally-pipelined/src/decompress.sv
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@ -149,7 +149,7 @@ module decompress (
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
5'b10100: if (instr16[12] == 0)
if (instr16[6:2] == 5'b00000)
InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
else
InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
else