From 8eebf01dca83fcb1e144a36613c870f049d6c820 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 28 Jan 2021 15:18:23 -0500
Subject: [PATCH] Fixed c.jr instruction improperly writing ra

---
 wally-pipelined/src/datapath.sv   | 46 +++++++++++++++----------------
 wally-pipelined/src/decompress.sv |  2 +-
 2 files changed, 23 insertions(+), 25 deletions(-)

diff --git a/wally-pipelined/src/datapath.sv b/wally-pipelined/src/datapath.sv
index 3c5685b69..ef15f97ed 100644
--- a/wally-pipelined/src/datapath.sv
+++ b/wally-pipelined/src/datapath.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: Wally Datapath
+// Purpose: Wally Integer Datapath
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -27,39 +27,37 @@
 
 module datapath (
   input logic clk, reset,
-  // Fetch stage signals
   // Decode stage signals
-  input  logic        StallD, FlushD,
-  input  logic [2:0]  ImmSrcD,
-  input  logic        LoadStallD, // for performance counter
-  input  logic [31:0] InstrD,
+  input  logic             StallD, FlushD,
+  input  logic [2:0]       ImmSrcD,
+  input  logic [31:0]      InstrD,
   // Execute stage signals
-  input  logic        FlushE,
-  input  logic [1:0]  ForwardAE, ForwardBE,
-  input  logic        PCSrcE,
-  input  logic [4:0]  ALUControlE,
-  input  logic        ALUSrcAE, ALUSrcBE,
-  input  logic        TargetSrcE, 
+  input  logic             FlushE,
+  input  logic [1:0]       ForwardAE, ForwardBE,
+  input  logic             PCSrcE,
+  input  logic [4:0]       ALUControlE,
+  input  logic             ALUSrcAE, ALUSrcBE,
+  input  logic             TargetSrcE, 
   input  logic [`XLEN-1:0] PCE,
-  output logic [2:0]  FlagsE,
+  output logic [2:0]       FlagsE,
   output logic [`XLEN-1:0] PCTargetE,
   // Memory stage signals
-  input  logic        FlushM,
-  input  logic [2:0]  Funct3M,
-  output logic [`XLEN-1:0] SrcAM,
+  input  logic             FlushM,
+  input  logic [2:0]       Funct3M,
   input  logic [`XLEN-1:0] CSRReadValM,
-  output logic [`XLEN-1:0] WriteDataFullM, DataAdrM,
   input  logic [`XLEN-1:0] ReadDataExtM,
-  input  logic        RetM, TrapM,
+  input  logic             RetM, TrapM,
+  output logic [`XLEN-1:0] SrcAM,
+  output logic [`XLEN-1:0] WriteDataFullM, DataAdrM,
   // Writeback stage signals
-  input  logic        FlushW,
-  input  logic        RegWriteW, 
-  input  logic [1:0]  ResultSrcW,
+  input  logic             FlushW,
+  input  logic             RegWriteW, 
+  input  logic [1:0]       ResultSrcW,
   input  logic [`XLEN-1:0] PCLinkW,
-
   // Hazard Unit signals 
-  output logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E,
-  output logic [4:0]  RdE, RdM, RdW);
+  output logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E,
+  output logic [4:0]       RdE, RdM, RdW
+);
 
   // Fetch stage signals
   // Decode stage signals
diff --git a/wally-pipelined/src/decompress.sv b/wally-pipelined/src/decompress.sv
index bb12db097..7c8b9f9a8 100644
--- a/wally-pipelined/src/decompress.sv
+++ b/wally-pipelined/src/decompress.sv
@@ -149,7 +149,7 @@ module decompress (
                         InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
             5'b10100: if (instr16[12] == 0)
                         if (instr16[6:2] == 5'b00000) 
-                          InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
+                          InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
                         else
                           InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
                       else