Merge branch 'main' of https://github.com/stineje/cvw

src/ieu/ieu.sv

@@ -77,7 +77,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   output logic              StructuralStallD,                             // IEU detects structural hazard in Decode stage
   output logic              LoadStallD,                                   // Structural stalls for load, sent to performance counters
   output logic              StoreStallD,                                  // load after store hazard
-  output logic              CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
+  output logic              CSRReadM, CSRWriteM, PrivilegedM,             // CSR read, CSR write, is privileged instruction
   output logic              CSRWriteFenceM,                               // CSR write or fence instruction needs to flush subsequent instructions
   // Debug scan chain
   input  logic              DebugScanEn,
@@ -120,7 +120,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   logic       BMUActiveE;                                                 // Bit manipulation instruction being executed
   logic [1:0] CZeroE;                                                     // {czero.nez, czero.eqz} instructions active
 
-  logic DSCR;
+  logic DSCR;                                                             // Debug Scan Chain Register
            
   controller #(P) c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,

src/ifu/ifu.sv

@@ -145,7 +145,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   logic [LINELEN-1:0]          FetchBuffer;
   logic [31:0]                 ShiftUncachedInstr;
   // Debug scan chain
-  logic                        DSCR;
+  logic                        DSCR;                                     // Debug Scan Chain Register
   
   assign PCFExt = {2'b00, PCSpillF};
 

src/lsu/lsu.sv

@@ -158,9 +158,10 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic                  IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
   logic                  SelDTIM;                                // Select DTIM rather than bus or D$
   logic [P.XLEN-1:0]     WriteDataZM;
-  logic                  LSULoadPageFaultM, LSUStoreAmoPageFaultM;
+  logic 		 LSULoadPageFaultM;
+  logic                  LSUStoreAmoPageFaultM;
 
-  logic                  DSCR;
+  logic                  DSCR;                                   // Debug Scan Chain Register (DSCR)
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M

src/privileged/csrm.sv

@@ -94,10 +94,10 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   localparam TDATA1        = 12'h7A1;
   localparam TDATA2        = 12'h7A2;
   localparam TDATA3        = 12'h7A3;
-  localparam DCSR          = 12'h7B0;
-  localparam DPC           = 12'h7B1;
-  localparam DSCRATCH0     = 12'h7B2;
-  localparam DSCRATCH1     = 12'h7B3;
+  localparam DCSR          = 12'h7B0;  // Debug Control and Status Register 
+  localparam DPC           = 12'h7B1;  // Debug PC 
+  localparam DSCRATCH0     = 12'h7B2;  // Debug Scratch Register 0
+  localparam DSCRATCH1     = 12'h7B3;  // Debug Scratch Register 1
   // Constants
   localparam ZERO = {(P.XLEN){1'b0}};
   // when compressed instructions are supported, there can't be misaligned instructions