From 97cf2fdd239d922a1488492d31161cd92cf52e8d Mon Sep 17 00:00:00 2001 From: James Stine Date: Sun, 9 Jun 2024 10:32:13 -0500 Subject: [PATCH 1/3] update some comments on debug --- src/ieu/ieu.sv | 1 + src/lsu/lsu.sv | 7 ++++--- src/privileged/csrm.sv | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 33fe4f03d..dd5bedcd6 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -120,6 +120,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic BMUActiveE; // Bit manipulation instruction being executed logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active + // Debug Control and Status (debug spec) logic DSCR; controller #(P) c( diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 1fe0c5738..e00e75cad 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -101,7 +101,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( output logic DebugScanOut ); localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED; - localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess + localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer @@ -158,9 +158,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; - logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; + logic LSULoadPageFaultM; + logic LSUStoreAmoPageFaultM; - logic DSCR; + logic DSCR; // Debug Control and Status ///////////////////////////////////////////////////////////////////////////////////////////// // Pipeline for IEUAdr E to M diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 293b918e1..07dcfeffb 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -95,7 +95,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam TDATA2 = 12'h7A2; localparam TDATA3 = 12'h7A3; localparam DCSR = 12'h7B0; - localparam DPC = 12'h7B1; + localparam DPC = 12'h7B1; // Debug PC (DPC) localparam DSCRATCH0 = 12'h7B2; localparam DSCRATCH1 = 12'h7B3; // Constants From 42af10dabf2d36d1e29bd7b2b6b5f56992a134f9 Mon Sep 17 00:00:00 2001 From: James Stine Date: Sun, 9 Jun 2024 10:43:43 -0500 Subject: [PATCH 2/3] minor fix of DSCR naming comment --- src/ieu/ieu.sv | 33 ++++++++++++++++----------------- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- 3 files changed, 18 insertions(+), 19 deletions(-) diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index dd5bedcd6..6de57f56d 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -72,13 +72,13 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic [4:0] RdW, // Destination register input logic [P.XLEN-1:0] ReadDataW, // LSU's read data // Hazard unit signals - input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit - input logic FlushD, FlushE, FlushM, FlushW, // Flush signals - output logic StructuralStallD, // IEU detects structural hazard in Decode stage - output logic LoadStallD, // Structural stalls for load, sent to performance counters - output logic StoreStallD, // load after store hazard - output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction - output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions + input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit + input logic FlushD, FlushE, FlushM, FlushW, // Flush signals + output logic StructuralStallD, // IEU detects structural hazard in Decode stage + output logic LoadStallD, // Structural stalls for load, sent to performance counters + output logic StoreStallD, // load after store hazard + output logic CSRReadM, CSRWriteM, PrivilegedM, // CSR read, CSR write, is privileged instruction + output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions // Debug scan chain input logic DebugScanEn, input logic DebugScanIn, @@ -111,17 +111,16 @@ module ieu import cvw::*; #(parameter cvw_t P) ( // Forwarding signals logic [4:0] Rs1D, Rs2D; - logic [4:0] Rs2E; // Source registers - logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers - logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages - logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic BranchSignedE; // Branch does signed comparison on operands - logic MDUE; // Multiply/divide instruction - logic BMUActiveE; // Bit manipulation instruction being executed - logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active + logic [4:0] Rs2E; // Source registers + logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers + logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages + logic MemReadE, CSRReadE; // Load, CSRRead instruction + logic BranchSignedE; // Branch does signed comparison on operands + logic MDUE; // Multiply/divide instruction + logic BMUActiveE; // Bit manipulation instruction being executed + logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active - // Debug Control and Status (debug spec) - logic DSCR; + logic DSCR; // Debug Scan Chain Register controller #(P) c( .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD, diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index e10658628..637fa231d 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -145,7 +145,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic [LINELEN-1:0] FetchBuffer; logic [31:0] ShiftUncachedInstr; // Debug scan chain - logic DSCR; + logic DSCR; // Debug Scan Chain Register assign PCFExt = {2'b00, PCSpillF}; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index e00e75cad..cdd4c1ed6 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -161,7 +161,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic LSULoadPageFaultM; logic LSUStoreAmoPageFaultM; - logic DSCR; // Debug Control and Status + logic DSCR; // Debug Scan Chain Register (DSCR) ///////////////////////////////////////////////////////////////////////////////////////////// // Pipeline for IEUAdr E to M From 67a6e3a24b0d73e56703adf2f3fabebfaa0749af Mon Sep 17 00:00:00 2001 From: James Stine Date: Sun, 9 Jun 2024 10:49:14 -0500 Subject: [PATCH 3/3] comment update in csrm.sv --- src/privileged/csrm.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 07dcfeffb..d5fede556 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -94,10 +94,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam TDATA1 = 12'h7A1; localparam TDATA2 = 12'h7A2; localparam TDATA3 = 12'h7A3; - localparam DCSR = 12'h7B0; - localparam DPC = 12'h7B1; // Debug PC (DPC) - localparam DSCRATCH0 = 12'h7B2; - localparam DSCRATCH1 = 12'h7B3; + localparam DCSR = 12'h7B0; // Debug Control and Status Register + localparam DPC = 12'h7B1; // Debug PC + localparam DSCRATCH0 = 12'h7B2; // Debug Scratch Register 0 + localparam DSCRATCH1 = 12'h7B3; // Debug Scratch Register 1 // Constants localparam ZERO = {(P.XLEN){1'b0}}; // when compressed instructions are supported, there can't be misaligned instructions