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Merge branch 'main' of https://github.com/stineje/cvw

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Matthew 2024-06-09 11:27:02 -05:00
commit 8e9b245af2
4 changed files with 25 additions and 24 deletions
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32
src/ieu/ieu.sv
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@ -72,13 +72,13 @@ module ieu import cvw::*; #(parameter cvw_t P) (
output logic [4:0] RdW, // Destination register
input logic [P.XLEN-1:0] ReadDataW, // LSU's read data
// Hazard unit signals
input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit
input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
output logic StructuralStallD, // IEU detects structural hazard in Decode stage
output logic LoadStallD, // Structural stalls for load, sent to performance counters
output logic StoreStallD, // load after store hazard
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions
input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit
input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
output logic StructuralStallD, // IEU detects structural hazard in Decode stage
output logic LoadStallD, // Structural stalls for load, sent to performance counters
output logic StoreStallD, // load after store hazard
output logic CSRReadM, CSRWriteM, PrivilegedM, // CSR read, CSR write, is privileged instruction
output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions
// Debug scan chain
input logic DebugScanEn,
input logic DebugScanIn,
@ -111,16 +111,16 @@ module ieu import cvw::*; #(parameter cvw_t P) (
// Forwarding signals
logic [4:0] Rs1D, Rs2D;
logic [4:0] Rs2E; // Source registers
logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
logic MemReadE, CSRReadE; // Load, CSRRead instruction
logic BranchSignedE; // Branch does signed comparison on operands
logic MDUE; // Multiply/divide instruction
logic BMUActiveE; // Bit manipulation instruction being executed
logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active
logic [4:0] Rs2E; // Source registers
logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
logic MemReadE, CSRReadE; // Load, CSRRead instruction
logic BranchSignedE; // Branch does signed comparison on operands
logic MDUE; // Multiply/divide instruction
logic BMUActiveE; // Bit manipulation instruction being executed
logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active
logic DSCR;
logic DSCR; // Debug Scan Chain Register
controller #(P) c(
.clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,

2
src/ifu/ifu.sv
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@ -145,7 +145,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [LINELEN-1:0] FetchBuffer;
logic [31:0] ShiftUncachedInstr;
// Debug scan chain
logic DSCR;
logic DSCR; // Debug Scan Chain Register
assign PCFExt = {2'b00, PCSpillF};

7
src/lsu/lsu.sv
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@ -101,7 +101,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
output logic DebugScanOut
);
localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
@ -158,9 +158,10 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
logic SelDTIM; // Select DTIM rather than bus or D$
logic [P.XLEN-1:0] WriteDataZM;
logic LSULoadPageFaultM, LSUStoreAmoPageFaultM;
logic LSULoadPageFaultM;
logic LSUStoreAmoPageFaultM;
logic DSCR;
logic DSCR; // Debug Scan Chain Register (DSCR)
/////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline for IEUAdr E to M

8
src/privileged/csrm.sv
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@ -94,10 +94,10 @@ module csrm import cvw::*; #(parameter cvw_t P) (
localparam TDATA1 = 12'h7A1;
localparam TDATA2 = 12'h7A2;
localparam TDATA3 = 12'h7A3;
localparam DCSR = 12'h7B0;
localparam DPC = 12'h7B1;
localparam DSCRATCH0 = 12'h7B2;
localparam DSCRATCH1 = 12'h7B3;
localparam DCSR = 12'h7B0; // Debug Control and Status Register
localparam DPC = 12'h7B1; // Debug PC
localparam DSCRATCH0 = 12'h7B2; // Debug Scratch Register 0
localparam DSCRATCH1 = 12'h7B3; // Debug Scratch Register 1
// Constants
localparam ZERO = {(P.XLEN){1'b0}};
// when compressed instructions are supported, there can't be misaligned instructions