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Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script.

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This commit is contained in:
Rose Thompson 2024-09-03 21:03:38 -07:00
parent 33435bfb6a
commit 8c99e28c8b
2 changed files with 2 additions and 2 deletions
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2
fpga/generator/Makefile
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@ -73,7 +73,7 @@ PreProcessFiles:
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
# build the Zero stage boot loader (ZSBL) # build the Zero stage boot loader (ZSBL)
.PHONE: zsbl .PHONY: zsbl
zsbl: zsbl:
$(MAKE) -C ../zsbl clean $(MAKE) -C ../zsbl clean
SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl

2
fpga/generator/ddr4-vcu118.tcl
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@ -1,7 +1,7 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set SYSTEMCLOCK $::env(CLOCK) set SYSTEMCLOCK $::env(SYSTEMCLOCK)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4