diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 88af463c7..7ffd9f163 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -73,7 +73,7 @@ PreProcessFiles:
 	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
 
 # build the Zero stage boot loader (ZSBL)
-.PHONE: zsbl
+.PHONY: zsbl
 zsbl:
 	$(MAKE) -C ../zsbl clean
 	SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl 
diff --git a/fpga/generator/ddr4-vcu118.tcl b/fpga/generator/ddr4-vcu118.tcl
index 104dfb80d..057c59c6f 100644
--- a/fpga/generator/ddr4-vcu118.tcl
+++ b/fpga/generator/ddr4-vcu118.tcl
@@ -1,7 +1,7 @@
 
 set partNumber $::env(XILINX_PART)
 set boardName $::env(XILINX_BOARD)
-set SYSTEMCLOCK $::env(CLOCK)
+set SYSTEMCLOCK $::env(SYSTEMCLOCK)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4