From 8b85a5c34ab369cff62b4e25cf22f1a676d62fa4 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 6 Aug 2024 16:57:57 -0500 Subject: [PATCH] SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree. --- fpga/constraints/constraints-ArtyA7.xdc | 8 ++- fpga/src/fpgaTopArtyA7.sv | 3 +- fpga/zsbl/boot.c | 2 +- linux/Makefile | 2 +- .../buildroot-2023.05.1/linux.config | 13 ++--- linux/devicetree/wally-artya7.dts | 51 ++++++++++++++----- 6 files changed, 55 insertions(+), 24 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index b8f98d430..394c58dda 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -35,6 +35,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}] set_max_delay -to [get_ports {GPO[*]}] 20.000 + set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}] @@ -106,18 +107,21 @@ set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}] + set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] + #set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10 set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000 diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 712f67869..5d038ad0f 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -47,6 +47,7 @@ module fpgaTop output SDCCmd, output SDCCS, input SDCCD, + input SDCWP, // Memory signals inout [15:0] ddr3_dq, @@ -194,7 +195,7 @@ module fpgaTop wire mmcm1_locked; - assign GPIOIN = {28'b0, GPI}; + assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI}; assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index e47b34e2f..52473ab46 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -159,7 +159,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { /* print_uart("\r\n"); */ // Intialize the SD card - init_sd(SYSTEMCLOCK, 3000000); + init_sd(SYSTEMCLOCK, 5000000); ret = gpt_load_partitions(); } diff --git a/linux/Makefile b/linux/Makefile index 6f7b6c7fb..b0b15ce7b 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -102,7 +102,7 @@ $(IMAGES)/busybox: # Generating new Buildroot directories -------------------------------- # This directive should be run as: make install BUILDROOT=path/to/buildroot -download: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) +download: $(WALLYBOARD) cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config # CONFIG DEPENDENCIES 2023.05.1 --------------------------------------- diff --git a/linux/buildroot-config-src/buildroot-2023.05.1/linux.config b/linux/buildroot-config-src/buildroot-2023.05.1/linux.config index e348cde78..047be24c2 100644 --- a/linux/buildroot-config-src/buildroot-2023.05.1/linux.config +++ b/linux/buildroot-config-src/buildroot-2023.05.1/linux.config @@ -2,7 +2,7 @@ # Automatically generated file; DO NOT EDIT. # Linux/riscv 6.6.0 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3-dirty) 12.3.0" +CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3) 12.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=120300 CONFIG_CLANG_VERSION=0 @@ -1042,7 +1042,7 @@ CONFIG_MMC_BLOCK_MINORS=8 # # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_SPI is not set +CONFIG_MMC_SPI=y # CONFIG_MMC_DW is not set # CONFIG_MMC_USDHI6ROL0 is not set # CONFIG_MMC_CQHCI is not set @@ -1455,7 +1455,7 @@ CONFIG_CRYPTO_HASH2=y # CONFIG_CRYPTO_POLY1305 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set +CONFIG_CRYPTO_SHA256=y # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3_GENERIC is not set @@ -1527,13 +1527,14 @@ CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines # CONFIG_CRC_CCITT is not set CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set # CONFIG_CRC64_ROCKSOFT is not set -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y @@ -1542,7 +1543,7 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_BIT is not set # CONFIG_CRC64 is not set # CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set +CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set # CONFIG_RANDOM32_SELFTEST is not set @@ -1599,7 +1600,7 @@ CONFIG_PRINTK_TIME=y # CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DYNAMIC_DEBUG_CORE is not set diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 87933bcc0..99b8ff00d 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -5,11 +5,11 @@ #size-cells = <0x02>; compatible = "wally-virt"; model = "wally-virt,qemu"; - + chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "root=/dev/vda ro console=ttyS0,115200"; + bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7"; stdout-path = "/soc/uart@10000000"; }; @@ -51,6 +51,25 @@ compatible = "simple-bus"; ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x1312D00>; + clock-output-names = "xtal"; + }; + + gpio0: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <0x03>; + interrupts = <3>; + reg = <0x00 0x10060000 0x00 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; @@ -70,18 +89,24 @@ #address-cells = <0x00>; }; - mmc@13000 { - interrupts = <0x14>; - compatible = "riscv,axi-sd-card-1.0"; - reg = <0x00 0x13000 0x00 0x7F>; - fifo-depth = <256>; - bus-width = <4>; + spi@13000 { + compatible = "sifive,spi0"; interrupt-parent = <0x03>; - clock = <0x1312D00>; - max-frequency = <0x1312D00>; - cap-sd-highspeed; - cap-mmc-highspeed; - no-sdio; + interrupts = <0x14>; + reg = <0x0 0x13000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <5000000>; + voltage-ranges = <3300 3300>; + disable-wp; + // gpios = <&gpio0 6 1>; + }; }; clint@2000000 {