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Resolved a bug in the cache but there are still mismatches with the cache simulator.

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This commit is contained in:
Rose Thompson 2024-11-12 11:35:29 -06:00
parent 0cf7b2e45a
commit 8a4868ac57
3 changed files with 10 additions and 4 deletions
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6
sim/rv64gc_CacheSim.py
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@ -54,7 +54,8 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar
"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]
# arch64i is the most interesting case. Uncomment line below to run just that case
# tests64gc = ["arch64i"]
#tests64gc = ["arch64i"]
tests64gc = ["coverage64gc"]
cachetypes = ["ICache", "DCache"]
simdir = os.path.expandvars("$WALLY/sim")
@ -63,10 +64,11 @@ def main():
parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
args = parser.parse_args()
simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1"
testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null"
#cachecmd = "CacheSim.py 64 4 56 44 -f {} --verbose"
cachecmd = "CacheSim.py 64 4 56 44 -f {}"
mismatches = 0

6
src/cache/cacheway.sv vendored
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@ -175,7 +175,11 @@ module cacheway import cvw::*; #(parameter cvw_t P,
//if (reset) DirtyBits <= {NUMSETS{1'b0}};
if(CacheEn) begin
Dirty <= DirtyBits[CacheSetTag];
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) begin
DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
if (CacheSetData == CacheSetTag) Dirty <= SetDirtyWay;
else Dirty <= DirtyBits[CacheSetTag];
end
end
end
end else assign Dirty = 1'b0;

2
testbench/common/loggers.sv
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@ -217,7 +217,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
"NULL";
end
assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | AccessTypeString == "C" | AccessTypeString == "L") &
~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &