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Merge pull request #1155 from davidharrishmc/dev

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Added compressed illegal instruction coverage ExceptionsZc
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Jordan Carlin 2024-11-29 15:07:05 -08:00 committed by GitHub
commit 89679aa231
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5 changed files with 15 additions and 9 deletions
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1
config/rv32gc/coverage.svh
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@ -45,3 +45,4 @@
`include "EndianM_coverage.svh" `include "EndianM_coverage.svh"
`include "EndianS_coverage.svh" `include "EndianS_coverage.svh"
`include "ExceptionsM_coverage.svh" `include "ExceptionsM_coverage.svh"
`include "ExceptionsZc_coverage.svh"

16
config/rv32gc/imperas.ic
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@ -9,7 +9,7 @@
#--showcommands #--showcommands
# Core settings # Core settings
--variant RV32GC # for RV32GC --variant RV32GCK # for RV32GC
--override cpu/priv_version=1.12 --override cpu/priv_version=1.12
--override cpu/user_version=20191213 --override cpu/user_version=20191213
# arch # arch
@ -59,7 +59,7 @@
#--override cpu/instret_undefined=T #--override cpu/instret_undefined=T
#--override cpu/hpmcounter_undefined=T #--override cpu/hpmcounter_undefined=T
## context registers not implemented # context registers not implemented
#--override cpu/scontext_undefined=True #--override cpu/scontext_undefined=True
#--override cpu/mcontext_undefined=True #--override cpu/mcontext_undefined=True
@ -69,9 +69,14 @@
#--override cpu/Zicfilp=F #--override cpu/Zicfilp=F
--override cpu/trigger_num=0 # disable CSRs 7a0-7a8 --override cpu/trigger_num=0 # disable CSRs 7a0-7a8
--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions # For code coverage, don't produce pseudoinstructions
--override no_pseudo_inst=T
--override show_c_prefix=T # Show "c." with compressed instructions # Show "c." with compressed instructions
--override show_c_prefix=T
# nonratified mnoise register not implemented
--override cpu/mnoise_undefined=T
# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
#--override cpu/ecode_mask=0x8000000F # for RV32 #--override cpu/ecode_mask=0x8000000F # for RV32
@ -80,7 +85,8 @@
# Debug mode not yet supported # Debug mode not yet supported
--override cpu/debug_mode=none --override cpu/debug_mode=none
# Zkr entropy source and seed register not supported.
--override cpu/Zkr=F
--override cpu/reset_address=0x80000000 --override cpu/reset_address=0x80000000

1
config/rv64gc/coverage.svh
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@ -44,6 +44,7 @@
`include "EndianM_coverage.svh" `include "EndianM_coverage.svh"
`include "EndianS_coverage.svh" `include "EndianS_coverage.svh"
`include "ExceptionsM_coverage.svh" `include "ExceptionsM_coverage.svh"
`include "ExceptionsZc_coverage.svh"
// `include "RV64VM_PMP_coverage.svh" // `include "RV64VM_PMP_coverage.svh"
// `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_VM_coverage.svh"
// `include "RV64CBO_PMP_coverage.svh" // `include "RV64CBO_PMP_coverage.svh"

4
config/rv64gc/imperas.ic
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@ -73,7 +73,7 @@
# Show "c." with compressed instructions # Show "c." with compressed instructions
--override show_c_prefix=T --override show_c_prefix=T
# nonratified mnosie register not implemented # nonratified mnoise register not implemented
--override cpu/mnoise_undefined=T --override cpu/mnoise_undefined=T
# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
@ -86,8 +86,6 @@
# Zkr entropy source and seed register not supported. # Zkr entropy source and seed register not supported.
--override cpu/Zkr=F --override cpu/Zkr=F
--override cpu/reset_address=0x80000000 --override cpu/reset_address=0x80000000
--override cpu/unaligned=T # Zicclsm (should be true) --override cpu/unaligned=T # Zicclsm (should be true)

2
testbench/common/ramxdetector.sv
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@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) (
/* verilator lint_off WIDTHXZEXPAND */ /* verilator lint_off WIDTHXZEXPAND */
if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
/* verilator lint_on WIDTHXZEXPAND */ /* verilator lint_on WIDTHXZEXPAND */
$display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests."); $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.");
$display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM); $display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
//$stop; //$stop;
end end